JPH05109892A - Designing method of interconnection of integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a chip area, to perform a high-speed processing operation, to guaranteee a 100% interconnection, to save a memory space and to reuse the result of an interconnection passing over a macro by a method wherein a net which is passed over the macro is extracted at each macro on the basis of an approximate interconnection route and the interconnection passing over the macro is executed. CONSTITUTION:When a layout inside a macro D out of macros is changed in a chip which has been laid out, its interconnection is used as it is in a macro E because an interconnection passing over the macro has already been executed. The interconnection passing over the macro is executed only in a macro F which has been changed. At this time, the interconnection is executed by using an interconnection layer which has not been used when the layout inside the macro is designed. The difference from an original net list is processed with reference to a net which has been successful, and a net list between macros is found. An interconnection inside a channel is executed to a pin pair which has failed to pass over the macros by means of a layout on a chip level. Consequently, the processing time of the title method can be halved as compared with an inter-connection where the position of a macro has been fixed to the chip as a whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring design method for an integrated circuit, and more particularly, in a chip layout design, it is also used as a wiring area on a macro to reduce a channel area which is a wiring area in the macro to achieve high density. The present invention relates to a wiring processing method for obtaining a chip layout.

[0002]

2. Description of the Related Art Conventionally, when performing a through wiring on a macro,
Targeting the entire chip surface with the macro position fixed,
Wiring was performed according to the processing flow as shown in FIG.

First, the floor plan 56 is performed, and the nets on the macro passage 57 are classified into the inter-channel nets 58 and the macro passage nets 59. next,
For the inter-channel net, the rough wiring 60 and the detailed wiring 61
I do. Finally, the macro-passable net wiring 62 is performed on the finely-wired chip.

When a chip is laid out, the entire surface of the chip is targeted as shown in FIG. 13, and the macro that cannot pass over the macro and the wiring prohibited area in the macro are avoided with the macro position fixed. Was wired to.

[0005]

In the above-mentioned conventional macro above-passage wiring method, wiring is performed with the position of the macro fixed while targeting the entire surface of the chip.

Therefore, for (1) there is a macro that cannot pass over the macro, and (2) there is a wiring prohibited area in the macro, these wiring prohibited areas are avoided. I have to wire. Therefore, there is a problem that a large amount of data must be handled at one time, a lot of processing time is required, and 100% wiring cannot be guaranteed.

[0007]

According to the wiring design method for an integrated circuit of the present invention, a layout design is performed for each macro on the basis of a rough wiring path in consideration of a wiring passing over a macro forming a circuit. A partial route of the rough wiring route passing through the macro is extracted, and detailed wiring corresponding to the partial route is realized by the above-macro-passage wiring mainly using a wiring layer which is not used in layout design in the macro.

[0008]

[Operation] Since the passing wiring process is performed for each macro,
(1) Since processing is performed in macro units, a large amount of memory space is not required at one time. (2) High-speed processing is possible for one macro, and overall wiring processing can be speeded up. (3) Wiring is performed with the macro position fixed for the entire surface of the chip, whereas there is no need to fix the macro position at the time of wiring, so 100% wiring is guaranteed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a processing flow chart showing an embodiment of the present invention. First, the floor plan 1 is performed, and then, on the basis of the route 3 obtained by the rough wiring process considering the above-macro wiring, the partial route of the rough wiring route passing through the macro is extracted for each macro. For each macro, the detailed wiring corresponding to the partial path is performed by the macro passing wiring 4 using the wiring passing on the macro. At this time, the wiring layer which is not used in the layout design in the macro is mainly used. Finally, chip level inter-channel wiring 5
Then, the layout design is finished.

FIG. 2 is a diagram of the chip model of the present invention. Of the macros 6 to 9, macros 6 and 9 are macros that cannot pass over the macros. As the wiring layers, first / third metal layers are used in the X direction, poly layers, and second / fourth metal layers are used in the Y direction. Poly layer, 1st / 2nd for macro wiring
The metal layer (partly the third metal layer) is used, and the first to fourth metal layers are used for the inter-macro wiring. The on-macro pass wiring is the third / fourth metal layer (the first / second metal layer is also used depending on the case).

FIG. 3 is a detailed processing flow of the macro pass wiring portion. First, preprocessing 13 creates a netlist 14 for passing each macro and information 15 for controlling the above-macro passing router. Next, on the basis of the on-macro passage netlist 14, for each macro, the third metal layer and the fourth metal layer are mainly used and the on-macro passage wiring 16 is used.
I do. At this time, the result (success / failure of connection) of the macro passing wiring is output as the wiring information 17. Finally, in post-processing 19, for the nets passing over the macro, the difference from the original net list is processed to obtain the inter-macro net list 20. Channel wiring 21 at the chip level is performed according to this netlist.

Now, let us consider laying out a schematic wiring path 22 in which the above-macro wiring is taken into consideration as shown in FIG.

First, as preprocessing, a netlist through which each macro is passed is extracted from this route information and represented as a pin pair set. Hypothesis terminals are provided on the outer shape of each macro as shown in FIG. 5 corresponding to this netlist. The hypothetical terminal position is determined in consideration of the grid of each wiring layer based on the design rule 23. If there is a real external terminal with the same potential near the hypothetical terminal position, it may be used. In addition, in order to perform on-macro pass wiring, grid spacing of each wiring layer, cost definition of wiring and through holes, and the like are also output.

Next, as shown in FIG. 6, based on the information for controlling the macro top passage netlist and the macro top passage router, the third metal layer and the fourth metal layer are mainly used for wiring on the macro. To do. When an actual external terminal is selected during preprocessing, the wiring in the macro connected to it is determined by equipotential tracing, and the entire wiring becomes the terminal. At this time, since the actual external terminal is usually the first / second metal,
The through wiring on the macro is performed using the first to fourth metals. Also, the success / failure of the passing wiring on the macro is output to each pin pair as wiring information.

Finally, the hypothetical terminals are converted into real terminals for each pin pair for which the above-macro pass wiring is successful, and the inter-macro netlist is obtained. The original net is {s, t}, the route is (s, α, β, t) (macro pass wiring between α and β)
Then, the hypothetical terminals α and β are changed to real terminals a and b, respectively, the difference from the macro pass wiring portion is obtained, and the netlist is converted into {s, a}, {b, t}. Further, conversion is not performed for the pin pair that has failed to pass on the macro, and in-channel wiring is performed in the layout at the next chip level as shown in FIG.

As described above, it is possible to perform the above-macro passage wiring for each macro. Since the over-macro wiring processing is performed for each macro unit instead of the conventional batch processing of the entire chip, the amount of data that must be handled at one time is limited to the information based on the layout result in one macro. Be done. Therefore, it is possible to perform processing with a smaller memory space as compared with the conventional method.

Next, a second embodiment will be described with reference to the drawings.

Consider the chip of three macros shown in FIG.

When the conventional macro through wiring is not performed, as shown in FIG. 8, there are 4 tracks in the horizontal direction (2 tracks for the left channel and 2 tracks for the right channel) and 3 tracks in the vertical direction (upper channel). 2 tracks, 1 track for the lower channel). If all the above-macro passing wirings are successful by using the above-mentioned macro above-passing wiring method, wiring can be performed with 0 tracks as shown in FIG.

[0021] As a result of performing the above-macro passage wiring for the data of the number of macros 16 (10 macros that can pass on the macro) and the number of nets 2362, the above-mentioned macro upper passage wiring is not performed, and the 3.5 layers The area of the wiring region is reduced by about 18% as compared with the layout result of the four-layer wiring between macros.

As described above, the chip area can be greatly reduced by using the above-macro pass multilayer wiring method of the present invention.

A third embodiment of the present invention will be described with reference to the drawings.

Consider a case where the layout in the macro of the macro D is changed in the laid-out chip as shown in FIG. Since the macro E has already been wired on the macro, the wiring result is used as it is. Only the changed macro F is routed on the macro as shown in FIG. The difference between the successful net and the original netlist is processed to obtain the inter-macro netlist. For the pin pair that has failed to pass on the macro, in-channel wiring is performed next with a layout at the chip level as shown in FIG.

As described above, by changing only the macro to be changed and reusing the wiring information of the macro that is not changed, the layout design at the chip level is possible.

For two macros that can pass over the macro, only one macro needs to be changed. Therefore, wiring can be performed in half the processing time as compared with the method of wiring the entire surface of the chip with the macro position fixed.

[0027]

As described above, according to the present invention, when the macro pass wiring is performed, the wiring is performed for each macro while the macro position is fixed while the macro position is fixed. Therefore, (1) the processing for one macro is fast, and the overall wiring processing can be speeded up.

(2) It is not necessary to fix the macro position at the time of wiring, and 100% wiring is guaranteed.

(3) Since a macro unit is used for processing, a large amount of memory space is not required.

(4) Since the passing wiring pattern is held for each macro, the result of passing wiring on the macro can be reused. The chip area is significantly reduced as compared with the wiring method that does not pass over the macro.

[Brief description of drawings]

FIG. 1 is a processing flow chart showing an embodiment of the present invention.

FIG. 2 is a diagram of a chip model of one embodiment.

FIG. 3 is a processing flow diagram of the above-macro passing wiring according to the embodiment.

FIG. 4 is a diagram showing a result of schematic wiring in consideration of an on-macro passage wiring according to an embodiment.

FIG. 5 is a diagram of an on-macro passage netlist according to an embodiment.

FIG. 6 is a diagram showing a result of the on-macro passing wiring according to the embodiment.

FIG. 7 is a diagram of an inter-macro netlist according to an embodiment.

FIG. 8 is a diagram of a conventional chip layout.

FIG. 9 is a diagram of a chip layout according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a result of the on-macro passage wiring according to the third embodiment.

FIG. 11 is a diagram of an inter-macro netlist according to the third embodiment.

FIG. 12 is a diagram of a processing flow in the related art.

FIG. 13 is a diagram of a chip layout in the related art.

[Explanation of symbols]

1 Floor Plan 2 General Wiring 3 Routing 4 Macro Passing Wiring 5 Chip Layout 6, 7, 8, 9 Macro 10, 11, 12 Cell Row 13 Pre-Processing 14 Macro Passing Netlist 15 Execution Designating Information 16 Macro Passing Wiring 17,18 Wiring information 19 Post-processing 20 Net list between macros 21 Chip layout 22 Routing 23 Design rules 24, 34, 50, 63 Chips 25, 35, 51, 64 Macro A 26, 36, 52, 65 Macro B 27 , 37, 53, 66 Macro C 28, 30, 32, 38, 67 Macro D 29, 31, 33, 39, 49, 55, 68 Macro E 48, 54 Macro F 40, 44 Chip 41, 42, 43, 45 , 46, 47 Macro 56 Floor plan 57 Macro passing net extraction 58 Inter-channel net 59 Macro-passable net 60 General wiring 61 Detailed wiring 62 Chip layout

Claims (1)

[Claims] 1. In a layout design, a partial route of a rough wiring route that passes through the macro is extracted for each macro based on a rough wiring route that takes into consideration that the wiring passes over a macro that constitutes a circuit. A wiring method for an integrated circuit, characterized in that detailed wiring corresponding to a partial path is realized by an on-macro passing wiring which mainly uses a wiring layer which is not used during layout design in the macro.