JPH05108578A - Information processing system - Google Patents

Abstract

PURPOSE:To avoid the bottle neck of a shared bus at the information processing system connecting plural processors through an information transmission line. CONSTITUTION:Plural sub units 1 and 1a are provided in the information processing system, and signal transmission lines 5 and 5a of the respective sub units are connected through interface means 6 and 6a to a common signal transmission line 7. Tag bits are set corresponding to address blocks in main memories 4 and 4a and cach memories 30 and 30a in the respective sub units and based on the information of the tag bits of the address blocks requested from processors 20 and 20a, the interface means controls whether a packet is transmitted from a certain sub unit through the common signal transmission line to the other sub unit or not. Thus, processings can be independently executed at the respective sub units, saturation in the signal transmission line can be prevented, and the consistency of the entire system is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system in which a plurality of processors are connected by a plurality of information transmission paths, and more particularly to an information processing system for speeding up processing and reducing traffic on the information transmission paths. Is.

[0002]

2. Description of the Related Art Conventionally, as an information processing system in which a plurality of processors are connected via an information transmission path, a system configuration called a shared bus / shared memory configuration as shown in FIG. 8 is generally adopted.

In FIG. 8, reference numeral 81 is a group of processors sharing a shared bus 83, and reference numeral 82 is to attach instructions and data to the processor group 81 and simultaneously reduce traffic on the shared bus 83. Is a cache memory group, and 84 is a memory shared by the processor group 81.

In the system shown in FIG. 8, if the data corresponding to the address requested for the data access from the processor group 81 is not in the cache memory associated with the processor requesting the data, the memory is used. A read request packet is issued to the memory 84 to read the data corresponding to the requested address from 84.

In the system as described above, when the number of processors n increases, the shared bus 83 becomes a bottleneck (known as "bus saturation") of request packet transfer from each processor. , There was a drawback that the increased processor performance could not be effectively utilized for system performance.

[0006]

SUMMARY OF THE INVENTION The present invention avoids the bottleneck of the shared bus as described above and can connect a large number of processors, and even when a large number of processors are connected, the processor It is an object of the present invention to provide an information processing system that can effectively utilize performance for system performance. More specifically, data that constitutes a sub-unit that includes a processor, cache memory, and main memory inside, and that hierarchically connects each sub-unit with multiple information transmission paths to access the sub-unit. The request aims to provide an information processing system configured so as not to affect the outside of the subunit.

[0007]

In order to achieve the above object, the information processing system of the present invention uses a first information transmission line in which data is transferred in packets between a cache memory and a main memory attached to a processor. A plurality of sub-units each connected to each other, and a tag indicating whether or not the data in the address block is the latest data for each address block divided in the main memory and the cache memory. Means for storing bits and interface means for connecting the plurality of sub-units to a second information transmission line for data transfer in packets, the tag being provided when the packets are generated inside the sub-units .Determining the state of the bit and storing it in the cache memory and main memory inside the subunit. Characterized by providing an interface means for sending the packet only if there is no latest data to the sub-unit outside to dress block.

[0008]

In the present invention, a plurality of sub-units are provided in the information processing system, and the signal transmission lines of each sub-unit are connected to the common signal transmission line via the interface means. Then, the tag bit is set corresponding to the address block in the main memory and the cache memory provided in each sub unit, and based on the information of the tag bit of the address block requested by the processor, By interface means
It controls whether or not a packet is transmitted from a certain subunit to another subunit via a common signal transmission path. As a result, processing can be performed independently in each sub unit, saturation in the signal transmission path can be prevented, and the consistency of the entire system is maintained. Also, unnecessary packets will not be sent to other subunits.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention will be specifically described below with reference to the drawings with reference to the drawings. First, a schematic configuration of an embodiment of the information processing system of the present invention will be described. In FIG. 1, reference numerals 1 and 1a represent units of a sub-unit in the present invention, and in the sub-unit, a processor group 2 and 2a for performing information processing
Cache memory groups 3, 3 that supply data at high speed
a, memory units 4 and 4a that constitute a part or all of the main memory for storing instructions and data, information transmission path 5,
There is 5a. In addition, 20, 20a is a processor, 30,
30a is a cache memory.

The sub-units 1 and 1a are bus interface units (hereinafter referred to as BIU).
6, 6a connect to the information transmission line 7 provided outside the sub unit connecting between the plurality of sub units 1 and 1a. The information transmission paths 5, 5a and 7 are 6 in this embodiment.
The signals have the same configuration with a 4-bit width, and information is transmitted by the same protocol.

In FIG. 1, for simplicity, only four sets of processor groups and cache memory groups are shown in each sub-unit. However, it is possible to have an arbitrary number of sets inside each sub-unit. It is possible. Also,
Although only one set of the memory unit 4 is shown in FIG. 1, it is possible to hold an arbitrary number of sets in the sub unit. Further, although FIG. 1 shows a system in which the information transmission paths 5 and 7 are two-layered, the present invention is not limited to this, and the information transmission paths of two or more arbitrary levels and the information transmission. It is possible to have a hierarchy of paths in the system.

Cache memory groups 3 and 3 in FIG.
a, the memory units 4, 4a are information transmission lines 5, 5a,
Data is stored in address block units, which are the units of information transmission on the above 7, and a tag indicating that the data in each address bit is the latest corresponding to each address block. Each has its own bit. The tag bit associated with the memory unit 4, 4a may be in the same unit as the memory unit 4, 4a or may be external to the memory unit 4, 4a. In the example shown in FIG. 1, it is stored in the tag units 8 and 8a connected to the information transmission lines 5 and 5a.

If the tag bit on the cache memory is set, then that cache memory was the last to update the data for that address block, and the updated data for that address block is still relevant. Indicates that the memory unit in the system that holds the address block has not been reflected, and if the tag bit associated with the memory unit is set, the data in that memory unit is up to date. That is, there is no cache memory or memory unit holding the latest data corresponding to the address block other than that memory unit.

FIG. 2 shows a conceptual diagram of tag bits stored in the tag unit 8. In the figure, the address block unit 21 is divided into data transfer units on the information transmission paths 5 and 7, and the tag block unit 21 corresponds to each address block.
Bit 22 is attached. This tag bit 22 is stored in the tag unit 8. Although FIG. 2 shows an example where the address space is 32 bits and the address block is divided into units of 64 bytes, the present invention is not limited to this.

Data transfer on the information transmission lines 5 and 7 in FIG. 1 is performed by a combination of the data transfer request packet and the response packet shown in FIG. In FIG. 3, (a)
Shows an example of a read request packet when the cache memory reads data from the memory unit,
(B) shows an example of a response packet corresponding to the read request packet. Similarly, (c) is the processor 20, 20.
FIG. 3D shows an example of a write request packet when a writes data to data shared by a plurality of cache memories 30 and 30a in the cache memory groups 3 and 3a. FIG. Shows an example of a response packet to the. Further, (e) shows an example of a write-back request packet in the case of writing back data corresponding to a certain address block existing in the cache memory 30, 30a to the memory, and (f) shows the write-back request packet. Shows an example of a response packet to the.

As shown in FIG. 4, the header portion of FIGS. 3A to 3F includes a packet type, an address field,
It has fields such as request unit and number.

The packet type field indicates the read / write discrimination of the packet transmitted on the information transmission path, the type of the request / response packet, and the like. The address field indicates the address of the head data of the data in the packet. The request unit number field is a unique number in the system of the unit that sent the request packet. The header portion of the response packet has a packet type indicating the response packet corresponding to the request packet, the same address field as the request packet, and the request unit number field.

The information transmission paths 5, 5a, 7 shown in FIG. 1 have tag signal lines (not shown in FIG. 1) as their constituent elements. The tag signal line is provided in parallel independently of the signal line for packet transmission.

The request packet is an information transmission path 5, 5a,
Cache memory 30, 30
The tag value associated with the address block indicated by the address field of the packet header is output to the tag signal line from the tag bits associated with the memory units 4 and 4a. This processing is performed by the cache memories 30 and 30a and the tag units 8 and 8a. The tag value output to the tag signal line is wired-OR with the output of another subunit on the tag signal line.

BIUs 6 and 6a shown in FIG.
Whether or not the request packet on the information transmission path 5, 5a is to be sent to the information transmission path 7 outside the subunit 1 is determined by the tag signal line value at the time when the request packet is sent on the 5a.

When the tag signal line of the information transmission line 5 is asserted, the request packet on the information transmission line 5 is not sent to the information transmission line 7, and the tag signal line of the information transmission line 5 is When negated, the request packet on the information transmission line 5 is sent to the information transmission line 7. That is, the request packet is sent to the information transmission line 7 only when there is no data of the requested address in the same subunit 1.

Details of the tag unit 8 realized separately from the memory unit shown in FIG. 1 will be described with reference to the internal structure diagram shown in FIG.

In FIG. 5, reference numeral 51 is an address register for latching a packet header section address field for designating an address block of a request packet transmitted on the information transmission line 5 (or 7), Similarly, 52 is a packet type register for latching the packet type field of the packet header section, and 53 is an address managed by the tag unit 8.
It is an address space register for holding address information for designating a space inside the tag unit 8. In the address space register 53, an address range to be managed by the tag unit 8 when the system is started up is set.

Further, in FIG. 5, reference numeral 54 is a tag memory for holding a tag bit associated with an address block held by the memory unit, and in the present embodiment, an SRAM is used. In addition, tags
Symbols ADRS, DATA, R / attached to the memory 54
W and CS represent an address terminal, a data terminal, a read / write control terminal, and a chip select terminal, respectively.

Reference numeral 55 is a packet type decoder for generating a control signal from the contents of the packet type register 52 to the tag memory 54, and 56 is a tag type decoder.
The tag bit read from the memory is used as the information transmission line 5
(Or 7) is an output buffer for outputting to the tag signal line L1. Reference numeral 57 is a memory activation signal output buffer for outputting the output of the tag memory 54 to the memory activation signal line L2 directly connected to the memory unit 4. Reference numeral 58 is a selector and 59 is an address decoder. The output of the packet type decoder 55 is also supplied to the output buffers 56 and 57 and the selector 58 as a control signal.

In the present embodiment, the memory activation signal is
It is used to notify the memory unit 4 that the output on the tag signal line L1 of the information transmission line 5 comes from the tag unit attached to itself. This memory activation signal is output from the tag memory similarly to the tag signal, but the tag signal is logically ORed with the tag bit output from the cache memory 30 in another unit, that is, the sub-unit. Therefore, it is provided separately because it cannot be used as a direct memory activation signal.

For example, as an example, the address system of this system is 32-bit byte addressing,
Assuming that the capacity of the memory unit 4 is 4 megabytes and the unit of information transmitted on the information transmission lines 5 and 7 is 64 bytes, 32 request packets are transmitted to the information transmission lines 5 and 7. Having an address field of bits, memory unit 4 internally holds an address block identified by 64K or 16 bits. Therefore,
To access the tag bits associated with memory unit 4, 16 of the 32 bits of the address field of the request packet header are used. Since 32-bit byte addressing is used in this embodiment, it is possible to access an address space of 4 gigabytes. That is, since 1K of 4 megabyte memory units 4 can be designated, 10 bits are required to identify each memory unit. Therefore, in order to avoid a collision with an address block held by another memory unit 4a, the tag unit 8 has 26 (= 16).
+10) bit address is latched in the address register 51, the upper 10 bits are compared with the contents of the address space register 53, and when the upper 10 bits of the address and the contents of the address space register 53 match. Tag memory 54 that holds only tag bits
The lower 16 bits of the address are output to. The address decoder 59 controls this.

In the present embodiment, of the 32 bit address, 10 bits from 31st bit to 22nd bit (denoted by <31:22>. The same applies to the following.) Causes the memory unit 4 of 4 megabytes. Used to select,
16 bits from 21st bit to 6th bit (<2
1: 6>) is used to select the address block, and 6 bits from the 5th bit to the 0th bit (<
5: 0>) are used to select bytes within the address block. However, the 31st bit is the most significant bit and the 0th bit is the least significant bit.

Generally, in a system having a plurality of processors as shown in FIG. 1 and each processor having a write-back type cache memory,
Literature James Archibald and Jea
n-Loop Bear, "Cache Cohere
nce Protocols: Evaluation
Using a Multiprocessor S
"imulationModel" (ACM Trans
actions on Computer System
s, vol. 4, No. 4, Nov, '86,
pp. 273-298) or Paul Sw
eazey and Alan Jay Smith,
"A Class of Compatible C
ache Consistency Protocol
s and ther support by th
e IEEE Futurebus ”(The 13
th Annual International S
ymposium on Computer Arch
issue Conference Proce
edings, pp. 414-423), the data consistency control between the cache memories is performed by the cache consistency protocol. Although we will not describe the details of the cache consistency protocol here, if we describe the broadcast method consistency protocol in a very simple manner: (1) If a cache memory read miss occurs, The data is supplied from the cache memory that holds the latest data, (2) cache
When the data shared by the memory with another cache memory is updated, the updated data is sent to the data shared cache memory to update the data on all the shared cache memories, (3 ) The cache memory constantly monitors the transactions on the shared bus, and if the read miss notification transaction is detected on the shared bus and the latest data for the address is held internally, the memory reads the read miss notification transaction. Response to the request cache memory and send the latest data held by itself to the request cache memory.
Memory always monitors transactions on the shared bus,
When an update request for data shared with another cache memory is issued on the shared bus, it updates its own data with the update data attached to the update request,
Becomes

In order to suppress the response to the memory read / miss notification transaction in the consistency protocol (3), the latest data required by the unit connected on the information transmission line 5 (or 7) is held. It is necessary to notify the memory unit 4 of whether or not this has been done.

In the conventional shared bus type information processing system as shown in FIG. 8 in which all the functional units capable of holding data are connected to one information transmission line, a cache memory is used for this purpose. A tag bit (generally referred to as an Owner bit) indicating that the cache memory is the last to update the data in the address block, and the data held in the cache memory is the latest data. Is provided and the tag bit value attached to the cache memory is sent to the tag signal line on the information transmission path 83 when the request packet is sent on the information transmission path 83. Was sufficient for the purpose. However, if the information transmission path is segmented as shown in FIG. 1 for the purpose of avoiding the bottleneck of the shared bus, the requested latest data does not always exist in the subunit 1, and the requested latest data is It may occur in the memory unit 4a of the sub unit 1a or the cache memory group 3a. Tags attached to the memory unit
In a conventional system having no bits, if there is no cache memory holding the latest data in the sub unit 1, the memory unit 4 checks whether the data held by itself is the latest data. No determination can be made, and compatibility between segmentation of the information transmission line and cache consistency protocol becomes impossible.

Therefore, in the present invention, as will be described below, by providing a tag bit attached to the memory unit, it is possible to operate the system consistently even if the information transmission path is segmented. ..

The operation of the embodiment of the present invention shown in FIGS. 1 and 5 will be described below.

As an initial state, it is assumed that the address block on the memory unit 4 holds the latest data and the tag bit corresponding to the address block is set. The selector 58 is assumed to be switched to the data terminal side of the tag memory 54.

When there is no data in the cache memory in response to the data read request from the processor, the cache memory sends a data read request packet (see FIG. 3A) to the information transmission path 5. Requesting the data from the memory unit 4.

The tag unit 8 monitors the transaction on the information transmission path 5, and when the header part of the data read request packet (see FIG. 3A) is sent out on the information transmission path 5, The address field of the header section is stored in the address register 51 shown in FIG.
The type field is the packet type register 52.
Latched on. Only when the upper 10 bits of the block address latched in the address register 51 are compared with the contents of the address space register 53 and the upper 10 bits of the block address and the contents of the address space register 53 are equal. , 16-bit address <21: 6> corresponding to the address block is output from the address decoder 57.

1 output from the address decoder 59
6-bit address and packet type decoder 55
The contents of the tag memory 54 are read out by the output from and output to the tag signal line L1 of the information transmission line 5 via the output buffer 56.

The BIU 6 interfacing the information transmission path 5 inside the sub-unit and the information transmission path 7 outside the sub-unit receives the data read request when the tag signal line L1 on the information transmission path 5 is asserted. The packet is prevented from being output to the information transmission path 7.

At the same time, a memory activation signal is output from the memory activation signal line L2, and the value of the tag signal line attached to the information transmission path 5 by the memory activation signal is attached to the memory unit 4 by the tag attached to the memory unit 4.・ Notifying that the data is output from the unit 8, and notifying the memory unit 4
To the data read request packet. The data read from the memory unit 4 is broadcast to a unit inside the sub unit 1 as a response packet (see FIG. 3B).

In the memory unit 4, the header portion of the request packet is latched independently of the tag unit 8 and the memory access sequence is started by the memory activation signal. The memory access sequence here is a process of reading data from the memory unit 4 and broadcasting a response packet.

Next, when the processor writes to the data corresponding to the same address block as the above-mentioned address block at the time of the data read request in the cache memory, the data of the relevant data in the cache memory is written. The update and the tag flag associated with the address block of the cache memory are set, and at the same time, a write request packet is sent to the memory unit 4. That is, the updated data in the cache memory becomes the latest data in the system.

When the write request packet is sent out on the information transmission path 5, the tag unit 8 internally stores the address field and the packet type in the header portion of the write request packet as in the case of the data read request packet. The address register 51 and the packet type register 52 are set. Similar to the above, the comparison with the contents of the address space register 53 is performed. The packet type decoder 55 detects that the packet type register is a data update request packet and clears the contents of the tag memory of the address block indicated by the address field of the request packet header. ..

The BIU 6 also uses the information transmission line 7 to broadcast the write request packet in the system.
The write request packet is output above.

When a data read request is issued from the cache memory to an address block in which the tag bit associated with the memory unit 4 is cleared, the address block other than the cache memory requesting the data If the cache memory in which the tag bit of the block is set exists in the sub unit, the data of the address block in which the tag is set when the header part of the request packet is output. The tag bit is output from the retained cache memory to the tag signal line L1 attached to the information transmission line 5, and as a result, the tag signal line L1 attached to the information transmission line 5 is asserted, and the BIU 6 transmits the request packet to the information. Although the output on the transmission line 7 is suppressed, the memory activation signal is not asserted. Memory unit 4 does not supply data to the data read request packet. Data is supplied from the cache memory that asserted the tag signal line L1.

Similarly, a data read request is issued from the cache memory to the address block in which the tag bit associated with the memory unit 4 is cleared, and the tag bit is set inside the subunit 1. If there is no cache memory holding the address block, the tag signal line L1 attached to the information transmission line 5 is not set, and the request packet is sent out to the information transmission line 7 by the BIU 6. To be done.

The BIU 6 connected to the sub unit 1a which has detected the data read request packet on the information transmission path 7.
The a outputs the request packet to the information transmission line 5a in the subunit 1a.

Since it is guaranteed that there is always only one unit that holds the address block in which the tag bit is set in the system, in this embodiment, the unit in the sub unit 1a must be the corresponding unit. A response packet (see FIG. 3B) corresponding to the data request packet (see FIG. 3A) is returned. The response packet includes the data requested by the read request packet. The response packet is broadcast to the information transmission path 7 and the sub unit 1 in the sub unit 1a.

A cache memory which internally holds an address block in which a tag bit is set tries to write the address block in which the tag bit is set to the memory by the write-back request packet shown in FIG. In this case, when the header portion of the write-back packet is output on the information transmission line 5, the selector 58 is switched to the packet type decoder 55 side by the control of the packet type decoder 55, and the memory activation signal line L2. At the same time as the write start signal output from the packet type decoder 55 is output, the tag bit corresponding to the address block is set.

The BIUs 6 and 6a are exactly the same for packets sent from the information transmission lines 5, 5a to the information transmission line 7 and for packets output from the information transmission line 7 to the information transmission lines 5, 5a. Take action.

FIG. 6 shows another embodiment of the present invention, in which the tag unit 8 in FIG.
An example when the function of is built in is shown. Like this, tags
By configuring the function of storing bits in the memory unit 4, it is possible to reduce the load on the information transmission line 5 and further increase the data transfer bandwidth of the information transmission line 5. The operation of another embodiment shown in FIG.
Since it is the same as the embodiment shown in FIG.

In the embodiments shown in FIGS. 1 and 6, it is possible to judge whether or not the latest data is in the sub unit, so that the read request packet in which the tag bit is asserted. However, the read response packet is generally not issued immediately after the read request packet is received, so the cache or memory that issues the read response packet must read the read response packet. It is impossible to know whether the request packet is issued from inside the subunit or from outside the subunit, and it is possible to completely suppress the output of the read request packet to outside the subunit. It is not always sufficient in that it cannot be done. By comparing the request unit number field of the read request packet header part,
It is possible to judge whether or not the read request packet needs to be output to the outside, but in this case, the circuit scale becomes large.

FIG. 7 shows still another embodiment in which the above points are improved. The packet is broadcast in the header part of the packet transmitted on the information transmission lines 5 and 7 of FIG. Broadcast indicating whether or not
A flag field 71 is newly provided.

When the data read request packet from the cache memory group 3 is sent to the information transmission line 7 via the BIU 6, the BIU 6 sets the broadcast flag field 71 of the request packet header section. Then, the unit that internally holds the data of the address block in which the tag bit on the subunit 1a is set is broadcast by the request packet header section in the broadcast field of the response packet header section when the response packet is returned. -It is configured to copy the value of the field and send the packet. This allows BIUs connected to subunits 1 and 1a
It becomes possible for 6 and 6a to more strictly check whether or not the read request response packet should be transmitted to the outside of the subunits 1 and 1a.
It is possible to reduce the number of packets.

[0054]

According to the present invention, by providing the tag bit attached to the memory unit, the system can be operated without contradiction even if the information transmission path is segmented. This solves the problem of shared bus saturation and prevents the control of the interface means from broadcasting more packets than necessary into the system. As a result, it becomes possible to support a larger number of processors even if the information transmission line having the same bandwidth is used, and the processing capability of the information processing system is improved. In addition, since the line length of the information transmission line in the subunit can be shortened by segmenting and the capacitance floating in the information transmission line can be reduced, the data transmission bandwidth of the information transmission line can be expanded. be able to.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a configuration of an embodiment of an information processing system of the present invention.

FIG. 2 is a conceptual diagram of tag bits used in the information processing system of the present invention.

FIG. 3 is an explanatory diagram showing a format of a packet transmitted through an information transmission line in the embodiment of the present invention.

FIG. 4 is a configuration diagram of a header of a packet transmitted through an information transmission line in an embodiment of the present invention.

FIG. 5 is a configuration diagram of a tag unit according to an embodiment of the present invention.

FIG. 6 is a configuration diagram of an information processing system showing another embodiment of the present invention in which a tag bit is provided in a memory unit.

FIG. 7 is a configuration diagram of a packet header in still another embodiment.

FIG. 8 is a schematic diagram showing an information processing system in which a plurality of conventional processors are connected via an information transmission path.

[Explanation of symbols]

1,1a subunit, 2,2a processor group,
3,3a cache memory group, 4,4a memory
Unit, 5,5a Sub-unit internal information transmission line,
6, 6a bus interface unit, 7 sub-unit external information transmission line, 8, 8a tag unit, 20, 20a processor, 21 address block section, 22 tag bit, 30, 30a cache memory, 51 address Register, 52 packet type register, 53 address space register, 54 tag memory, 55 packet type decoder, 56 tag signal line output buffer, 57 memory start signal output buffer, 58 selector, 59 address decoder , 71 Broadcast flag
Field, L1 tag signal line, L2 memory activation signal line

Claims (1)

[Claims] 1. A plurality of sub-units each configured by connecting a cache memory attached to a processor and a main memory by a first information transmission line for transferring data in packets, the main memory, and For each address block divided in the cache memory, means for storing a tag bit indicating whether or not the data in the address block is the latest data, and data transfer by a packet to the plurality of subunits. Interface means for connecting to a second information transmission path to be performed, which determines the state of the tag bit when a packet is generated inside the sub unit, and determines the cache memory inside the sub unit and the main unit. Supports the packet only if the memory does not have the latest data for that address block. An information processing system characterized in that an interface means for sending the data to the outside of the bus unit is provided.