JPH0494237A - Priority control system in atm exchange channel - Google Patents

Abstract

PURPOSE:To save the hardware and to simplify read control by providing priority in response to a cell abort characteristic to each input cell in advance and using a cell abort means to abort a cell whose priority is low when the cell storage quantity exceeds a predetermined cell storage quantity. CONSTITUTION:Each of plural talking blocks includes a buffer section avoiding collision of cells whose number is equal to number of input highways 3 for each relevant output highway section 4 and each cell is provided with priority P in response to an abort characteristic of each cell. Each buffer section is provided with a buffer memory 5, a cell storage quantity measuring means 6 measuring a cell storage quantity and a cell abort means 8, 9 or 10. When the cell storage quantity exceeds a predetermined cell storage quantity by the cell storage quantity measuring means 6, the cell abort means 8, 9 or 10 aborts a cell with low priority. Thus, number of buffer memories is reduced and cell read control from the buffer is simplified.

Description

[Detailed Description of the Invention] [Summary] Regarding the priority control method in ATM switched communication paths, the purpose of this invention is to reduce the number of buffer memories and to simplify the control of reading cells from the buffers. and a plurality of output highways, and in which cells entering from the input highway are output to a desired output highway along a required bus, a priority is assigned to each input according to the discard characteristics of the cell. Buffer memories are added to the cells and provided for each output highway in the same number as the input highways, for avoiding cell collisions, cell storage amount measuring means for measuring the cell storage amount in the buffer memory, and cell discarding means. and is configured such that when the amount of stored cells exceeds a predetermined amount of stored cells, the cell discarding means discards cells with low priority.

[Industrial application field]

The present invention is an ATM (Asynchronous
(Transfer Mode) relates to a priority control method in a switched communication path.

In the ATM switching system, when a call is accepted, the expected bandwidth to be used on the network is declared, and based on this, the bandwidth of the call path is managed and traffic control such as routing is performed, but bursts of input traffic If traffic larger than the declared bandwidth is input due to network interference or communication abnormalities, and the network becomes overloaded, cells will be discarded.

To prevent this, cells are divided in advance into priority classes according to their discard characteristics and transferred, and when the network becomes overloaded, cells with lower priority classes are restricted, reducing the load on the network and transferring cells to priority classes according to their discard characteristics. Control is required to satisfy the discard characteristics by preferentially passing through high-value cells.

[Prior Art] FIG. 8 is a block diagram showing the configuration of a conventional priority control device. In the conventional priority control system, the buffer memory of the communication path is divided into each priority class, such as the buffer memory 81 for high priority cells and the buffer memory 85 for low priority cells. Detects an input cell, determines the priority class of the input cell by a priority detection unit 83, and controls each buffer memory 81 according to the priority by a buffer control unit 84 or 86.
Or accumulated to 85. To read data from the buffer memory, the buffer control unit 84 or 86 is controlled under the control of the read order control unit 88, and data is read out to the output highway via the selector 87 in the order of priority class.

[Problem to be solved by the invention]

In the conventional method described above, since the ratio of cell priority classes is unknown, it is necessary to prepare as many communication path buffers as there are priority classes, resulting in an enormous amount of hardware and complicated readout control. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the amount of hardware and simplify read control in a priority control system in an ATM exchange channel.

(Means for solving problems) FIG. 1 is a block diagram showing the principle of the present invention.

In the figure, (a) is a block diagram showing the configuration of a communication path, and (b) is a block diagram showing the configuration of a buffer section in the communication path. As shown in (a), the ATM according to the present invention
The switched communication path has a plurality of input highways 3 and a plurality of output highways 4, and a plurality of communication blocks 1-1 to 1 for outputting cells entering from the input highway 3 to a desired output highway along a required path. -n, and each call block is provided with buffer units 2-1 to 2-1 for each corresponding output highway (#d to #n) 4 corresponding to the number of input highways for avoiding cell collision. ,,,,2-m
Contains.

As shown in (b), each cell is assigned a priority P depending on the discard characteristics of the cell. Each buffer section includes a buffer memory 5, a cell storage amount measuring means 6 for measuring the amount of cells stored in the buffer memory 5, and cell discarding means 8, 9 .
or 10. In the cell storage amount measuring means 6, when the cell storage amount exceeds a predetermined cell storage amount, the cell discarding means 8.9. or 10, cells with lower priority are discarded.

The buffer units 2-1 to 2-n are connected by a read multiplex control line 12 that circulates tokens that give read rights, and when the token arrival interval exceeds a predetermined token arrival interval, a cell discard unit is connected. 8.9. Alternatively, a read multiplex control means 7 may be provided which controls cells having a lower priority to be discarded.

Preferably, the cell discarding means 8 is configured to discard cells of low priority on the input highway 3 before being written to the buffer memory 5.

Preferably, the cell discarding means 9 discards cells of low priority already stored in the buffer memory 5.

Preferably, the cell discarding means 10 discards the next cell to be read from the buffer memory 5 when that cell has a low priority.

[For production]

By providing the cell storage amount measuring means 6 and the cell discarding means 8, 9 or 10, the number of buffer memories in each buffer section can be reduced to one. Furthermore, since the number of buffer memories is one, there is no need to control the reading order as in the conventional case, and the control is simplified.

(Example) Identical parts are given the same reference numerals throughout the figures.

FIG. 2 is a block diagram showing the configuration of the first embodiment of the present invention, and shows one specific example of the buffer section in the communication path shown in FIG. 1(a).

In FIG. 2, 21 is a write counter, 22 is a read counter, 23 is a valid cell arrival detection unit, and 24 is a priority detection unit that outputs a high level when the priority contained in an input cell is low priority. , 25 is a NAND gate receiving the outputs of the priority detection section 24, the cell storage amount measuring device 6, and the readout multiplexing control section 7;
Reference numeral 26 denotes a gate that allows or prevents the valid cells output from the valid cell arrival detection section 23 from passing through depending on the output of the NAND gate 25.

In this first embodiment, the cell storage amount of the buffer memory 5 measured by the cell storage amount measuring device 6 exceeds a predetermined storage amount (threshold value), and the readout multiplexing control line 12 The arrival interval of the token for acquiring the read right inputted to the control unit 7 is longer than a predetermined time, and the priority detection unit 24 detects that
On condition that the priority of the valid cell input at the input side of the buffer memory (priority according to the discard characteristics of the cell) is low priority, the NAND gate 25 outputs a low level, and the gate 26 outputs a low level. When enabled, the output of the arrival detection unit 23 is prohibited from passing through. thus,
By not sending a write pulse to the write counter 21 for a cell with a low priority, control is performed so that the cell is not written to the buffer memory 5 and the cell is discarded.

FIG. 3 shows the configuration of the cell storage amount measuring device 6 shown in FIG. In FIG. 3, 31 is a device that outputs the maximum value of the counter, 32 is a comparator, 33 is a subtracter that subtracts the value of the read counter 22 from the maximum value of the counter, and 34 is a device that outputs the output of the subtracter 33 and the output of the write counter 21. 35 is a subtractor that subtracts the value B of the read counter 22 from the value A of the write counter 21; 36 is an output of either the output of the subtracter 35 or the output of the adder 34 according to the output of the comparator 32; A selector 37 is a comparator that compares the output of the selector 36 with a predetermined threshold.

Normally, when the buffer memory 5 is operated as a FIFO, there is a magnitude relationship between the value A of the write counter 21 and the value B of the read counter 22, so it is necessary to measure the cell storage amount for each. In this configuration, if A>B, the subtracter 35 adds the complements of A and B, and if A<B, the subtracter 33 first adds the maximum value of the counter and the complement of B,
The adder 34 adds the result and A. The comparator 36 selects these two calculation results according to the magnitude relationship between A and B output from the comparator 32 to determine the cell storage amount, and the comparator 37 selects a predetermined cell amount (i.e., If the number is higher than the threshold value, a signal is sent to the cell discarding means.

FIG. 4 is a block diagram showing the configuration of the read multiplex control section 7 shown in FIG. 2. In FIG. 4, numeral 41 latches the cell presence information sent from the cell storage amount measuring device 6 in response to a token from the readout multiplex control line 12, and the information is sent via the readout multiplex control line 12. A register whose contents are reset in response to the rising edge of a read frame indicating the length of a cell, 42 a counter that measures the time interval of tokens, 43 a comparator that compares the count value of the counter 43 with a predetermined threshold, 44 a register This selector outputs the token on the read multiplex control line 12 only when information indicating the presence of a cell is output from 41, and outputs only the read frame when there is no cell.

FIG. 5 is a time chart illustrating the operation of the read multiplex section shown in FIG. 4. The operation of the read multiplex section will be explained with reference to FIGS. 4 and 5.

When a token for acquiring the read right is input from the read multiplex control line 12, the cell storage amount measuring device 6 (
The presence/absence information of cells in the buffer memory 5 inputted from FIG. 2) is latched into the register 41.

If there is a cell in the buffer memory 5, the read counter 22
By sending that signal to increment the counter 22, cells are read out from the buffer memory on the highway. At the same time as this reading, the token is sent to the next stage buffer section via the read multiplex control line 12.

If there are no cells in the buffer memory 5, the input token is immediately sent to the next stage buffer memory via the read multiplex control line 12.

In other words, if cells are stored evenly in the buffer memory that performs collision avoidance, which is provided for each output highway by the number of input highways, the interval between tokens will be long, and if cells are stored unevenly, the interval between tokens will be short. Become. As a result, the utilization rate of the output highway can be determined in each buffer section, control can be distributed, and cells can be prevented from being erroneously discarded even though the output highway can be used.

Detection of this usage rate is done by counting input tokens at counter 42.
The comparator 43 compares the counter value up to the next token with a predetermined threshold, and if the counter value is above the threshold, sends a high level signal to the NAND gate 25. There is.

FIG. 6 is a block diagram showing the configuration of a second embodiment of the present invention. In the figure, 61 is a priority detection unit;
62 is a valid cell arrival detection unit, 63 is a selector, 64 is an empty address storage memory 64, 65 is a high priority cell address storage memory, 66 is a low priority cell address storage memory, and 67 is a selector.

In this second embodiment, when the cell storage amount of the buffer memory 5 is measured and exceeds a predetermined storage amount (threshold value), a token for acquiring the read right inputted from the read multiplex control line is When the arrival interval is longer than a predetermined time, control is performed to discard only cells with low priority among the cells already written in the buffer memory from the buffer memory.

That is, an empty address of the buffer memory 5 is written in the empty address storage memory 64 in advance, and when the arrival of a valid cell is detected by the valid cell arrival detection unit 62, the empty address is read from the empty address storage memory 64 and a cell is stored at that address. At the same time, the written address is stored in each address storage memory (F
IFO) Write to 65 or 66. Each time a token is input from the buffer memory 5, the cell is output by sequentially reading out the addresses stored in the address storage memory 65 or 66 prepared for each priority cell.

Further, the read address is written to the free address storage memory 64 again. Here, if the cell storage amount exceeds the threshold value in the cell storage amount measurement device 6 and the token interval is longer than the threshold value in the readout multiplex control device 7, the low priority cell address storage memory 66 is reset. By writing the stored address into the free address storage memory 64, only the low priority cells in the buffer memory 5 are discarded.

FIG. 7 is a block diagram showing the configuration of a third embodiment of the present invention.

This third embodiment measures the amount of accumulated cells in the buffer memory 5, exceeds a predetermined accumulated amount (threshold value), and receives a token for acquiring the read right inputted from the read multiplex control line. If the interval is longer than a predetermined time, control is performed to discard only cells with low priority among the cells to be read next from the buffer memory.

The configuration of the third embodiment is almost the same as that of the second embodiment, except that when the accumulated cell amount exceeds the threshold and the token interval is longer than the threshold, low priority cells are Instead of resetting the address storage memory 66, a read signal is applied via the OR gate 71, and the address of the cell to be read next in the low priority cell address storage memory 66 is read blankly (the cell is not read). By writing the stored address into the free address storage memory 64, the high-priority cells are preferentially sent to the output highway.

〔Effect of the invention〕

As is clear from the above description, by providing the cell storage amount measuring means and the read multiplexing control means for measuring the token interval according to the present invention, each buffer section is provided with a single buffer memory regardless of the priority. Since there is no need to provide multiple buffer memories depending on the priority, it is possible to significantly reduce the amount of hardware.

Furthermore, since the number of buffer memories is one, there is no need to control the reading order as in the conventional case, and the control is simplified.

Furthermore, network overload can be suppressed by discarding cells with low priority in terms of discard rate, thereby satisfying the discard rate characteristics of cells with high priority in terms of discard.

Furthermore, since the amount of accumulated cells in the buffer memory of the communication path is measured and discard control is performed using the token interval of read multiplex control, it is possible to cope with temporary burst track fluctuations and to reduce the usage rate of the output highway. Since each buffer can make a decision, it is possible to decentralize control and prevent cells from being erroneously discarded even though an output highway can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing a first embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of the cell storage amount measuring device shown in FIG. 2. 4 is a block diagram showing the configuration of the read multiplex control section shown in FIG. 2, FIG. 5 is a time chart explaining the operation of the read multiplex control section shown in FIG. 4, and FIG. 6 is a block diagram showing the structure of the read multiplex control section shown in FIG. FIG. 7 is a block diagram showing a third embodiment of the present invention. FIG. 8 is a block diagram showing a conventional configuration example. In the figure, 1-1 to 1-n are communication blocks, 2-1 to 2-m are buffer sections, 3 is an input highway, 4 is an output highway, 5 is a buffer memory, 6 is a cell storage amount measuring means, and 7 is a 8.9 and 1o are cell discard means; 11 is a buffer control section; and 12 is a read multiplex control line.

Claims (1)

[Claims] 1. It has a plurality of input highways (3) and a plurality of output highways (4), and outputs cells entering from the input highway (3) along a required path to a desired output highway. In the communication path of the ATM switching system, a priority (P) is added to each input cell according to the discard characteristics of the cell, and cell collision avoidance is provided for each output highway as many as the number of input highways. Buffer memory (2-1, .
．． ．． , 2-m), comprising cell storage amount measuring means (6) for measuring the cell storage amount in the buffer memory, and cell discarding means (8, 9, or 10), wherein the cell storage amount is determined in advance. 1. A priority control system characterized in that, when a cell storage amount exceeds a predetermined cell storage amount, cells with a low priority are discarded by the cell discarding means. 2. The buffer memories are connected by a read multiplex control line (12) that circulates tokens that give read rights, and when the token arrival interval exceeds a predetermined token arrival interval, the cell discarding means 2. The priority control system according to claim 1, wherein cells with lower priority are discarded. 3. Input highway before writing to the buffer memory (
3. The priority control system according to claim 1 or 2, wherein in the above, the cell discarding means (8) discards cells with low priority. 4. The priority control system according to claim 1 or 2, wherein the cell discarding means (9) discards cells of low priority already stored in the buffer memory. 5. The priority control system according to claim 1 or 2, wherein the cell discarding means (10) discards the cell when the next cell to be read from the buffer memory has a low priority.