JPH0488752A - Picture processor - Google Patents

Abstract

PURPOSE:To store an excellent picture with less memory capacity by providing a resolution memory, a gradation memory, and plural image memories compressing an image data and storing the result to the processor and synthesizing the image data with a text data in response to the resolution information stored in the resolution memory. CONSTITUTION:A host computer is connected to an input terminal 1, the host computer inputs a data stored to a resolution memory 3, gradation memories 4,5 and an image memory 6, a data identification circuit 2 decodes header information added to the data and the data is stored in the memories 3, 4, 5, 6. When the host computer transfers one page of data and a printer engine is started, the memories 3, 4, 5, 6 output the data from a head picture element of a page sequentially and synchronously with the printer engine to supply the data to a control terminal and an input terminal (a) of a selector 9 and each input terminal of a selector 8. On the other hand, an image area signal representing valid/invalid output data of each image memory is inputted from the image memory 6 to a priority encoder 7. The encoder 7 controls the selector 8 so that the valid image data of the area set finally is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device having a storage means for storing images, particularly line drawings such as characters and graphics (hereinafter referred to as "text"), and gradation processing. The present invention relates to an image processing device that stores image information in which halftone images such as photographs (hereinafter referred to as "images") are mixed.

[Conventional technology]

Generally, when storing text, high resolution is required to ensure smoothness and continuity of diagonal lines, etc., while when storing images, high gradation is required to avoid deterioration of image quality due to false contours. sexuality is required. Therefore, conventionally, when storing an image in which an image area and a text area coexist, the number of pixels that can achieve sufficient resolution to ensure the quality of the text, that is, the smoothness and continuity of diagonal lines, etc., and the image The storage device is configured to have a number of gradation levels that can avoid image quality deterioration due to false contours.

[Problem that the invention is trying to solve]

However, according to the above conventional storage device, in order to achieve high image quality for both text and images, both the number of pixels and the number of gradations increase, resulting in the need for a huge memory capacity. However, the disadvantage is that the scale of the device (hardware) and cost become enormous. In particular, when trying to store a full-color image, three planes of the three primary colors, red (R), green (G), and blue (B), are required, so the memory capacity is tripled. For example, set the number of gradations of each RGB plane of image data to 2.
56, the number of bits per pixel required for full-color display is 24, and 24 times the memory capacity is required compared to the case of only monochrome characters (the number of bits per pixel is 1).

The present invention has been made in view of the above-mentioned points, and is an apparatus for storing images in which text and images are mixed, without increasing the memory capacity (in particular, it is possible to store both images and text having color information). An object of the present invention is to provide an image processing device that can maintain good image quality.

[Means and effects for solving the problems] To solve the above problems, the image processing device of the present invention includes a resolution memory for storing resolution information and a memory for storing drawing colors of text data. It has a gradation memory and a plurality of image memories for compressing and storing image data, and for overlapping parts of the image data stored in the image memories, the image data stored last is used to store the image data in the resolution memory. The text data is combined with the text data according to the resolution information stored in the text data.

〔Example〕

First Embodiment> FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to a first embodiment of the present invention. In the figure, 1 is an input terminal, 2 is a data identification circuit, 3 is a resolution memory, 4.5 is a gradation memory, 6 is an image memory, 7 is a priority encoder, 8.9 is a selector, and 10 is an output terminal. .

A host computer is connected to input terminal 1,
Data to be stored in the resolution memory 3, gradation memory 4.5, and image memory 6 is input from the host computer, and the data identification circuit 2 interprets the header information added to the stored data. The corresponding data is stored in 3.4.5.6. From the above host computer 1
When data for one page is transferred and the printer engine is started, each memory 3, 4, 5, and 6 synchronizes with the printer engine in order from the first pixel of the page according to the synchronization signal (H8YNK). and supplies data to the control terminal and input terminal a of the selector 9 and each input terminal of the selector 7, respectively.

On the other hand, an image area signal indicating validity/invalidity of the output data of each image memory is input from the image memory 6 to the priority encoder 7. The priority encoder 7 controls the selector 7 so that the valid image data of the last set area is selected based on the input image area signal.

Note that when all the image data is invalid, the background color data in the gradation memory 5 is selected. Therefore, if valid image data exists, the image data of the last set area is supplied to the terminal of the selector 9, and if no valid image data exists, the background color data is supplied. The selector 6 follows the output of the resolution memory 3 and selects the resolution data as “1”.
When , the data of terminal a (that is, the data of gradation memory 4) is selected as the drawing color, and when the resolution data is "0", the data of terminal A is selected as the background color, and the data is connected to output terminal 7. The gradation data is supplied to the printer engine that is running.

FIG. 2 is a block diagram showing a specific example of the configuration of the image memory 6. As shown in FIG.

In the figure, 11 is a compression rate setting circuit, 12 is a compression circuit, 13 is a memory, 14 is an expansion circuit, and 15 is an area detection circuit.

When the starting coordinates of the image area and the width and height of the area are input to the compression rate setting circuit 11 from the signal line 100, the compression rate setting circuit 11 determines the size of the input image data based on the size of the area, that is, the width and height. The amount of data is calculated and the compression ratio is set based on the ratio to the capacity of the memory 9.

Note that when the compression ratio is less than or equal to a predetermined value of 1/k, the image area is divided so that the compression ratio is equal to or more than L/k. On the other hand, the coordinate values of two points, the start coordinate and the end point coordinate of the area calculated from the width and height of the area, are set in each register of the area detection circuit 15. The compression circuit 12 controls quantization conditions and the like so that the compression rate set by the compression rate setting circuit 11 is achieved, and stores the compressed image data in the memory 13. The compression circuit 12 is a known compression encoding circuit that performs orthogonal exchange, vector quantization, and the like.

FIG. 3 is a block diagram showing a specific example of the configuration of the compression circuit 12. This example uses JPEG (Joint Photography), a joint effort between ISO and CCITT.
Basel, an alternative international standard for color still image encoding proposed by the icExpert Group
ineSystem encoding unit (References Niyasuda, "International Standardization of Color Still Image Coding", Journal of the Institute of Image Electronics Engineers, Vol. 18, No. 6, PP, 398-407.1
987) The image pixel data inputted from the signal line 103 is cut out into 8×8 pixel blocks in the blocking circuit 16 which is constituted by delay line memory for several lines, and then processed into a discrete cosine transform (DCT) circuit 17. Cosine transform is performed at , and the transform coefficients are supplied to a quantizer (Q) 18 . The quantizer 18 linearly quantizes the transform coefficients according to the quantization step information applied by the quantization table 19. Among the quantized transform coefficients, the DC coefficient is subjected to a difference (prediction error) from the DC component of the previous block in a predictive coding circuit (DPCM) 20 and is supplied to a Huffman coding circuit 23 . FIG. 4 shows the predictive encoding circuit 2o.
FIG. 2 is a detailed block configuration diagram of FIG. The DC coefficients quantized by the quantizer 18 are applied to the delay circuit 3o and the subtracter 31. The delay circuit 30 is a circuit that delays the discrete cosine transform circuit by the amount of time required to calculate one block, that is, 8×8 pixels. Therefore, the DC coefficient of the previous block is supplied from the delay circuit 30 to the subtracter 31. Ru.

Therefore, the subtracter 31 outputs the difference in DC coefficients (prediction error) from the previous block.

(Since this predictive encoding uses the previous block value as the predicted value, the predictor is configured with a delay circuit as described above.) The Huffman encoding circuit 21 receives the prediction supplied from the predictive encoding circuit 20 The error signal is variable-length coded according to the DC Huffman code deple 24, and then sent to the multiplexing circuit 29.
Huffman ◆ Supply code.

On the other hand, the AC coefficient (D
The coefficients other than the C coefficients are zigzag-scanned by the scan conversion circuit 21 in the order of low-order coefficients as shown in FIG. 5(a), and are supplied to the significant coefficient detection circuit 22. The significant coefficient detection circuit 22 determines whether the quantized AC coefficient is "0" or not. If it is "0", a count up signal is supplied to the run length counter 25 to increase the value of the counter by +1. On the other hand, in the case of a coefficient other than "0", a reset signal is supplied to the run length counter, the value of the counter is reset, and the coefficient is assigned a group number by the grouping circuit 26 as shown in FIG. 5(b). 5sss and additional bits, and supply the group number 5sss to the Huffman encoding circuit 28 and the additional bits to the multiplexing circuit 29, respectively.

The run length counter 25 is a circuit that counts the run length of "0" and supplies the number NNNN of "0" between significant coefficients other than "0" to the Huffman encoding circuit 28. Huffman encoding circuit 2
8 performs variable length encoding on the supplied run length NNNN of "0" and significant coefficient group number 5sss according to the AC Huffman code table 27, and supplies the AC Huffman code to the multiplexing circuit 29.

The multiplexing circuit 29 multiplexes the DC Huffman medium code, AC Huffman fist code, and additional bits for one block (8×8 input pixels), and compressed image data is output from the signal line 104.

Therefore, the memory capacity can be reduced by storing the compressed data output from the signal line 104 in a memory and decompressing it by reverse operation when reading.

The decompression circuit 14 decompresses the compressed data by the reverse operation described above only when the signal supplied from the image area detection circuit 15 becomes valid (image area pixel), and outputs the image data from the signal line lot.

Note that the value of the quantization table 19 is controlled according to the compression rate supplied from the compression rate setting circuit 11.

FIG. 6 is a block diagram showing a specific example of the configuration of the gradation memory 4(5). In the figure, 32 and 34 are selectors, 33 is a register group, and 35 is an area determination circuit.

The gradation data input from the signal line 108 is sent to the selector 32.
are sequentially stored from the register 33-2.

Note that default gradation data (
For example, black is set in gradation memory 4, and white is set in gradation memory 5. The area determination circuit 35 has signal lines 105, 1
Based on the coordinate values of the output data of the resolution memory 3 inputted from 06, the range in which the gradation data stored in each register is valid is determined, the selector 34 is controlled, and the signal line 10
Effective gradation data is output from 9.

FIG. 7 is a block diagram showing a specific example of the configuration of the area determination circuit 35. In the figure, 36 is an area detection circuit, 34 is a priority encoder, 38, 39, 40° 41 is a register, 42, 43 is a comparison circuit, and 44 is an AND circuit.

In this embodiment, the effective area of each gradation register 33-2 to 33-n is limited to a rectangle as shown in FIG. 8, and the first scanned point (Xo, yo) (in FIG. the upper left corner (hereinafter referred to as the "starting point") and the last scanned point (
x+, y+) (lower right corner of the rectangle in the figure, hereinafter "end point")
It is set at two points. Note that in the figure, the X-axis direction is the main scanning direction of the printer, and the y-axis direction is the sub-scanning direction.

The coordinate values (x) of the starting point and ending point identified by the data identification circuit 2.

yo)+(Xl+31'l) is each register 3 of the area detection circuit 35 corresponding to the gradation register 33 in FIG.
Stored at 8°39.40.41.

On the other hand, when printing out, the signal line 105. 106
Thus, each coordinate value of the pixel data read out from the resolution memory 3 is input. A first comparison circuit 42 compares the X coordinate value X of the resolution memory 3 with the X coordinate value XO of the starting point and ending point.
+ Compare with Xl, and when x□≦X≦X1, set it to “1”, Alternatively, when x>x1, "0" is input to the AND circuit 41. Similarly, the second comparison circuit 43
When ≦y≦y1, y<y.

Alternatively, when y>yl, "0" is input to the AND circuit 44. Therefore, from the AND circuit 44, (i) X o≦X
≦X, and y. When ≦y≦y1, “bi, (it) (i)
In other cases, "0" is output, and area detection becomes possible.

The results detected by each of the area detection circuits 36-2 to 36-n are processed by the priority encoder 37 to determine the priority of overlapping areas as shown in the shaded area in FIG. , the number of the last set area is encoded and output from the signal line 107. That is, in the overlapping part, the area set later is determined to be valid. In addition,
If the results of each area determination are all "0", the priority encoder outputs "0" and the selector is activated to select the gradation data (i.e. default value) of the gradation register 33-1 in FIG. 34.

Note that the image area detection circuit 15 in FIG. 2 is constructed of a circuit similar to the area detection circuit 36 in FIG. 7.

FIG. 1(b) is a diagram showing the overall configuration of an image processing apparatus including the image storage section of FIG. 1(a).

In FIG. 1(b), 200 is an image input unit connected to the host computer, but it may also be an image reading device such as an image scanner including a CCD sensor, an interface for external equipment such as the Sv left camera video camera, etc. It's okay. In the latter case, the data identification circuit 50 identifies the data. The image data input from 200 is stored in the image storage unit 2 shown in FIG. 1(a).
01 input terminal 1. Reference numeral 202 designates an operation unit through which an operator specifies output light for image data, and reference numeral 203 designates an output control unit, which performs selection of output light for image data, output of a synchronization signal for memory reading such as HSYNO of the printer engine, and the like. The synchronization signal is supplied to the identification circuit 50 of FIG. 1(a) and each memory, and is used as a control signal for data transfer, reading from the memory, etc. 204 is an image display unit such as a display; 205 is a transmitting unit that communicates image data via a public line or local area network; and 206 is a latent image formed by irradiating a laser beam on a photoreceptor, and this is This is an image output unit such as a laser beam printer that creates a visible image. Note that the image output unit 206 may be an inkjet printer, a thermal transfer printer, a dot printer, or the like.

As described above, this embodiment of the present invention has an image memory that compresses and stores continuous tone data such as image data using the correlation between pixels and visual characteristics, and a text color (drawing color) for each specific area. Alternatively, a gradation memory that stores the background color and a resolution memory that stores the dot resolution of pixel data are provided.
By switching the output data of the image memory and gradation memory in accordance with the output signal of the resolution memory, it is possible to reduce the memory capacity while maintaining good image quality of both text and images.

Furthermore, by providing a plurality of image memories and making it possible to combine image data, the efficiency of transferring image data from the host computer is improved and the data transfer time is reduced.

<Second Embodiment> FIG. 9 is a block diagram showing the configuration of an image processing apparatus according to a second embodiment of the present invention. In the drawings, components that perform the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and only the differences from the first embodiment will be described below.

In the figure, 45 and 46 are selectors.

The image data transferred from the host computer is
Since the data is sent for each image area, the compression circuit 12 can be shared by each image memory.

On the other hand, in this embodiment, since overlapping of image areas is also allowed, the decompression circuit 14 cannot be shared (however, it can be shared if there is no overlapping).

The header information of the image data identified by the data identification circuit 2 is interpreted by the compression rate setting circuit, and the compression rate and the coordinates of the start and end points of the image area are calculated and supplied to the compression circuit 12 and the selector 46, respectively. . The compression circuit 12 compresses the image data according to a set compression rate, and sequentially stores the compressed data for each image area from the memory 13-1 via the selector 45. Similarly, the coordinates of the start point and end point of each image area are stored in each register in order from the area detection circuit 15-1 via the selector 46. From then on, the first
Since this embodiment is the same as that in the embodiment, the explanation will be omitted.

By sharing the compression circuit 12 and compression rate setting circuit 11 in each image memory, the amount of hardware can be reduced.

<Third Embodiment> FIG. 10 is a block diagram showing the configuration of an image processing apparatus according to a third embodiment of the present invention. In the figure, components that perform the same functions as in FIGS. 1 and 2 are given the same reference numerals.
Hereinafter, only the points different from the first embodiment will be explained.

In the figure, 47, 48, 49, 50, 51, and 52 are selectors, and 53 is a compression ratio setting circuit.

In this embodiment, each time image data is transferred from the host computer, the compressed data stored in the memory is decompressed, combined with the input image data, compressed, and stored in another memory. ing. With this configuration, the compression circuit 12, the expansion circuit 13, and the compression rate setting circuit 53 are all required in one system, and the memory 13 and the image area detection circuit 13 are required in only two systems, which greatly reduces the amount of hardware.

A method of combining image data will be described below.

In the initial state, selector 47 connects terminal a, selector 48 to
52 selects the terminal d. Therefore, the first image area data is compressed and stored in the memory 13-1, and the coordinates of the start and end points of the image area are stored in the area detection circuit 15-1. When the storage of the first image area data is completed, the selectors 48 to 52 are each controlled to select the terminal e.

Next, the second image area data is transferred to the data identification circuit 2.
When supplied from the selector 5, the compression ratio setting circuit 53
The starting point coordinates (x
e, ys), end point coordinates (xe, ye), and start point coordinates (xo, yo) of the second image area calculated from the header information supplied from the data identification circuit 2, end point coordinates (
xl, y+), start point coordinates (x s
, ys) and the end point coordinates (Xe, yJ) are determined by the following calculations and stored in the area detection circuit 15-2.

Next, a target compression ratio is determined from the determined coordinates of the starting point and end point of the synthesis area, and set in the compression circuit 12, and the selector 47 performs synthesis from the pixel at the starting point coordinate to the pixel at the ending point coordinate. The second image area detection signal selected by the selector 52 is supplied to the control terminal of the selector 47;
When the composite pixel is in the second image area, terminal a (ie, the second image data) is selected, and in other cases, terminal b (ie, the output image data of the expansion circuit 14) is selected to perform the synthesis. The combined image data is compressed by the compression circuit 12 and stored in the memory 13-2 via the selector 48. Note that the expansion circuit 14 outputs expanded image data when the area detection signal supplied from the selector 51 indicates validity, and outputs blank (white) data when it indicates invalidity. By the above operation, when the synthesis is performed up to the end point coordinates of the synthesis area and the compressed data is stored in the memory 13-2, the selectors 48 to 52 are inverted and select the terminal d, and then wait for the synthesis of the image area. state.

By repeating the above operations, image data for one page is stored in the memory 13, and when the printer engine is started, the last stored compressed image data is supplied to the decompression circuit 14 and synchronized with the printer engine. The image data obtained is supplied to a terminal of the selector 53. Since the subsequent steps are similar to those in the first embodiment, the explanation will be omitted.

In the first to third embodiments, the gradation information (drawing color) of the text data is stored in the gradation memory 4, but it may be stored in the image memory.

In this case, the background color is stored in the gradation memory 4, and the gradation memory 5 becomes unnecessary.

〔Effect of the invention〕

As explained above, according to the image storage device of the present invention, images containing text images can be stored with a small memory capacity.
I was able to memorize both text and images well.

Furthermore, since it has become possible to combine image data, the time for transferring image data is shortened, and a variety of output images can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to the first embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the configuration of an image memory, and FIG.
The figure shows a specific configuration example of a compression circuit, FIG. 4 shows a specific configuration example of a predictive coding circuit (DPCM), FIG. 5 shows a DCT scan order, and FIG. FIG. 7 is a diagram showing a specific configuration example of the tone memory, FIG. 7 is a diagram showing a specific configuration example of the area determination circuit, FIG. 8 is a diagram showing the effective area of the tone memory on the page, and FIG. 9 is the present invention. FIG. 1O is a block diagram showing the structure of a third embodiment of the present invention. 2...Data identification circuit 3...Resolution memory 4.5...Gradation memory 6...Image memory 7...Priority encoder 8.9.45.46.47.48.49.50 .51.
12...Selector 11.53...Compression rate setting circuit 12...Compression circuit 13...Memory 14...Expansion circuit 15...Image area detection circuit. 1st stage ((1) Figure 4 Figure 5 ■ (σ) Figure 5 (shi) Several ACCs sss Figure 6 L-1

Claims (4)

[Claims] (1) A resolution memory for storing resolution information, a gradation memory for storing drawing colors of text data, and a plurality of image memories for compressing and storing image data; An image processing device characterized in that overlapping portions of image data stored in a memory are combined with the text data using the last stored image data according to resolution information stored in a resolution memory. . (2) The image processing apparatus according to claim 1, wherein the image data compression means is shared by the plurality of image memories. (3) When the compression ratio becomes less than a predetermined value 1/k, the image area is divided and stored in a plurality of memories so that the compression ratio becomes 1/k or more. The image processing device described. (4) It has at least two memories for storing compressed images, at least two image area detection circuits, one compression circuit and one decompression circuit, and the data stored in one memory is Claim 1, characterized in that the image data is restored in the decompression circuit, the restored image data and the image data input from the host computer are combined, and then compressed in the compression circuit and stored in the other memory. image processing device.