JPH0482388A - Image pickup device and video signal reproducing device for video signal recorded by the image pickup device - Google Patents

Abstract

PURPOSE:To correct a blur in the subscanning direction of a video signal based on a blur signal representing quantity of hand blur at reproduction by inserting the blur signal into the video signal and recording the resulting signal onto a recording medium. CONSTITUTION:An encoder circuit 5a uses a horizontal hand blur data mix circuit so as to insert a horizontal hand blur data given from a hand blur detection section to a video signal as a digital signal for a vertical blanking period of the video signal. The video signal with the horizontal blur data inserted thereto is recorded on a VTR tape via a VTR video recording circuit 6. AVTR reproduction circuit 8 reproduces the video signal recorded on the VTR tape 7 and gives the signal to a TBC and a horizontal hand blur compensation circuit 42 as Y and C signals. Thus, the hand blur is compensated and a stable video image is sent to the output of a Y signal processing section.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an imaging device and a video signal reproducing device for reproducing a video signal imaged by the imaging device, and in particular, to a video signal reproducing device for reproducing a video signal captured by the imaging device. Camera-integrated VTR
The present invention relates to an improvement of a video table recorder (video table recorder) and a playback device such as a stationary VTR for playing back in good condition a video signal shot by such an imaging device.

[Prior Art] FIG. 6 is a block diagram of a conventional VTR camera with a camera shake compensation function and a VTR deck for reproducing video signals recorded on a VTR tape.

Referring to FIG. 6, a conventional VTR camera 68a with a camera shake compensation function includes a lens 1 for condensing light rays incident from a subject and forming an image on a predetermined surface. A CCD 2 converts an optical image into a video signal, and various correction processes are performed on the video signal output from the CCD 2.
Further, a signal processing circuit 3 for separating the colors and outputting a luminance signal and a color difference signal, and a signal processing circuit 3 provided in the VTR camera 68a,
A camera shake detector 70 for detecting horizontal and vertical camera shake of the TR camera 68a and outputting vertical shake data and horizontal shake data; connected to the camera shake detector 70 and the signal processing circuit 3; A horizontal camera shake compensation circuit 4 that performs processing to compensate for horizontal camera shake on the Y (luminance) signal and C (chroma) signal provided from the signal processing circuit 3; Processing circuit 3
Y, which is connected to Y and given from the horizontal camera shake compensation circuit 4.
An encoder 5 for encoding the signal and the C signal given from the signal processing circuit 3, and a composite video signal connected to the encoder 5 and output from the encoder 5,
a VTR recording circuit 6 for recording on a TR tape 7;
Synchronization signal generation circuit (SSG) 1 that outputs a synchronization signal for regulating the timing of the entire operation of the TR camera 68g
2, it receives and receives vertical shake data from the camera shake detector 70, receives a synchronization signal from the 5SG12, and operates the CCD 2 according to the vertical shake data to eliminate the influence of camera shake on the vertical video signal. To compensate, CC
A timing generator 11 that outputs a timing signal for driving D2;
an H-driver for receiving timing signals from and outputting horizontal transfer pulses and vertical transfer pulses necessary for horizontal scanning and vertical scanning by the CCD 2;
- driver circuit 10.

The camera shake detection unit 70 includes a vertical shake sensor 14 for detecting vertical shake of the VTR camera 68a, and a vertical shake sensor 14 for detecting vertical shake of the VTR camera 68a.
Horizontal shake sensor 15 for detecting horizontal shake of 8a, vertical shake sensor 14 and horizontal shake sensor 15
The camera shake detection circuit 13 includes a camera shake detection circuit 13 for processing signals indicating vertical and horizontal camera shake input from the camera shaker 11 and providing digital data to a timing generator 11 and a horizontal camera shake compensation circuit 4, respectively. Vertical blur sensor 1
4. As the horizontal shake sensor 15, an angular velocity sensor is used for boat fishing.

The VTR deck 69a includes a VTR playback circuit 8 for playing back the video signal recorded on the VTR tape 7, and a TBC (Time-Base) for correcting time-base errors in the video signal played by the VTR playback circuit 8. Corr
controller) circuit 67 and a buffer 9 for buffering the output of the TBC circuit 67. The video signal is provided to the monitor via a buffer 9.

Referring to FIG. 8, the camera shake detection circuit 13 calculates the amount of vertical shake from the signal indicating vertical shake given from the vertical shake sensor 14, digitizes it, and outputs the vertical camera shake detection circuit 84. and a horizontal camera shake detection circuit 85 that calculates horizontal shake from a signal indicating horizontal shake given from the horizontal shake sensor 15, digitizes the signal, and provides the digitalized signal to the horizontal camera shake compensation circuit 4.

The vertical camera shake detection circuit 84 includes an amplifier 16 for amplifying the signal output from the vertical shake sensor 14, and a circuit for calculating the amount of vertical shake based on this signal after removing noise from the output of the amplifier 16. LPF and arithmetic circuit 17, A/D conversion circuit 18 for digitizing the analog signal output from circuit 17, and A/D conversion circuit 1
8 and a parallel/serial (P/S) conversion circuit 19 for converting the parallel digital signals outputted by the circuit 8 into serial data.

The horizontal camera shake detection circuit 85 includes an amplifier 20 for amplifying a signal indicating horizontal shake output from the horizontal shake sensor 15, removes noise from the output of the amplifier 20, and detects the amount of horizontal shake based on this signal. L to find by calculation
A PF and arithmetic circuit 21, an A/D conversion circuit 22 for digitizing the analog signal output from the circuit 21,
It includes a P/S conversion circuit 23 for converting parallel data output from the A/D conversion circuit 22 into serial data.

Referring to FIG. 10, horizontal camera shake compensation circuit 4 receives and receives the Y signal from signal processing circuit 3, performs processing on the Y signal to compensate for camera shake in the horizontal direction, and sends it to encoder 5. The Y signal compensation circuit 90 for output and the signal processing circuit 3 receive the Y signal for color erasing during /X illumination and the line-sequential color difference signal, and apply compensation for horizontal camera shake to these signals. Color thread signal compensation circuit 91 for processing and providing it to the encoder 5 and the signal processing circuit 3, respectively.
, the horizontal synchronization signal HD from the 5SG 12 and the horizontal shake data from the camera shake detection circuit 13, and the Y signal compensation circuit 90 and the colored thread signal compensation circuit 9 based on the horizontal shake data.
1 and a memory controller 30 for performing compensation processing for these horizontal camera shakes by controlling the timing of the operations in FIG.

The Y signal compensation circuit 90 includes an amplifier 24 for amplifying the Y signal provided from the signal processing circuit 3, and an amplifier 24 according to a clock provided from the memory controller 30.
A/D to digitize the analog signal output by
The data output from the conversion circuit 25 and the A/D conversion circuit 25 are stored in synchronization with the write clock given from the memory controller 30, and the stored contents are sequentially output in synchronization with the read clock given from the memory controller 30. a D/A conversion circuit 27 for converting digital data outputted from the line memory 26 into an analog signal in synchronization with a read clock given from the memory controller 30; LPF 28 whose input is connected to the output of circuit 27;
The input is connected to the output of PF28, and the output is connected to the encoder 5.
and a buffer 29 connected to.

The colored thread signal compensation circuit 91 includes an amplifier 31 for receiving and taking the Y signal for color erasure from the signal processing circuit 3 and amplifying and outputting it, and receiving and receiving line-sequential color difference signals from the signal processing circuit 3. an amplifier 32 for amplifying and outputting the
A multiplexer 33 whose inputs are connected to the outputs of the amplifiers 31 and 32 and for multiplexing and outputting the Y signal for color erasure and the line-sequential color difference signal in synchronization with the clock given from the memory controller 30; An A/D conversion circuit 34 whose input is connected to the output, and which digitizes the analog signal output from the multiplexer 33 in synchronization with the write clock given from the memory controller 30; The input is connected, and in response to a write clock given from the memory controller 30, the output of the A/D conversion circuit 34 is stored sequentially, and the stored data is sequentially output in synchronization with a read clock given from the memory controller 30. The line memory 35 has an input connected to the output of the line memory 35, and by reading data from the line memory 35 in synchronization with the read clock given from the memory controller 30, color erasing Y is output from the output of the line memory 35. An input is connected to a color erasing Y signal processing circuit 92 for extracting a signal, converting it into an analog signal, and providing it to the encoder 5, and the output of the line memory 35, and the memory controller 3
The color difference signal is extracted from the output of the line memory 35 by reading the output of the line memory 35 in synchronization with a clock whose phase is opposite to the read clock given to the color erasing Y signal processing circuit 92, which is given from 0 to the color erasing Y signal processing circuit 92. It includes a color difference signal processing circuit 93 for converting this into analog and providing it to a synchronization circuit (not shown) of the signal processing circuit 3.

The color erasing Y signal processing circuit 92 has an input connected to the output of the line memory 35, reads data from the line memory 35 in synchronization with a read clock given from the memory controller 30, and converts the data into analog. It includes an A conversion circuit 36, an LPF 37 whose input is connected to the output of the D/A conversion circuit 36, and a buffer 38 whose input is connected to the output of the LPF 37 and whose output is connected to the encoder 5.

The color difference signal processing circuit 93 is a D/A conversion circuit whose input is connected to the output of the line memory 35 and reads data from the line memory 35 in synchronization with a read clock given from the memory controller 30 and converts it into analog. 39, an LPF 40 whose input is connected to the output of the D/A conversion circuit 39, and a buffer 41 whose input is connected to the output of the LPF 40 and whose output is connected to a synchronization circuit (not shown) of the signal processing circuit.

The color erasing Y signal is used in the following cases. The dynamic range of a CCD is not very wide. Therefore, when extremely bright light is incident, the light receiving element on the CCD may become saturated. In such a case, charges may not be read out from the light receiving element properly, and the resulting video signal may have an abnormal color. The Y signal for color erasure is intended to prevent such a phenomenon, and removes the color component from the video signal at the time of highlighting. Therefore, the highlighted portion on the screen is mostly white.

The line sequential color difference signal given to the amplifier 32 from the signal processing circuit 3 is two color difference signals (for example, R-YSB-Y).
appear alternately every horizontal scanning line. A light receiving element provided with four different color filters is arranged on the color light receiving CCD. Usually, these four light receiving elements having filters of different colors are arranged in a mosaic pattern. On the other hand, when reading charges from the light receiving element, the charges are first read out to the vertical transfer register of the CCD and then transferred in the vertical direction. By further transferring and processing one after another in the horizontal direction for each stage of light-receiving elements, a video signal for one horizontal scanning line is obtained. Since the light receiving elements are arranged in a mosaic pattern on the CCD as described above, the video signals obtained from each stage represent different color components. Therefore, the color difference signal obtained from the signal processing circuit 3 represents a different color component for each horizontal scanning line.

The aforementioned synchronization circuit (not shown) is a circuit that interpolates color difference signals obtained for every other horizontal scanning line to generate a signal for one intermediate horizontal scanning line. With this circuit,
A signal for each horizontal scanning line can be obtained for each of the two color difference signals.

FIG. 11 is a block diagram of a TBC circuit 67 for correcting time axis errors in the video signal reproduced from the VTR tape 7 by the VTR reproduction circuit 8. The Y signal and C signal output from the VTR reproducing circuit 8 include the VT at the time of reproduction.
This includes deviations in the time axis caused by various factors, such as uneven rotation of the R drive mechanism and uneven contact between the tape and the head (so-called "head striking"). These appear as horizontal fluctuations in the video signal during playback. The function of the TBC circuit is to electrically correct this error.

Referring to FIG. 11, this TBC circuit 67 is a Y signal TBC circuit for receiving and taking the Y signal from the VTR reproducing circuit 8, correcting the time axis error on the Y signal, and outputting it to the buffer 9. 94, a C signal TBC circuit 95 for receiving and receiving the C signal from the VTR reproducing circuit 8, correcting the time axis error on the C signal, and outputting it to the buffer 9;
It is connected to the signal TBC circuit 94 and the C signal TBC circuit 95, and defines the timing of writing data to the memory included in the circuit 94 and 95 in synchronization with the synchronization signal included in the Y signal output from the VTR reproducing circuit 8. a write control circuit 96 and circuits 94 and 95 for outputting a clock to
A read control circuit 9 for outputting a clock having a stable frequency that defines the read timing of data from the memory included in these circuits 94 and 95.
7.

The Y signal TBC circuit 94 has an amplifier 48 for amplifying the Y signal given from the VTR reproduction circuit 8, and an input connected to the output of the amplifier 48, and receives a synchronization signal of the reproduced video signal given from the write control circuit 96. An A/D conversion circuit 50 for digitally converting the signal output from the amplifier 48 in response to a synchronized clock, and an input connected to the output of the A/D conversion circuit 50, and an output of the A/D conversion circuit 50. A line memory 51 for sequentially storing data in synchronization with a clock given from a write control circuit 96 and sequentially outputting stored data in synchronization with a clock given from a read control circuit 97; A D/A converter circuit 52 is connected to the D/A converter circuit 52 for sequentially reading the data stored in the line memory 51 and converting it into analog data in synchronization with a clock given from the read control circuit 97; , and an LPF 53 whose output is connected to the buffer 9.

The C signal TBC circuit 95 includes an amplifier 55 for amplifying the C signal given from the VTR reproducing circuit 8, and an input connected to the output of the amplifier 55, and outputs the signal from the amplifier 55 in synchronization with a clock given from the write control circuit 96. An A/D conversion circuit 56 for digitally converting an analog signal to be output, and an A/D conversion circuit 56 whose input is connected to the output of the A/D conversion circuit 56
A decoder 57 decodes the digitized C signal output from the conversion circuit 56 in synchronization with the clock given from the write control circuit 96 and outputs two digital color difference signals; connected,
Write control circuit 96 for color difference signals output from decoder 57
A line memory 58 has an input connected to the output of the line memory 58 and has an input connected to the output of the line memory 58 to perform read control. circuit 97
an encoder 59 for sequentially reading and encoding the two color difference signal data stored in the line memory 58 in synchronization with a clock given from the line memory 58 and outputting a digital C signal; the input is connected to the output of the encoder 59; is,
A D/A conversion circuit 60 for converting the digital signal output from the encoder 59 into analog in synchronization with the clock given from the readout control circuit 97; Connected BPF
61.

The write control circuit 96 includes a synchronization separation circuit 62 for separating the synchronization signal included in the Y signal output from the VTR reproduction circuit 8, and a clock for generating a clock synchronized with the synchronization signal output from the synchronization separation circuit 62. AFC (Auto
Frequency Control) circuit 63
, a burst separation circuit 100 for separating the burst signal from the C signal given from the VTR reproducing circuit 8, and an APC (Auto Phase Control) for outputting a clock phase-synchronized with the separated burst signal.
trol) circuit 101, and a memory write control circuit 65 for outputting a write clock indicating timing for writing data to the line memory 51, 58 in synchronization with the clocks provided from the AFC circuit 63 and the APC circuit 101. . The read control circuit 97 includes a CXO C crystal oscillation circuit (CXO C crystal oscillation circuit) 64 for generating a stable reference clock, and a read control circuit that defines the read timing of data from the line memories 51 and 58 in synchronization with the reference clock output from the CX064. and a memory read control circuit 66 for generating a clock.

The conventional VTR camera 68a operates as follows. The lens 1 condenses incident light from the subject and forms an optical image of the subject on the light receiving surface of the CCD. The CCD 2 sequentially scans this optical image in the vertical direction, which is the main scanning direction, and the horizontal direction, which is the sub-scanning direction, and converts it into a video signal for each horizontal scanning line and outputs it.

At this time, the CCD 2 is controlled by the camera shake detection section 70, the timing generator 11, and the circuit 10, and performs charge transfer in the vertical direction to compensate for vertical camera shake.

Referring to FIG. 4, in the effective pixel area 77 of the CCD 2,
Pixels are arranged to form more horizontal scanning lines than the number of horizontal scanning lines in the normal NTSC system. That is, the effective pixel area 77 includes a normal vertical transfer area 75 that outputs an NTSC video signal and a normal vertical transfer area 75.
Similarly, the high-speed vertical transfer regions 74 and 76 generate charges for generating a video signal, but the charges are discarded at high speed during the vertical blanking period. By moving the normal vertical transfer area 75 up and down according to the amount of vertical camera shake, vertical camera shake is removed from the video signal output from the CCD 2.

The operation of compensating for vertical camera shake will be explained in more detail with reference to FIGS. 6, 8, and 9.

The vertical shake sensor 14 detects the angular velocity in the vertical direction and provides a signal indicating the angular velocity in the vertical direction to the amplifier 16 of the vertical camera shake detection circuit 84. This signal is amplified by amplifier 16 and given to circuit 17. In circuit 17,
After the noise contained in the amplified signal is removed, the amount of blur in the vertical direction is determined by integrating the angular velocities.

This quantity is output from circuit 17 as an analog signal.

The A/D conversion circuit 18 converts this analog signal into several bits of parallel digital data, and the P/S conversion circuit 1
Give to 9. The P/S conversion circuit 19 converts the applied parallel data into serial data and provides it to the timing generator 11. The timing generator 11 is
The circuit 1 moves the position of the normal vertical transfer area 75 shown in FIG.
0 to compensate for vertical image blur.

FIG. 9(a) shows a vertical transfer pulse applied from the circuit 10 to the CCD 2. In FIG. In FIG. 9(b), C
A read pulse 88 indicating the timing of reading charges from each light receiving element of CD2 to the vertical transfer register is shown.

Referring to FIG. 9, read pulse 88 is applied to CCD 2 within the vertical blanking period. During a read period 89 defined by the read pulse 88, accumulated charges are read from each light receiving element of the CCD 2 to the vertical transfer register. After reading out the charge to the vertical transfer register is completed, the circuit 10 applies a first high speed vertical transfer pulse 87a to the CCD.

In response to the high-speed vertical transfer pulse 87a, the vertical transfer register of the CCD 2 transfers charge at high speed, and a portion corresponding to the high-speed vertical transfer area 76 (FIG. 4) is transferred to an overflow drain provided near the horizontal transfer register of the CCD 2. Sweep out unnecessary charges. The timing generator 11 determines the width of the first high-speed vertical transfer pulse 87a according to the vertical camera shake data provided from the camera shake detection circuit 13, and thereby determines the number of stages of the high-speed vertical transfer area 76.

Thereafter, the circuit 10 applies a normal vertical transfer pulse 86 to the CCD 2 at a constant cycle during a period corresponding to reading out charges from the normal vertical transfer region 75.

The CCD 2 normally transfers one stage of charge in the vertical transfer register to the horizontal transfer register each time one vertical transfer pulse 86 is applied. The horizontal transfer register sequentially transfers charges in the horizontal direction until the next normal vertical transfer pulse 86 is applied to the CCD 2, and provides them to the signal processing circuit 3 as a video signal.

When the vertical charge transfer corresponding to the normal vertical transfer region 75 is completed and the next vertical blanking period begins, the timing generator 11 again applies the second high-speed vertical transfer pulse 87b to the CCD 2. The CCD 2 responds to the high-speed vertical transfer pulse 87b and drains the remaining unnecessary charges to the overflow drain. The width of the high-speed vertical transfer pulse 87b, and therefore the number of stages of the high-speed vertical transfer area 74, is also calculated by the timing generator 11 according to the vertical blur data.

By determining the number of high-speed vertical transfer areas 74 and 76 in accordance with the vertical blur data in this way, the influence of vertical blur can be removed from the video signal output from the CCD 2.

The signal processing circuit 3 processes the video signal provided from the CCD 2 and provides the horizontal camera shake compensation circuit 4 with a Y signal, a Y signal for color erasing during highlighting, and a line-sequential color difference signal.

With particular reference to FIG. 10, Y signal compensation circuit 90 operates as follows. The Y signal applied to the amplifier 24 is amplified by the amplifier 24 and applied to the A/D conversion circuit 25. The memory controller 30 provides a write clock having a predetermined frequency to the A/P conversion circuit 25 and the line memory 26.

According to this write clock, the A/D conversion circuit 25
The input analog signal is digitized and the line memory 2
Give to 6. The line memory 26 sequentially stores the digital signals output from the A/D conversion circuit 25 in accordance with the write clock from the memory controller 30. At this time,
The memory controller 30 determines the time to start writing data to the line memory 26 according to the horizontal shake data provided from the camera shake detector 70. By shifting the writing start time forward or backward, the video signal written into the line memory 26 moves to the left or right to some extent within one horizontal scanning line.

Data read from line memory 26 is output according to a read clock having a slower frequency than the write clock. Among the signals for one horizontal scanning line of the Y signal input to the Y signal compensation circuit 90, only the necessary portion of the signal is expanded as a signal for one horizontal scanning line and output. By shifting the start time of writing data into the line memory 26, it is possible to compensate for horizontal blur represented by horizontal blur data.

The video signal read from the line memory 26 is converted into an analog signal by the D/A conversion circuit 27, and is applied to the encoder 5 via the LPF 28 and the buffer 29.

FIG. 7 shows a timing diagram showing horizontal blur compensation performed in the Y signal compensation circuit 90.

Referring to FIG. 7(a) and FIG. 10, a horizontal synchronization signal HD is applied to the memory controller 30 from the 5SG12. The A/D conversion circuit 25 digitizes the manually input analog signal for each horizontal scanning period defined by the horizontal synchronization signal HD, and provides the digitized signal to the line memory 26.

It is assumed that the A/D conversion circuit 25 starts outputting the signal 81 for one horizontal scanning line at time to. The memory controller 30 determines the data writing timing t1 to the line memory 26 based on the horizontal shake data provided from the camera shake detector 70. Therefore, the digitized Y signal 82 is stored in the line memory 26 at time t1.
written from. The memory controller 30 finishes writing data to the line memory 26 at time t2, which has elapsed for a certain period of time from the writing start time t1. That is, the time between times t1 and t2 is constant.

Writing to the line memory 26 is not performed from time t2 to end time t3 of this horizontal scanning period.

When the writing of the digitized Y signal 82 to the line memory 26 is completed, the memory controller 30 reads the stored contents and outputs them to the D/A conversion circuit 27 in accordance with the read tarlock. As mentioned above, the read clock is slightly slower than the write clock. Therefore, as shown in FIG. 7(d), the transmission signal 83 applied to the D/A conversion circuit 27 is time-base converted to a length corresponding to one horizontal scanning period.

The memory controller 30 converts the time tO to t1 based on the horizontal blur data, so that the video signal 82 moves left and right within one horizontal scanning line of the original video signal. This makes it possible to eliminate the influence of horizontal camera shake on the Y signal.

The operation of the colored yarn signal compensation circuit 91 is also similar to that of the Y signal compensation circuit 90. The Y signal for color erasing and the line sequential color difference signal are amplified by amplifiers 31 and 32, respectively, and provided to a multiplexer 33.

The multiplexer 33 multiplexes the color erasing Y signal and the line-sequential color difference signal in accordance with the clock supplied from the memory controller 30 and supplies the multiplexed signal to the A/D conversion circuit 34. The A/D conversion circuit 34 digitizes the analog signal output from the multiplexer 33 in accordance with the write clock given from the memory controller 30 and supplies it to the line memory 35.

The memory controller 30 determines the start timing of writing data to the line memory 35 in accordance with the horizontal blur data, similarly to the Y signal compensation circuit 90. As a result, only the necessary portion of the signal for one horizontal scanning line is written into the line memory 35. Memory controller 3
0 causes data to be output from the line memory 35 using a read clock slower than the write clock when writing to the line memory 35 is completed. The output of the line memory 35 is given to a color erasing Y signal processing circuit 92 and a color difference signal processing circuit 93.

The signal output from the line memory 35 is a Y signal for color erasure and a line sequential color difference signal arranged alternately by the multiplexer 33. Therefore, the color erasing Y signal processing circuit 92 extracts only the color erasing Y signal from among the manually input signals, processes it, and supplies it to the encoder 5. On the other hand, the color difference signal processing circuit 93 extracts only the color difference signal from the output of the line memory 35 and supplies it to a synchronization circuit (not shown) of the signal processing circuit.

The D/A conversion circuit 36 of the color erasing Y signal processing circuit 92 converts the digital signal provided from the line memory 35 into an analog signal in response to the readout clock provided from the memory controller 30, and provides the analog signal to the LPF 37. The output of the LPF 37 is provided to the encoder 5 via a buffer 38.

The D/A conversion circuit 39 of the color difference signal processing circuit 93 is given a clock whose phase is inverted from the readout signal given to the D/A conversion circuit 36 from the memory controller 30, and according to this clock, the digital signal output from the line memory 35 is Analogize the signal. The output of the D/A conversion circuit 39 is applied to the synchronization circuit of the signal processing circuit 3 via an LPF 40 and a buffer 41. The synchronization circuit generates all scanning lines for each of the color difference signals RY and BY by interpolating the line sequential color difference signals as described above. The horizontal blur compensation in the colored thread signal compensation circuit 91 is essentially the same as that of the Y signal compensation circuit 90 described with reference to FIG.

The signal processing circuit 3 synchronizes the color difference signals given from the horizontal camera shake compensation circuit 4 and supplies them to the encoder 5 . Encoder 5 synchronizes with the clock given from 5SG12.
The signal and the color difference signal are encoded and provided to the VTR recording circuit 6 as a composite video signal. The VTR recording circuit 6 records this signal on the VTR tape 7.

The VTR deck 69a operates as follows.

The VTR reproducing circuit 8 reproduces the video signal recorded on the VTR tape 7, separates it into a Y signal and a C signal, and supplies the Y signal and C signal to the TBC circuit 67. At this time, due to various factors such as uneven rotation of the VTR's playback mechanism and uneven contact between the tape and the head,
The reproduced video signal includes time axis errors that appear as horizontal fluctuations in the video.

Referring to FIG. 11, the Y signal is amplified by amplifier 48 and then provided to A/D conversion circuit 50.

After the C signal is also amplified by the amplifier 55, the A/D conversion circuit 5
given to 6. The Y signal is also applied to a sync separation circuit 62, which separates a horizontal sync signal from the Y signal and provides it to an AFC circuit 63.

The AFC circuit 63 generates a clock synchronized with the applied horizontal synchronization signal and supplies it to the memory write control circuit 65. The memory write control circuit 65 controls the A/D conversion circuit 50 and the line memory 51 in response to this clock, digitizes the Y signal, and writes the Y signal to the line memory 5.
1 sequentially.

The C signal is also applied to burst separation circuit 100. The burst separation circuit 100 separates the burst signal from the C signal and provides it to the APC circuit 101. The APC circuit 101 generates a clock phase-synchronized with the burst signal and supplies it to the memory write control circuit 65. The memory write control circuit 65 provides the A/D conversion circuit 56 and the decoder 57 with a clock that is phase synchronized with the subcarrier (burst signal) in the video signal, which is provided from the APC circuit 101 . The A/D conversion circuit 56 digitizes the C signal and provides it to the decoder 57. The decoder 56 decodes the input digitized C signal and converts the frequency into two color difference signals at the same time, and provides these color difference signals to the line memory 58 .

The memory write control circuit 65 supplies the line memory 58 with the same clock as the clock for writing the Y signal to the line memory 51. The line memory 58 sequentially stores the input color difference signals in synchronization with this clock.

The CXO circuit 64 oscillates a reference clock at a stable frequency and provides it to the memory read control circuit 66. Memory read control circuit 66 provides the reference clock provided from CXO circuit 64 to line memory 51 and line memory 58 as a read clock. Line memory 51 sequentially supplies the stored data to D/A conversion circuit 52 in response to this read clock. The memory read control circuit 66 converts the read clock into a D/A
It is also applied to a conversion circuit 52, and the D/A conversion circuit 52 converts the input digital signal into an analog signal and applies it to the LPF 53. The output of the LPF 53 is sent to the monitor via the buffer 9.

Data read from line memory 58 is provided to encoder 59. The encoder 59 performs frequency conversion and encoding of the color difference signal using a clock synchronized with the subcarrier (burst signal), and supplies the signal to the D/A conversion circuit 60 . The digital C signal output from the encoder 59 is
Analog conversion is performed by the D/A conversion circuit 60 according to the same clock. The analog C signal is BPF61
The signal is then applied to the buffer 9 and sent to the monitor.

In the TBC circuit 67, data is written into the line memories 51 and 58 as described above using a clock synchronized with the horizontal synchronization signal of the input Y signal. Similarly, reading data from line memory 5L 58 is performed using CX.
This is performed according to a stable reference clock provided from the O circuit 64.

As a result, horizontal fluctuations in the video caused by uneven rotation of the reproducing mechanism during playback, uneven contact between the tape and the head, etc. are attenuated, and a stable video signal can be obtained.

[Problems to be Solved by the Invention] As described above, the horizontal shake compensation circuit of the conventional camera-integrated VTR is composed of a digital circuit.

The power consumption of digital circuits, such as A/D conversion circuits, memories, and D/A conversion circuits, is generally large.

On the other hand, a camera-integrated VTR is usually portable and is often driven by a battery, especially during recording. Since the horizontal camera shake compensation circuit operates during recording, it consumes a lot of power, which is disadvantageous for extending battery life.

Therefore, the purpose of this invention is to reduce power consumption and
An imaging device capable of obtaining a video signal capable of compensating for camera shake in a reproduced video signal, and a video signal capable of reproducing the video signal recorded by the imaging device without adverse effects caused by camera shake. The purpose of the present invention is to provide a playback device.

[Means for Solving the Problems] An imaging device according to the invention according to claim 1 includes an optical system for condensing incident light from a subject and forming an optical image of the subject on a predetermined surface; An imaging means for scanning an image in a predetermined main scanning direction and a sub-scanning direction intersecting the main scanning direction and converting the image into a video signal; a blur detection means for outputting a blur signal, a blur signal insertion means for inserting a blur signal into a vertical blanking period of a video signal, and a video signal for recording the video signal into which the blur signal has been inserted onto a predetermined recording medium. and signal recording means.

The video signal reproducing device according to the invention as set forth in claim 2 provides a video signal reproduction device that is generated by scanning a subject in a predetermined main scanning direction and a sub-scanning direction that intersects with the main scanning direction, and that is recorded on a predetermined recording medium. This is a device for reproducing a signal, and a blur signal indicating the amount of blur in the sub-scanning direction during imaging is recorded during a vertical blanking period of a recorded video signal. This video signal reproducing device includes a reproducing means for reproducing a video signal recorded on a recording medium, a blur signal extracting means for extracting a blur signal from the video signal reproduced by the reproducing means, and a blur signal extracting means for extracting a blur signal from the video signal reproduced by the reproducing means. and blur compensation means for compensating for blur in the sub-scanning direction of the video signal based on the signal.

According to the video signal reproducing device according to the invention set forth in claim 3, in the device set forth in claim 2, the video signal includes a predetermined first synchronization signal. In this device, the compensation means includes a synchronization signal extraction means for extracting a first synchronization signal from the video signal reproduced by the reproduction means, and a synchronization signal for outputting a second synchronization signal having a predetermined constant period. In response to the output means, the extracted first synchronization signal, the second synchronization signal, and the shake signal, compensation is made for one shake in the sub-scanning direction of the video signal, which occurs during playback by the playback means. and a time axis error correction means for correcting an error in the time axis of the video signal.

[Function] In the imaging device according to the invention described in claim 1, the video signal is not corrected due to camera shake in the sub-scanning direction. However, since a shake signal indicating the amount of camera shake is inserted into the video signal and recorded on the recording medium, it is possible to correct the shake in the sub-scanning direction of the video signal based on this shake signal during playback. .

The video signal reproducing device according to the second aspect of the present invention can extract a blur signal recorded in the video signal, and can compensate for blur in the sub-scanning direction of the video by the compensating means based on the blur signal. Therefore, it is possible to reproduce the video signal recorded by the imaging device according to the first aspect of the present invention and obtain a video with blur in the sub-scanning direction removed.

The video signal reproducing device according to the invention described in claim 3 compensates for blur in the sub-scanning direction based on the blur signal recorded in the video signal, and at the same time corrects the time axis error of the video signal during playback by the same means. can do.

[Embodiment] FIG. 1 is a block diagram of a VTR camera 68 as an imaging device and a VTR deck 69 as a video signal reproducing device according to the present invention. Referring to FIG. 1, the VTR camera 6
Reference numeral 8 denotes a lens 1 as an optical system for condensing incident light from a subject and forming an optical image on a predetermined imaging plane, and an imaging means for converting the formed optical image into a video signal. A signal processing circuit 3 performs necessary processing to convert the video signal output from the CCD 2 into a composite video signal, detects camera shake from the VTR camera 68, and generates a signal indicating vertical blur data and horizontal blur data. A camera shake detector 70 that outputs a synchronization signal and a 5SG12 that generates a synchronization signal that defines the operation timing of the entire device; Based on the vertical blur data, C
A timing generator 11 that controls the CD 2 and the signal processing circuit 3 and removes the effects of vertical camera shake from the video signal, and a horizontal transfer pulse and a vertical transfer pulse that are controlled by the timing generator 11 and drive the CCD 2. H-driver that generates, ■-driver circuit 10, signal processing circuit 3.5SG12, camera shake detection section
0 and encodes the Y signal and C signal given from the signal processing circuit 3.
an encoder 5a for inserting horizontal camera shake compensation data given from 0 into the vertical blanking period of the video signal;
It includes a VTR recording circuit 6 for recording on a tape 7.

The VTR deck 69 includes a VTR reproducing circuit 8 for reproducing video signals from the VTR tape 7;
The horizontal direction camera shake compensation data is extracted from the Y signal and C signal output from the camera, and based on that data, the horizontal direction video signal is digitally compensated for, and at the same time, the time axis error of the video signal is corrected. The circuit includes a TBC and horizontal camera shake compensation circuit 42 for performing the operation, and a buffer 9 for buffering the output of the TBC and horizontal camera shake compensation circuit 42 and providing it to a monitor (not shown).

Identical parts have been given the same reference numerals and names in FIGS. 1 and 6. In FIG. Their functions are also the same. Therefore, detailed explanations about them will not be repeated here.

Referring to FIG. 2, the encoder 5a receives the Y signal from the signal processing circuit 3 and inserts a composite blanking (C-BLK) signal, a composite synchronization (C-SYNC) signal, and horizontal camera shake data into the Y signal. Y for giving to the VTR recording circuit 6
The signal encoder circuit 98 receives and receives color difference signals R-Y and B-Y from the signal processing circuit 3, and modulates and multiplexes them using two subcarriers SCI and SC2 that have the same frequency but are out of phase by 90 degrees. generate a C signal by
It also includes a C signal encoder circuit 99 for inserting a burst signal into the C signal according to the burst flag BF and providing it to the VTR recording circuit 6.

The Y signal encoder circuit 98 includes an amplifier 43 for amplifying and outputting the Y signal received and received from the signal processing circuit 3, and a C-BLK signal for mixing the C-BLK signal with the Y signal amplified by the amplifier 43. BLK mix circuit 44 and C
- C-SY is added to the signal output from the BLK mix circuit 44.
During the vertical blanking period of the video signal output from the C-8YNC mix circuit 45 for mixing the NC signal and the C-5YNC mix circuit 45, the camera shake detector 70
a horizontal camera shake data mix circuit 46 for inserting horizontal camera shake data given from the digital signal as a digital signal;
An amplifier 47 for amplifying the video signal output from the horizontal camera shake data mix circuit 46 and feeding it to the VTR recording circuit 6
including.

Referring to FIGS. 1 and 2, the VTR camera 68 according to the present invention operates as follows. The lens 1 collects incident light from a subject and forms an optical image on a predetermined imaging plane.

The CCD 2 transfers charges accumulated in photoelectric elements on its light-receiving surface in the main scanning direction and the sub-scanning direction, thereby converting them into video signals and providing them to the signal processing circuit 3 . At this time,
Reading of signals from the CCD 2 is controlled according to vertical shake data provided from the camera shake detector 70. This eliminates the influence of vertical camera shake on the video signal. The method is the same as done in conventional VTR cameras. Therefore, detailed explanation thereof will not be repeated here.

The signal processing circuit 3 processes the video signal from the CCD 2 by performing DC reproduction, automatic gain control, carrier removal, γ correction, color separation,
Performs white balance, color difference signal generation processing, etc.
signal and color difference signal R-Y.

Give B-Y to the encoder 5a.

Referring to FIG. 2, Y signal encoder circuit 98 inserts a C-BLK signal and a c-syNC signal into the video signal. The Y signal encoder circuit 98 further inserts the horizontal camera shake data given from the camera shake detector 70 as a digital signal into the vertical blanking period of the video signal by the horizontal camera shake data mix circuit 46 .

Referring to FIG. 5, the vertical blanking period is C-5Y
It is inserted into the video signal 78 by the NC mix circuit 45. Horizontal camera shake data mix circuit 46
inserts a digital signal 79 indicating horizontal camera shake data into the video signal during the vertical blanking period. The horizontal camera shake data is 7 bits of serial data, as will be described later.

Therefore, even if the transfer rate is slow (IH (horizontal scanning period)), horizontal blur data is sufficiently contained.
In order to ensure that magnetic recording tape is reliably recorded and reproduced, and to increase reliability, the same horizontal blur data is written in several H numbers. The video signal into which the horizontal blur data has been inserted is recorded on a VTR tape 7 via a VTR recording circuit 6.

Referring to FIG. 7, as already explained, the horizontal camera shake data is the time from the start of one horizontal scanning period to the start of digital writing to the line memory, that is, the time t.
This is done by changing O-tl according to the amount of horizontal camera shake. The horizontal camera shake data represents, for example, the time tO to t1 using 7-bit digital data in 128 steps.

As a result, the time tO
~t1 is adjusted in 128 steps to compensate for horizontal camera shake.

Referring to FIG. 3, the TBC and horizontal camera shake compensation circuit 42 of the VTR deck 69 (see FIG. 1) receives and receives the Y signal from the VTR reproducing circuit 8, and removes the horizontal camera shake included in the Y signal. A Y signal processing section 71 receives the C signal from the VTR reproducing circuit 8 and receives the C signal from the VTR reproducing circuit 8. 71, a C signal processing unit 72 for compensating the horizontal blur of the C signal based on the horizontal blur data extracted from the Y signal, and at the same time correcting the time axis error of the C signal, and a Signal and C
It receives the signal, extracts a synchronization signal from the Y signal and a burst signal from the C signal, receives horizontal camera shake data from the Y signal processing section 71, and receives the Y signal processing section 71 and the C signal processing section 72. and a timing control section 73 for controlling horizontal camera shake and time axis error of each signal.

The Y signal processing section 71 includes an amplifier 4 for amplifying the Y signal.
8, a horizontal camera shake data extraction circuit 49 for extracting horizontal camera shake data from the Y signal output from the amplifier 48 and providing it to the timing control section 73; and a horizontal camera shake data extraction circuit 49 for receiving and receiving video signals from the horizontal camera shake data extraction circuit 49. The timing control section 7
3, an A/D conversion circuit 50 for digitizing according to a clock synchronized with a horizontal synchronization signal given from 3;
The input is connected to the output of the D conversion circuit 50, and the output of the A/D conversion circuit 50 is sequentially stored in accordance with a clock synchronized with the horizontal synchronization signal given from the timing control section 73.
A line memory 51 for sequentially outputting stored data according to a stable reference clock given from the timing control unit 73, and converting the digital signal outputted from the line memory 51 into analog according to the stable reference clock given from the timing control unit 73. and an LPF 53 whose input is connected to the output of the D/A conversion circuit 52 and whose output is connected to the buffer 9 (FIG. 1).

The C signal processing section 72 receives and receives C signals from the VTR reproducing circuit 8.
An amplifier 55 for amplifying the signal and a C signal outputted from the amplifier 55 are given from a timing control section 73.
An A/D conversion circuit 56 for digital conversion according to a clock phase-synchronized with the burst signal of the C signal;
a decoder 57 for decoding and frequency converting the digitized C signal output from the conversion circuit 56 according to a clock synchronized with the burst signal provided from the timing control section 73 and outputting two color difference signals; The timing control unit 7
A line memory 58 for sequentially storing stored data in accordance with a clock synchronized with the horizontal synchronization signal given from the timing control unit 73 and sequentially outputting stored data in accordance with a stable reference clock given from the timing control unit 73; A D/A conversion circuit 60 converts data into analog according to a stable reference clock given from a timing control section 73, and encodes the analogized color difference signal outputted from the D/A conversion circuit 60 as a C signal. It includes an encoder 59 for output and a BPF 61 whose input is connected to the output of the encoder 59 and whose output is connected to the buffer 9 (FIG. 1).

The timing control section 73 includes a synchronization separation circuit 62 for separating a horizontal synchronization signal from the Y signal output from the VTR reproduction circuit 8, and an AFC for generating a clock synchronized with the horizontal synchronization signal output from the synchronization separation circuit 62. The circuit 63 and V
A burst separation circuit 100 for separating the burst signal from the C signal output from the TR regeneration circuit 8, an APC circuit 101 for outputting a clock phase-synchronized with the burst signal output from the burst separation circuit 100, and a stable reference. CXO circuit 64 for generating clock and AFC
It is connected to the circuit 63, the APC circuit 101, the CXO circuit 64, and the horizontal camera shake data extraction circuit 49. It also includes a memory controller 54 for controlling the supplied clock and changing the data write timing in accordance with the horizontal camera shake data.

The horizontal camera shake compensation operation performed in circuit 42 is similar to the conventional technique already described with reference to FIG. However, since it is necessary to process the Y signal including the synchronization signal and the C signal modulated by the subcarrier, it has a slightly different configuration from the horizontal camera shake compensation circuit 4 shown in FIG. .

Referring to FIGS. 1 and 3, the VTR deck 69 according to the present invention operates as follows. The VTR reproducing circuit 8
The video signal recorded on the TR tape 7 is reproduced and applied to the TBC and horizontal camera shake compensation circuit 42 as a Y signal and a C signal.

The synchronization separation circuit 62 separates the horizontal synchronization signal from the Y signal,
It is applied to the AFC circuit 63. The AFC circuit 63 generates a clock synchronized with the horizontal synchronization signal and outputs a clock to the memory controller 5.
Give to 4. The burst separation circuit 100 separates the burst signal from the C signal and supplies it to the APC circuit 101. APC
The circuit 101 generates a clock phase-synchronized with the burst signal and supplies it to the memory controller 54. CXO circuit 6
4 generates a stable reference clock and supplies it to the memory controller 54.

The Y signal amplified by the amplifier 48 is given to a horizontal camera shake data extraction circuit 49. Horizontal camera shake data extraction circuit 49
extracts horizontal camera shake data 79 (FIG. 5) from the vertical blanking period of the video signal and stores it in the memory controller 54.
give to The video signal is then given to an A/D conversion circuit 50.

The memory controller 54 controls the A/D conversion circuit 50 and the line memory 51 to digitize the video signal and sequentially store it in the line memory 51 in accordance with a clock synchronized with the horizontal synchronization signal provided from the AFC circuit 63. The memory controller 54 further takes out the stored data from the line memory 51 in accordance with a stable reference clock that is slower than the write clock provided by the CXO circuit 64, and converts it into an analog signal by the D/A conversion circuit 52. The converted analog Y signal is applied to the buffer 9 via the LPF 53.

As described above, writing of the video signal to the line memory 51 is performed using a clock synchronized with the horizontal synchronization signal of the input Y signal. Reading of the video signal from the line memory 51 is performed using a stable reference clock provided from the CXO circuit 64. As a result, horizontal fluctuations in the video signal output from the Y signal processing section 71 are attenuated. The memory controller 54 also changes the start point of writing data into the line memory 51 according to the horizontal camera shake data provided from the horizontal camera shake data extraction circuit 49 . As a result, compensation for horizontal blur is also performed, and a stable image can be sent to the output of the Y signal processing section 71.

The C signal processing section 72 operates as follows. amplifier 55
The C signal amplified in is digitized by an A/D conversion circuit 56, decoded and frequency converted by a decoder 57, and provided to a line memory 58 as two digital color difference signals. A/D conversion circuit 56
, the decoder 5I7 is operated by a clock provided from the memory controller 54 and synchronized in phase with the burst signal. Writing of the color difference signal to the line memory 58 is performed according to a clock synchronized with the horizontal synchronization signal of the Y signal, which is provided from the memory controller 54. At this time, the timing at which data is started to be written into the line memory 58 is changed back and forth according to the horizontal camera shake data provided from the horizontal camera shake data extraction circuit 49.

From the line memory 58, according to a clock synchronized with a stable reference clock given from the CXO circuit 64,
Data reading is performed. The frequency of this clock is lower than that of the data write clock to the line memory 58. This data is transferred to the D/A conversion circuit 6
0, it is converted into analog data using the same clock and provided to the encoder 59. The encoder 59 is the D/A conversion circuit 6
Two analog color difference signals given from 0 are encoded, frequency converted, and sent to the buffer 9 as a C signal via the BPF 61.

In the C signal processing section 72, as in the Y signal processing section 71, horizontal camera shake and time axis errors of the transfer signal are removed. Therefore, a stable video signal can be obtained as the C signal.

As described above, according to the present invention, there is no need to provide the horizontal camera shake compensation circuit 4 in the VTR camera 68.

Since the horizontal camera shake compensation circuit 4, which uses many digital circuits, is no longer necessary, the power consumption of the VTR camera 68 during recording is reduced. Therefore, it is possible to extend the life of the battery or reduce the size of the battery.

In the embodiment described above, the VTR camera 68 and the VTR
The case where the deck 69 is separate has been described. However, the present invention is not limited thereto, and the playback function of the VTR deck 69 may be incorporated into the VTR camera 68. That is, the VTR camera 68 may be a camera-integrated VTR capable of recording and reproducing. In this case, the VTR camera 68 incorporates the TBC and the horizontal camera shake compensation circuit 42, which consume a large amount of power.

However, this circuit operates only during playback, not during recording. Playback is usually done indoors and VT
The R camera 68 is often supplied with power from an external power source rather than a battery. Therefore, there is no adverse effect on battery power consumption during recording.

Further, in the above-described embodiment, the VTR deck 69 has a T.
A circuit that also functions as a BC and horizontal camera shake compensation circuit 42 is incorporated. However, this circuit may be separated into two circuits: a circuit dedicated to TBC and a horizontal camera shake compensation circuit.

As in this embodiment, the TBC and the horizontal camera shake compensation circuit 42
The efficiency of the VTR deck 69 will be better if the circuits are grouped together as one. However, even if these circuits are separated, the effect of saving the battery consumption during recording of the VTR camera 68 and the VTR camera 68 can be improved.
Images captured by TR Camera 68 are shake-free.
Moreover, the effect of being able to reproduce without horizontal fluctuation remains unchanged.

[Effects of the Invention] As described above, according to the invention set forth in claim 1, a blur signal can be recorded in a video signal. It becomes possible to correct the video signal on the playback side based on this blur signal, and there is no need to provide a circuit with large power consumption to compensate for blur in the sub-scanning direction on the imaging device side. The power consumption of the imaging device during recording can be reduced, making it possible to downsize the battery and extend the life of the battery.

According to the second aspect of the invention, it is possible to compensate for camera shake in the video signal during playback based on the blur signal inserted into the video signal. It is not necessary to provide the imaging device with a circuit that consumes a large amount of power to compensate for blur in the sub-scanning direction, and the power consumption of the imaging device can be reduced. Therefore, it is possible to provide a video signal reproducing device that allows the battery of the imaging device to be made smaller or to have a longer lifespan.

According to the invention set forth in claim 3, in the invention set forth in claim 2, time axis correction of the reproduced video signal and compensation for blur in the sub-scanning direction are simultaneously performed by the same circuit. Therefore, without increasing the size of the video signal reproducing device, part of the blur compensation function of the imaging device can be performed on the reproducing device side. - This circuit consumes a lot of power when fishing on a boat, and the power consumption of the imaging device during recording can be significantly reduced. Therefore, it is possible to provide a video signal reproducing device that can further downsize the battery of the imaging device or extend its lifespan without increasing the size of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the VTR camera and VTR deck according to the present invention, FIG. 2 is a block diagram of the encoder of the VTR camera according to the present invention, and FIG. 3 is a block diagram of the TBC and VTR deck of the VTR deck according to the present invention. FIG. 4 is a block diagram of the horizontal camera shake compensation circuit, FIG. 4 is a schematic diagram of the effective pixel area of a CCD as an imaging means, and FIG. 5 is a block diagram of the horizontal camera shake compensation circuit, and FIG. FIG. 6 is a block diagram of a conventional VTR camera and VTR deck, FIG. 7 is a timing chart for explaining horizontal camera shake compensation, and FIG. 8 is a waveform diagram for camera shake detection. FIG. 9 is a timing chart showing the operation of the CCD to compensate for vertical shake, and FIG. 10 is a block diagram of a horizontal camera shake compensation circuit for a conventional VTR camera. , FIG. 11 is a block diagram of a TBC circuit of a conventional VTR deck. In the figure, 1 is a lens, 2 is a CCD, 3 is a signal processing circuit, and 5
a is an encoder, 6 is a VTR recording circuit, 7 is a VTR tape, 8 is a VTR playback circuit, 42 is a TBC and horizontal camera shake compensation circuit, 46 is a horizontal camera shake data mix circuit, 49 is a horizontal camera shake data extraction circuit , 68 HaV T
69 is a VTR deck, 70 is a camera shake detection section, 71 is a Y signal processing section, 72 is a C signal processing section, and 73 is a timing control section. In addition, the same symbols in the figures indicate the same or equivalent parts. Figure 7, Figure 8, I3, Figure 0, Figure 10.

Claims (3)

[Claims] (1) an optical system for condensing incident light from a subject and forming an optical image of the subject on a predetermined surface;
an imaging means for scanning in a predetermined main scanning direction and a sub-scanning direction intersecting the main scanning direction and converting the image into a video signal; blur detection means for outputting, blur signal insertion means for inserting the blur signal into a vertical blanking period of the video signal, and recording the video signal into which the blur signal has been inserted on a predetermined recording medium. and a video signal recording means. (2) A video signal reproducing device for reproducing a video signal generated by scanning a subject in a predetermined main scanning direction and a sub-scanning direction intersecting the main scanning direction and recorded on a predetermined recording medium. In the vertical blanking period of the recorded video signal,
A blur signal indicating the amount of blur in the sub-scanning direction at the time of imaging is recorded, a reproducing means for reproducing the video signal recorded on the recording medium, and the video reproduced by the reproducing means. A video signal reproduction comprising: a blur signal extracting means for extracting the blur signal from a signal; and a blur compensating means for compensating for blur in the sub-scanning direction of the video signal based on the extracted blur signal. Device. (3) the video signal includes a predetermined first synchronization signal, and the compensation means includes synchronization signal extraction means for extracting the first synchronization signal from the video signal reproduced by the reproduction means; synchronization signal output means for outputting a second synchronization signal with a predetermined constant period; and in response to the extracted first synchronization signal, the second synchronization signal, and the blur signal, 3. The video image display device according to claim 2, further comprising time axis error correction means for compensating for blurring of the video signal in the sub-scanning direction and at the same time correcting an error on the time axis of the video signal that occurs during reproduction by the reproduction means. Signal regenerator.