JPH0481112A - Method of packaging fixed delay line - Google Patents

Method of packaging fixed delay line

Info

Publication number
JPH0481112A
JPH0481112A JP19446990A JP19446990A JPH0481112A JP H0481112 A JPH0481112 A JP H0481112A JP 19446990 A JP19446990 A JP 19446990A JP 19446990 A JP19446990 A JP 19446990A JP H0481112 A JPH0481112 A JP H0481112A
Authority
JP
Japan
Prior art keywords
delay line
fixed delay
pin
output pins
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19446990A
Other languages
Japanese (ja)
Inventor
Kenichi Omae
大前　憲一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19446990A priority Critical patent/JPH0481112A/en
Publication of JPH0481112A publication Critical patent/JPH0481112A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve the waveform of a signal passing through the fixed delay line by employing surface packaging type input output pins for the fixed delay line. CONSTITUTION:A fixed delay line 1 has input output pins 3, 4 and a signal inputted from one pin is outputted to the other pin with a prescribed delay. Moreover, the fixed delay line 1 has GND pins 2 at both sides of each signal pin, in total four GND pins 2. Each GND pin 2 is designed long so as to be inserted into a contact 7 packaged to a throughhole and the input output pins 3, 4 are designed very short. Since a signal is inputted/outputted to/from the input output pins of the delay line not through the throughhole type contact, distortion hardly occurs to the waveform.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固定ディレーライ る。[Detailed description of the invention] [Industrial application field] The present invention is a fixed delay line. Ru.

〔従来の技術〕[Conventional technology]

ンの実装方法に関す 従来の固定ディレーラインの実装方法は、取り替える必
要性があるという理由から基板上にスルーホール実装の
コネクタを実装し前記コネクタに固定ディレーラインの
全ピンを挿入する方法で実装を行なっていた。The conventional fixed delay line mounting method is to mount a through-hole connector on the board and insert all pins of the fixed delay line into the connector because it needs to be replaced. was doing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の固定ディレーラインの実装方法は全ピン
についてスルーホール実装のコネクタを用いているため
、ディレーラインの入力部と出力部、各１個のスルーホ
ールおよびコネクタのコンタクト部分のインダクタンス
成分および容量成分による波形の歪が生じる一方、プリ
ント配線板側から見るとコンタクトをスルーホールに実
装するためスルーホールの径が大きくなり、前記スルー
ホールの数だけプリント配線板上に穴があき、この分だ
けプリント配線板上の配線可能エリアが減少するという
欠点がある。The conventional fixed delay line mounting method described above uses through-hole mounted connectors for all pins, so the inductance component and capacitance of the input and output parts of the delay line, one through hole each, and the contact part of the connector are On the other hand, when viewed from the printed wiring board side, since the contacts are mounted in the through holes, the diameter of the through holes becomes larger, and the number of holes on the printed wiring board equal to the number of through holes is created. This has the disadvantage that the wiring area on the printed wiring board is reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の固定ディレーラインの実装方法は、入出力ピン
については短いビンを出す固定ディレーライン本体と、
前記固定ディレーラインを受けるプリント配線板上のコ
ネクタにおいて、前記入出力ピンに対応したコンタクト
に関しては表面実装を使用したコネクタを有している。The fixed delay line mounting method of the present invention includes a fixed delay line main body with short bins for input/output pins,
In the connector on the printed wiring board that receives the fixed delay line, the contact corresponding to the input/output pin has a connector using surface mounting.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す側面図である。FIG. 1 is a side view showing an embodiment of the present invention.

固定ディレーライン１は入出力用ピン３，４を有し、片
方のピンから入力した信号は一定のディレーを持っても
う一方のピンへ出力される。The fixed delay line 1 has input/output pins 3 and 4, and a signal inputted from one pin is outputted to the other pin with a certain delay.

又、同時に固定ディレーライン１は信号ピンの両側にＧ
ＮＤピン２を持ち、合計４本のＧＮＤピン２を持つ。At the same time, fixed delay line 1 has G on both sides of the signal pin.
It has ND pin 2 and a total of 4 GND pins 2.

ＧＮＤピア２はスルーホールに実装されたコンタクト７
へ挿入するよう長いピンで設定されているが、入出力ピ
ン３．４は非常に短いピンで設定されている。GND peer 2 is a contact 7 mounted in a through hole
The input/output pins 3.4 are configured with very short pins.

固定ディレーライン１の下にプリント配線板５の上には
んだ１０により固定された固定ディレーライン用コネク
タ６（コンタクト７．８の保持用）かあり、これに組み
込まれたＧＮＤピン接続用コンタクト７および表面実装
を用、いた入出力ピン接続用コンタクト８．９かある。Below the fixed delay line 1, there is a fixed delay line connector 6 (for holding contacts 7.8) fixed on the printed wiring board 5 with solder 10, and the GND pin connection contact 7 and There are 8 and 9 contacts for connecting input and output pins using surface mounting.

固定ディレーライン１のＧ　Ｎ　Ｄピン２はコネクタ６
のコンタクト７へ挿入され固定ディレーラインの保持と
ＧＮＤ接続の働きをする。GND pin 2 of fixed delay line 1 is connected to connector 6
It is inserted into the contact 7 of the circuit and functions to hold the fixed delay line and connect it to GND.

一方固定ディレーライン１の入出力ピン３および４はコ
ネクタ６のコンタクト８．および９に接続され、コネク
タ側のコンタクト８．９はプリント配線板５の上のバッ
トを通し配線か行なわれる。On the other hand, input/output pins 3 and 4 of fixed delay line 1 are connected to contacts 8. and 9, and the contacts 8.9 on the connector side are wired through the butts on the printed wiring board 5.

以上の構成により、ディレーラインの入出力ピンはスル
ーホールタイプのコンタクトを通さすに信号を入出力す
るため波形に歪か生しにくくなる。一方プリント配線板
側でも入出力ピンに対応する場所には第１図に示すよう
なコンタクト７を実装するスルーホールか不要となるた
め、この分だけ内層の信号パターンが通すことかできる
。With the above configuration, the input/output pins of the delay line input/output signals through through-hole type contacts, making it difficult for distortion to occur in the waveform. On the other hand, on the printed wiring board side, there is no need for through-holes for mounting contacts 7 as shown in FIG. 1 in locations corresponding to input/output pins, so that signal patterns on the inner layer can pass through.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は固定ディレーラインの入出
力ピンを表面実装対応したことによりディレーラインを
通る信号波形を改善できるという効果と共に固定ディレ
ーラインを実装するプリント配線板のパターンの収容性
を向上させるという効果がある。As explained above, the present invention has the effect of improving the signal waveform passing through the delay line by making the input/output pins of the fixed delay line compatible with surface mounting, and also improving the pattern accommodation of the printed wiring board on which the fixed delay line is mounted. It has the effect of causing

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す側面図である。 １・・・固定ディレーライン、２・・・固定ディレーラ
インのＧＮＤピン（スルーホール対応）、３．４・・・
固定ディレーラインの信号ピン（表面実装対応）、５・
・・プリント配線板、６・・・コネクタ（コンタクト７
．８．９の保持用）、７・・・ピンに対するコンタクト
（スルーホール実装）、８．９・・・ピンに対するコン
タクト（表面実装対応）、１０・・・はんだ。FIG. 1 is a side view showing an embodiment of the present invention. 1...Fixed delay line, 2...GND pin of fixed delay line (through hole compatible), 3.4...
Fixed delay line signal pin (surface mount compatible), 5.
...Printed wiring board, 6...Connector (contact 7
．． 8.9 for holding), 7... Contact for pin (through-hole mounting), 8.9... Contact for pin (compatible with surface mounting), 10... Solder.

Claims (1)

【特許請求の範囲】[Claims] 　それぞれ固有のディレー値を持ち、これを入れ替える
ことによってディレー値の調整を行なう固定ディレーラ
インの実装方法において、入出力ピンについては短いピ
ンを出すと共に前記固定ディレーラインを受けるプリン
ト配線板上のコネクタでは前記入出力ピンに対応したコ
ンタクトに対しては表面実装を使用したことを特徴とす
る固定ディレーラインの実装方法。In a fixed delay line implementation method in which each has a unique delay value and the delay value is adjusted by exchanging them, short pins are put out for the input/output pins, and the connector on the printed wiring board that receives the fixed delay line is A fixed delay line mounting method characterized in that surface mounting is used for contacts corresponding to the input/output pins.
JP19446990A 1990-07-23 1990-07-23 Method of packaging fixed delay line Pending JPH0481112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19446990A JPH0481112A (en) 1990-07-23 1990-07-23 Method of packaging fixed delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19446990A JPH0481112A (en) 1990-07-23 1990-07-23 Method of packaging fixed delay line

Publications (1)

Publication Number Publication Date
JPH0481112A true JPH0481112A (en) 1992-03-13

Family

ID=16325070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19446990A Pending JPH0481112A (en) 1990-07-23 1990-07-23 Method of packaging fixed delay line

Country Status (1)

Country Link
JP (1) JPH0481112A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019999A1 (en) * 2001-08-23 2003-03-06 Raytheon Company Low cost, large scale rf hybrid package for simple assembly onto mixed signal printed wiring boards

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019999A1 (en) * 2001-08-23 2003-03-06 Raytheon Company Low cost, large scale rf hybrid package for simple assembly onto mixed signal printed wiring boards

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