JPH047976A - Butterfly arithmetic circuit - Google Patents

Abstract

PURPOSE:To unnecessitate the code bit of a multiplying coefficient and to decrease one bit from the number of bits inputted to a multiplier by converting all the multiplying coefficients in a butterfly arithmetic circuit so that all the coefficients can be positive values. CONSTITUTION:In the range of 0<r<1/4, namely, in the angle range of 0-pi/4 radian, a multiplying coefficient -cos(rpi)+sin(rpi) is a negative value. While paying attention onto this fact, a code is inverted in advance to cos(rpi)-sin(rpi). In place of inverting the code of this multiplying coefficient, -1 is multiplied and added to the multiplied result, namely, subtraction is executed in the next addition processing. Thus, an arithmetic result to be finally obtained is same as that of the butterfly arithmetic circuit of Wang. Therefore, a code processing in multiplication is unnecessitated and the code bit is also unnecessitated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a butterfly calculation circuit for fast cosine transform (FCT) used in natural image compression processing and the like.

[Conventional technology]

As a calculation algorithm for one-dimensional fast cosine transform, C
hen, Wang X Makhou 1 and other methods have been proposed. - As an example, in Figures 2(a) and (b), C
hen's 8-point FCT and its inverse transform (IFCT) algorithm are shown. In the figure, black circles indicate addition. The white circles are terminals and do not perform any calculations. The value written next to each line is a multiplication coefficient, and indicates that the incoming data is multiplied by the multiplication coefficient. c.
(rπ) is an abbreviation for cos (rπ), S(γπ) is 5in
(γπ). Further, - is an abbreviation for -1, and represents that the sign of the data entering that line is inverted. When using this Chen's algorithm, 8
Point FCT (IFCT) can be processed at high speed with 16 multiplications and 26 additions and subtractions.

Furthermore, the butterfly arithmetic circuit shown in FIG. 3(a), which is the basis of cosine transformation, was modified as shown in FIG.
When transformed into a circuit like this (hereinafter referred to as "W a n g butterfly calculation circuit"), the circuit shown in the figure (al.
The previously mentioned 8-point FCT (
IFCT) can be realized with 13 multiplications and 29 additions/subtractions, and the calculation speed can be further increased by reducing the time-consuming multiplications. Note that the port in bl in FIG. 3(a) is a terminal and does not perform any calculations.

[Problem to be solved by the invention]

By modifying the butterfly arithmetic circuit, which is the basis of cosine transformation, like the Wang butterfly arithmetic circuit (in Figure 3), what used to require four multiplications and two additions/subtractions can be reduced to three multiplications. It only takes three additions and subtractions. The multiplication coefficient for these three times is, as is clear from Figure 3 (bl), ■ cos (rπ) + 5in (Tπ) ■ -cos
(γπ)+5in(γπ)■5in(γπ). Here, γ is 1/4.1/8.1/16
．． It is a value in the range of 0 to 172 such as 5/16, that is, in terms of angle value (γπ), it is a value in the range of 0 to π/2 [radian].

By the way, among the three multiplication coefficients mentioned above, the multiplication coefficient -
cos (rπ) +5in(γπ) is O<r<1/4
It becomes a negative value in the range of , that is, the angle value range of 0 to π/4 [radian]. Therefore, since the multiplication coefficient is a positive or negative signed value, in order to implement the circuit in Figure 3(b) in hardware, it is necessary to use a multiplier that has a signed arithmetic function for the multiplication coefficient. , and the circuit scale increases accordingly. Furthermore, since one pin is required for the sign pin, there is a problem in that the number of input bits for multiplication also increases accordingly.

The present invention was made to solve the above problems, and
It is an object of the present invention to provide a butterfly arithmetic circuit in which a multiplier can be constructed as simply as possible by setting all multiplication coefficients to positive values.

[Means to solve the problem]

In order to achieve the above object, the present invention uses a cosine function as a basis function for orthogonal transformation, and provides a high-speed cosine transformation in which a calculation result is obtained by three multiplications and three additions/subtractions for two data. In Wang's butterfly arithmetic circuit for , the sign of the multiplication coefficient whose coefficient value is negative in the angle range of 0 to π/4 [radian] is inverted in advance, and the sign of the next stage of the multiplication coefficient with the sign inverted is It replaces addition with subtraction.

[For production]

In the present invention, in the angular range of O to π/4 [radianco, the multiplication coefficient of the above-mentioned ■ - cos (Tπ) + 5 in (r
This method focuses on the fact that π) becomes a negative value, and the multiplication coefficient, which is originally a negative value, is converted into a positive value in advance and multiplication processing is performed, and in the next stage of addition processing, subtraction is performed instead of addition. This is how it was done. Since the subtraction process is equivalent to addition with the sign reversed, the final calculation result obtained from the butterfly calculation circuit is the same value as the conventional Wang butterfly calculation circuit shown in Figure 3 (bl), but the butterfly calculation Inside the circuit, all multiplication coefficients are processed as positive values.Therefore, there is no need for sign focusing on the multiplication coefficients, and there is no need for positive/negative sign processing on the input side of the multiplier.

〔Example〕

One embodiment of the invention is shown in FIG.

FIG. 1(a) shows a butterfly operation circuit when the value of T is 0 < r < 1/4 (0 to π/4 [radians] with an angle value of 7π), and FIG. 1(b) shows the The value of γ is 1/4≦γ
This is the configuration of the butterfly calculation circuit in the case of <1/2 (O to π74 [radians] in angle value Tπ).

In the present invention, as shown in FIG. 1(a), T is O<r<1
/4 range, that is, in the angular range from 0 to π/4 [radians], the multiplication coefficient of the above-mentioned ■ cos(rπ) + 5i
Focusing on the fact that n(rπ) is a negative value, the sign of the multiplication coefficient that is a negative value is reversed in advance and cos
(γπ)−sin(γπ). Then, instead of inverting the sign of this multiplication coefficient, the multiplication result is multiplied by -1 and added, that is, subtracted, in the next stage of addition processing.

When transformed in this way, the multiplication result of the sign-inverted multiplication coefficient will have the opposite sign to the original multiplication value, but in the next stage of addition processing, it will be multiplied by ~1 and added, that is, subtracted, so
The finally obtained calculation result is the Wang
The value is the same as that of the butterfly arithmetic circuit. therefore,
Sign processing in multiplication is not required, and the sign bit is also not required.

A range of 1/4≦r<1/2 other than the above, that is, π/4
~π/2 [In the radian 10 angle range, the multiplication factor of ■ -
cos (γπ) +5in(rπ) is a positive value.

Therefore, when the angle value is in this range,
), the conventional W a
ng remains the same as the butterfly arithmetic circuit (FIG. 3(b)).

〔Effect of the invention〕

As is clear from the above description, according to the present invention, all the multiplication coefficients in the butterfly calculation circuit are converted to positive values, so there is no need for sign bits for the multiplication coefficients. , the number of input bits of the multiplier can be reduced by one bit.

Moreover, since no positive or negative sign processing is required on the input side of the multiplier, the structure of the multiplier is simplified, and it is possible to improve the calculation speed and reduce the amount of hardware in high-speed cosine transformation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing Chen's 8-point FCT and 8-point IFCT algorithms, and FIG. 3 is a diagram showing W a n g's butterfly calculation circuit. Patent applicant Riko Co., Ltd. (bl 0kuγku1/4 fake factory [蓚FO) 1-Invention Color Yi Katsui 1 Figure 1 (b) Wang Mehakufrazu Conventional Figure 3

Claims (1)

[Claims] Wang's butterfly calculation circuit for high-speed cosine transformation uses a cosine function as a basis function for orthogonal transformation, and obtains the calculation result by three multiplications and three additions/subtractions for two data. The multiplication coefficient whose coefficient value is negative in the angular range of π/4 [radian] is sign-inverted in advance, and addition in the next stage of the sign-inverted multiplication coefficient is replaced with subtraction. Butterfly calculation circuit.