JPH0479330A - Method of forming laminated wiring - Google Patents
Method of forming laminated wiringInfo
- Publication number
- JPH0479330A JPH0479330A JP19530390A JP19530390A JPH0479330A JP H0479330 A JPH0479330 A JP H0479330A JP 19530390 A JP19530390 A JP 19530390A JP 19530390 A JP19530390 A JP 19530390A JP H0479330 A JPH0479330 A JP H0479330A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- silicon film
- tungsten silicide
- polycrystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract 6
- 230000008018 melting Effects 0.000 claims abstract 6
- 238000000151 deposition Methods 0.000 claims abstract 5
- 229910052751 metal Inorganic materials 0.000 claims abstract 4
- 239000002184 metal Substances 0.000 claims abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 10
- -1 silicide compound Chemical class 0.000 claims description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 29
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 9
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000005368 silicate glass Substances 0.000 abstract description 4
- UXBCHMIKTYBYTN-LQPTXBPRSA-N (3s,8s,9s,10r,13r,14s,17r)-3-[12-(3-iodophenyl)dodecoxy]-10,13-dimethyl-17-[(2r)-6-methylheptan-2-yl]-2,3,4,7,8,9,11,12,14,15,16,17-dodecahydro-1h-cyclopenta[a]phenanthrene Chemical compound O([C@@H]1CC2=CC[C@H]3[C@@H]4CC[C@@H]([C@]4(CC[C@@H]3[C@@]2(C)CC1)C)[C@H](C)CCCC(C)C)CCCCCCCCCCCCC1=CC=CC(I)=C1 UXBCHMIKTYBYTN-LQPTXBPRSA-N 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000005336 cracking Methods 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は積層配線の形成方法とくに、信頼性の高い積層
配線の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming a laminated wiring, and particularly to a method of forming a highly reliable laminated wiring.
従来の技術
半導体装置の配線材料として高融点金属のシリサイド化
合物が耐熱性、耐腐食性、微細加工などの面から広く使
用されるようになってきた。2. Description of the Related Art Silicide compounds of refractory metals have come to be widely used as wiring materials for semiconductor devices due to their heat resistance, corrosion resistance, microfabrication, and other aspects.
以下、従来の積層配線の製造方法を第４図を用いて説明
する。第４図（ａ）に示すように、段差を有する半導体
基板１上に熱フローできる薄いガラス膜として、ボロン
・フォスファ・シリケート・ガラス（ＢＰＳＧ）膜２を
例えば常圧ＣＶＤ法により４５００人堆積し、次に第４
図（ｂｌに示すようにＢＰＳＧ膜の熱フローを例えば窒
素雰囲気中で９００℃３０分行なう。その後多結晶シリ
コン膜３を１５００人例えば減圧ＣＶＤ法により堆積し
、さらにコールドウオール型の減圧ＣＶＤ法によりタン
グステンシリサイド膜４を２５００人堆積する。その後
、周知の写真食刻法により多結晶シリコン膜３とタング
ステンシリサイド膜４の二層よりなるポリサイド配線を
形成する。Hereinafter, a conventional method for manufacturing a laminated wiring will be explained with reference to FIG. As shown in FIG. 4(a), a boron phosphor silicate glass (BPSG) film 2 is deposited by 4,500 people by, for example, atmospheric pressure CVD as a thin glass film that allows heat to flow on a semiconductor substrate 1 having steps. , then the fourth
As shown in Figure (bl), heat flow of the BPSG film is carried out for 30 minutes at 900°C in a nitrogen atmosphere. Thereafter, a polycrystalline silicon film 3 is deposited by 1500 people, for example, by low pressure CVD method, and then by cold wall type low pressure CVD method. 2,500 layers of tungsten silicide film 4 are deposited. Thereafter, a polycide wiring consisting of two layers of polycrystalline silicon film 3 and tungsten silicide film 4 is formed by a well-known photolithography method.
発明が解決しようとする課題
上記したようにこのような従来技術の構成では、下地凹
凸のある層間絶縁膜上にシリサイド膜４を被着しポリサ
イド配線を形成するとシリサイド膜４の内部応力の為に
タングステンシリサイド膜にクラックが生じ、熱処理を
行なうと下層の多結晶シリコン膜３まで切断してしまい
断線になる。微細化が行なわれると、さらに内部応力が
集中し断線が発生しやすくなる。Problems to be Solved by the Invention As described above, in the configuration of the prior art, when a silicide film 4 is deposited on an interlayer insulating film with uneven underlying layers and a polycide wiring is formed, internal stress of the silicide film 4 causes Cracks occur in the tungsten silicide film, and when heat treatment is performed, the underlying polycrystalline silicon film 3 is also cut, resulting in disconnection. When miniaturization is performed, internal stress is further concentrated and wire breaks are more likely to occur.
本発明は以上述べた問題を解決し、信頼性の高いポリサ
イド配線の形成方法を提供するものである。The present invention solves the above-mentioned problems and provides a highly reliable method for forming polycide wiring.
課題を解決するための手段
本発明では、上記課題を解決するために、ポリサイド配
線を形成する際に多結晶シリコン膜とシリサイド膜の膜
厚比を適正化し、またシリサイド膜の組成比の適正化を
行なう。Means for Solving the Problems In the present invention, in order to solve the above problems, when forming polycide wiring, the film thickness ratio of the polycrystalline silicon film and the silicide film is optimized, and the composition ratio of the silicide film is optimized. Do this.
作用
本発明では、多結晶シリコン膜とシリサイド膜の膜厚比
を適正化し、シリサイド膜の組成比を適正化することに
よりシリサイド膜の膜はかれやポリサイド配線の断線を
防止でき高い信頼性をもつ積層配線を形成できる。Function: In the present invention, by optimizing the film thickness ratio of the polycrystalline silicon film and the silicide film, and by optimizing the composition ratio of the silicide film, the silicide film can be prevented from flaking and polycide interconnections can be prevented from breaking, resulting in high reliability. Laminated wiring can be formed.
実施例
本発明の第１の実施例を第１図、第２図を用いて詳細に
説明する。Embodiment A first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
１は凹凸を有する半導体基板又は半導体素子、２はボロ
ン・フォスファ・シリケート・ガラス、３は多結晶シリ
コン膜、４はタングステンシリサイド膜である。Reference numeral 1 designates a semiconductor substrate or semiconductor element having unevenness, 2 a boron phosphor silicate glass, 3 a polycrystalline silicon film, and 4 a tungsten silicide film.
第１図（ａ）において半導体基板１上に常圧ＣＶＤヲ用
イて熱フローできるガラス膜としてボロン・フォスファ
・シリケート・ガラス（以下Ｂ Ｐ Ｓ Ｇ）膜２を成
長する。ＢＰＳＧ膜２の堆積は、例えば常圧ＣＶＤ法な
どにより行ない、ＢＰＳＧ膜２の膜厚は４５００人を用
いた。In FIG. 1(a), a boron phosphor silicate glass (hereinafter referred to as BPSG) film 2 is grown on a semiconductor substrate 1 by atmospheric pressure CVD as a glass film capable of thermal flow. The BPSG film 2 was deposited by, for example, atmospheric pressure CVD, and the thickness of the BPSG film 2 was 4500.
次に第１図ｆｂ）に示すように、ＢＰＳＧ膜２を水蒸気
雰囲気中で熱処理を例えば９００℃３０分行ない、溶融
平坦化を行なう。次に多結晶シリコン膜３を約１５００
人例えば減圧ＣＶＤ法により堆積し、さらにタングステ
ンシリサイド膜４を例えば、シラン８００ｓｅｃｍ、六
弗化タングステン５ｓｅｃｍを使用したコールドウオー
ル型の減圧ＣＶＤ法により１５００人堆積する。その後
、周知の写真食刻法とドライエツチングにより、多結晶
シリコン膜３とタングステンシリサイド膜４０２層から
なるポリサイド配線を形成する。このとき、タングステ
ンシリサイド膜４にクラック５がポリサイド配線には生
じない。Next, as shown in FIG. 1 fb), the BPSG film 2 is heat-treated at, for example, 900° C. for 30 minutes in a steam atmosphere to melt and flatten it. Next, a polycrystalline silicon film 3 of about 1500
For example, a tungsten silicide film 4 is deposited by a cold wall type low pressure CVD method using, for example, 800 seconds of silane and 5 seconds of tungsten hexafluoride. Thereafter, a polycide wiring consisting of a polycrystalline silicon film 3 and a tungsten silicide film 402 is formed by well-known photolithography and dry etching. At this time, cracks 5 in the tungsten silicide film 4 do not occur in the polycide wiring.
次に第２図に上記実施例で形成したポリサイド配線の多
結晶シリコン膜３とタングステンシリサイド膜４の膜厚
比とポリサイド配線の断線率を示す。この結果、多結晶
シリコン膜３とタングステンシリサイド膜４の膜厚比が
、１．３以上でポリサイド配線の断線が発注する。本実
施例では多結晶シリコン膜３とタングステンシリサイド
膜４を共に１５００人とし断線は発生しない。またタン
グステンシリサイド膜４と多結晶シリコン膜３の膜厚比
を０．２以下にすると配線抵抗が増加するため膜厚比は
０．２以上１．３以下であることか適当であり、最適値
として多結晶シリコン膜３とタングステンシリサイド膜
４の膜厚比か１．０の時は応力による不良発生率が低く
さらに配線抵抗も低い。Next, FIG. 2 shows the film thickness ratio of the polycrystalline silicon film 3 and tungsten silicide film 4 of the polycide wiring formed in the above embodiment and the disconnection rate of the polycide wiring. As a result, when the film thickness ratio between the polycrystalline silicon film 3 and the tungsten silicide film 4 is 1.3 or more, the polycide wiring becomes disconnected. In this embodiment, both the polycrystalline silicon film 3 and the tungsten silicide film 4 have a thickness of 1,500, and no disconnection occurs. Furthermore, if the film thickness ratio of the tungsten silicide film 4 and the polycrystalline silicon film 3 is set to 0.2 or less, the wiring resistance will increase, so the film thickness ratio should be between 0.2 and 1.3, which is the optimum value. When the film thickness ratio between the polycrystalline silicon film 3 and the tungsten silicide film 4 is 1.0, the failure rate due to stress is low and the wiring resistance is also low.
さらに、第１図に示した構成で、従来問題となっていた
タングステンシリサイド膜４の内部応力によるタングス
テンシリサイド膜４中のクラックの発生を防止できる。Furthermore, the configuration shown in FIG. 1 can prevent the occurrence of cracks in the tungsten silicide film 4 due to internal stress in the tungsten silicide film 4, which has been a problem in the past.
次に第３図にタングステンシリサイド膜４のタングステ
ンとシリコンの組成比と断線率の関係を示す。この結果
タングステンとシリコンの組成比が２．５以上で断線が
発生しない。本実施例ではシランを８００ｓｃｃｍ六弗
化タングステン６ｓｅｃｍでタングステンシリサイドを
堆積し組成比を２．６としているので断線は発生しない
。また、組成比を３．０以上とするとタングステンンリ
サイド膜の比抵抗が増加し配線抵抗か増加するため、組
成比は２．５以上３．０以下か適している。Next, FIG. 3 shows the relationship between the composition ratio of tungsten and silicon in the tungsten silicide film 4 and the disconnection rate. As a result, when the composition ratio of tungsten and silicon is 2.5 or more, disconnection does not occur. In this embodiment, tungsten silicide is deposited using 800 sccm of silane and 6 seconds of tungsten hexafluoride, and the composition ratio is set to 2.6, so that no disconnection occurs. Further, if the composition ratio is set to 3.0 or more, the resistivity of the tungsten silicide film increases and the wiring resistance also increases, so a composition ratio of 2.5 or more and 3.0 or less is suitable.
以上のように本実施例によれば、
（１） ポリサイド配線のタングステンシリサイド膜
と多結晶シリコン膜の膜厚比を０．２以上１．３以下に
することによりタングステンシリサイド膜のクラックを
防止できポリサイド配線の断線を防止できる。As described above, according to this embodiment, (1) Cracks in the tungsten silicide film can be prevented by setting the film thickness ratio of the tungsten silicide film and the polycrystalline silicon film of the polycide wiring to 0.2 or more and 1.3 or less. Breakage of polycide wiring can be prevented.
（２） ポリサイド配線のタングステンシリサイド膜
のタングステンシリサイドとシリコンの組成比を２．５
以上３．０以下にすることによりタングステンシリサイ
ド膜のクラックを防止しポリサイド配線の断線を防止で
きる。(2) The composition ratio of tungsten silicide and silicon in the tungsten silicide film of polycide wiring is 2.5.
By setting the value to 3.0 or less, cracking of the tungsten silicide film and disconnection of the polycide wiring can be prevented.
また、本実施例では、シリサイド化合物としてタングス
テンシリサイドを用いたが、それ以外のＴｉ、Ｍｏなと
のケイ化物などでも同様な効果が期待できる。Further, in this example, tungsten silicide was used as the silicide compound, but similar effects can be expected with other silicides such as Ti and Mo.
発明の効果
本発明によってポリサイド配線のクラックを防止するこ
とで、断線を起こさない信頼性の高い配線を形成できる
。Effects of the Invention By preventing cracks in polycide wiring according to the present invention, highly reliable wiring that does not cause disconnection can be formed.
第１図は本発明の一実施例における積層配線の製造方法
を示す図、第２図はタングステンシリサイド膜と多結晶
シリコン膜の膜厚比と断線率を示す図、第３図はタング
ステンシリサイド膜の組成比と断線の関係を示す図、第
４図は従来例を説明するための図である。
１・・・・・・半導体基板、２・・・・・・ＢＰＳ’Ｇ
膜、３・・・・・・多結晶シリコン膜、４・・・・・・
タングステンシリサイド膜、５・・・・・・クラック。
代理人の氏名 弁理士 粟野重孝 はか１名第１図
第 ２
図
〃θＬ
第３ ｆ７１
！θ１
７ンクステンンリプＡトヒ夛奪を晶ンリコンｎ月貧ＡＩ
乙タ
ノじり文テン
シソゾイド８罠FIG. 1 is a diagram showing a method for manufacturing a laminated wiring in an embodiment of the present invention, FIG. 2 is a diagram showing the film thickness ratio and disconnection rate of a tungsten silicide film and a polycrystalline silicon film, and FIG. 3 is a diagram showing a tungsten silicide film and a disconnection rate. FIG. 4 is a diagram showing the relationship between the composition ratio and wire breakage, and is a diagram for explaining a conventional example. 1...Semiconductor substrate, 2...BPS'G
Film, 3... Polycrystalline silicon film, 4...
Tungsten silicide film, 5...Crack. Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 1 Figure 2〃θL 3rd f71! θ1 7nxtennlip A Tohi's hijacking and reconn n month poor AI
Otano Jiri Bun Tenshisozoid 8 Trap
Claims (2)
成した後、前記ガラス膜をマニールし熱フローする工程
と、前記熱フローしたガラス膜上に多結晶シリコン膜を
被着する工程と、前記多結晶シリコン膜上に高融点金属
のシリサイド化合物を被着する工程を備え、前記シリサ
イド化合物が、前記多結晶シリコン膜の膜厚に対し０．
２以上１．３以下の膜厚であることを特徴とする積層配
線の形成方法。(1) After forming a glass film on the main surface of a semiconductor substrate having a step, the step of manulating and heat-flowing the glass film, and the step of depositing a polycrystalline silicon film on the heat-flowed glass film. , comprising a step of depositing a silicide compound of a high melting point metal on the polycrystalline silicon film, the silicide compound having a thickness of 0.0.
A method for forming a laminated wiring, characterized in that the film thickness is 2 or more and 1.3 or less.
成した後、前記ガラス膜をマニールし熱フローする工程
と前記熱フローしたガラス膜上に多結晶シリコン膜を被
着する工程と、前記多結晶シリコン膜上に高融点金属の
シリサイド化合物を被着する工程を備え、前記シリサイ
ド化合物の高融点金属に対するシリコンの組成比が２．
５以上３．０以下であることを特徴とする積層配線の形
成方法。(2) After forming a glass film on the main surface of a semiconductor substrate having a step, a step of manulating and heat-flowing the glass film, and a step of depositing a polycrystalline silicon film on the heat-flowed glass film; a step of depositing a silicide compound of a high melting point metal on the polycrystalline silicon film, the silicide compound having a composition ratio of silicon to the high melting point metal of 2.
A method for forming a laminated wiring, characterized in that the ratio is 5 or more and 3.0 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19530390A JPH0479330A (en) | 1990-07-23 | 1990-07-23 | Method of forming laminated wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19530390A JPH0479330A (en) | 1990-07-23 | 1990-07-23 | Method of forming laminated wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0479330A true JPH0479330A (en) | 1992-03-12 |
Family
ID=16338913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19530390A Pending JPH0479330A (en) | 1990-07-23 | 1990-07-23 | Method of forming laminated wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0479330A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6970226B2 (en) | 2003-02-21 | 2005-11-29 | Au Optronics Corp. | Liquid crystal display having vacuum layer for isolating heat |
| US7832916B2 (en) | 2004-06-21 | 2010-11-16 | Idemitsu Kosan Co., Ltd. | Back chassis integrating reflector, back light and liquid crystal display |
| US8279375B2 (en) | 2007-04-16 | 2012-10-02 | Sharp Kabushiki Kaisha | Display apparatus, driving apparatus of display apparatus, and electronic device |
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|---|---|---|---|---|
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| JPS6347950A (en) * | 1986-08-18 | 1988-02-29 | Mitsubishi Electric Corp | Semiconductor device |
| JPS63133672A (en) * | 1986-11-26 | 1988-06-06 | Nec Corp | Semiconductor device |
| JPS63143841A (en) * | 1986-12-08 | 1988-06-16 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
-
1990
- 1990-07-23 JP JP19530390A patent/JPH0479330A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62281350A (en) * | 1986-05-29 | 1987-12-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS6347950A (en) * | 1986-08-18 | 1988-02-29 | Mitsubishi Electric Corp | Semiconductor device |
| JPS63133672A (en) * | 1986-11-26 | 1988-06-06 | Nec Corp | Semiconductor device |
| JPS63143841A (en) * | 1986-12-08 | 1988-06-16 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6970226B2 (en) | 2003-02-21 | 2005-11-29 | Au Optronics Corp. | Liquid crystal display having vacuum layer for isolating heat |
| US7832916B2 (en) | 2004-06-21 | 2010-11-16 | Idemitsu Kosan Co., Ltd. | Back chassis integrating reflector, back light and liquid crystal display |
| JP4726783B2 (en) * | 2004-06-21 | 2011-07-20 | 出光興産株式会社 | Back chassis integrated reflector, backlight device, and liquid crystal display device |
| US8279375B2 (en) | 2007-04-16 | 2012-10-02 | Sharp Kabushiki Kaisha | Display apparatus, driving apparatus of display apparatus, and electronic device |
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