JPH0478584U - - Google Patents

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Publication number
JPH0478584U
JPH0478584U JP12141490U JP12141490U JPH0478584U JP H0478584 U JPH0478584 U JP H0478584U JP 12141490 U JP12141490 U JP 12141490U JP 12141490 U JP12141490 U JP 12141490U JP H0478584 U JPH0478584 U JP H0478584U
Authority
JP
Japan
Prior art keywords
frequency
jamming
received
gate
diagram showing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12141490U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12141490U priority Critical patent/JPH0478584U/ja
Publication of JPH0478584U publication Critical patent/JPH0478584U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aはこの考案の一実施例を示す構成図、
第2図bはこの考案の一実施例における効果を示
す説明図、第2図はこの考案の他の実施例を示す
構成図、第3図はこの考案のさらに他の実施例を
示す構成図、第4図は従来の電波送受信装置を示
す構成図である。 図において1は受信アンテナ、2は周波数メモ
リ、3は送信アンテナ、4はメモリ・ゲート回路
、5は受信周波数検出回路、6は周波数ゲート判
定回路、7は受信パルス幅検出回路、8はパルス
幅ゲート判定回路、9は受信方位検出回路、10
は方位ゲート判定回路である。なお、図中、同一
符号は同一、又は相当部分を示す。
FIG. 1a is a configuration diagram showing an embodiment of this invention;
Fig. 2b is an explanatory diagram showing the effects of one embodiment of this invention, Fig. 2 is a block diagram showing another embodiment of this invention, and Fig. 3 is a block diagram showing still another embodiment of this invention. , FIG. 4 is a block diagram showing a conventional radio wave transmitting/receiving device. In the figure, 1 is a reception antenna, 2 is a frequency memory, 3 is a transmission antenna, 4 is a memory gate circuit, 5 is a reception frequency detection circuit, 6 is a frequency gate judgment circuit, 7 is a reception pulse width detection circuit, and 8 is a pulse width. gate determination circuit; 9 is a reception direction detection circuit; 10
is an orientation gate determination circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信した電波源信号のパルス波形を周波数メモ
リに記憶し妨害電波として送信する妨害方式にお
いて、指定周波数範囲の受信パルス信号のみを記
憶するために周波数ゲートを備えた電波送受信装
置。
A radio wave transmitting/receiving device equipped with a frequency gate to store only received pulse signals in a specified frequency range in a jamming method in which the pulse waveform of a received radio source signal is stored in a frequency memory and transmitted as a jamming wave.
JP12141490U 1990-11-19 1990-11-19 Pending JPH0478584U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12141490U JPH0478584U (en) 1990-11-19 1990-11-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12141490U JPH0478584U (en) 1990-11-19 1990-11-19

Publications (1)

Publication Number Publication Date
JPH0478584U true JPH0478584U (en) 1992-07-08

Family

ID=31869271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12141490U Pending JPH0478584U (en) 1990-11-19 1990-11-19

Country Status (1)

Country Link
JP (1) JPH0478584U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017520760A (en) * 2014-06-03 2017-07-27 レイセオン カンパニー Analog RF memory system
US10027026B2 (en) 2014-09-18 2018-07-17 Raytheon Company Programmable beamforming system including element-level analog channelizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017520760A (en) * 2014-06-03 2017-07-27 レイセオン カンパニー Analog RF memory system
US10027026B2 (en) 2014-09-18 2018-07-17 Raytheon Company Programmable beamforming system including element-level analog channelizer

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