JPH0477039A - Communication equipment - Google Patents

Communication equipment

Info

Publication number
JPH0477039A
JPH0477039A JP2188791A JP18879190A JPH0477039A JP H0477039 A JPH0477039 A JP H0477039A JP 2188791 A JP2188791 A JP 2188791A JP 18879190 A JP18879190 A JP 18879190A JP H0477039 A JPH0477039 A JP H0477039A
Authority
JP
Japan
Prior art keywords
transmitter
equipment
connection
program
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2188791A
Other languages
Japanese (ja)
Inventor
Takahiro Fudeyasu
筆保 隆弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP2188791A priority Critical patent/JPH0477039A/en
Publication of JPH0477039A publication Critical patent/JPH0477039A/en
Pending legal-status Critical Current

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  • Arrangements For Transmission Of Measured Signals (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To prevent malfunction by automatically detecting the connection state, inquiring a transmitter about an equipment name, reading a program corresponding to an equipment from a 2nd storage area and operating the equipment. CONSTITUTION:When a connection line 4 of a communication equipment 3 connects to an output signal line 2, an output current I of a transmitter 1 flows through a resistor 21 and a voltage across the resistor 21 is higher than a voltage of a reference power supply 22 and a comparator 23 outputs a connection detection signal. An interrupt input enters a CPU 12 by the signal and gives an inquiry command of an equipment name to the transmitter 1 at first and the equipment name sent from the transmitter 1 is received. Then a head address of a fixed part to the equipment name is set to an address designation register 13. Then the program specific to the equipment is read from an address designated by the address designation register 13 by the program memory 14 to execute the processing specific to the equipment.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、電磁流量計、温度変換器、圧力伝送器等の
各種伝送器の出力信号線に接続してデータ通信を行う通
信装置に関する。
Detailed Description of the Invention (a) Industrial Application Field This invention relates to a communication device that connects to the output signal line of various transmitters such as an electromagnetic flowmeter, temperature converter, and pressure transmitter to perform data communication. .

(ロ)従来の技術 従来、各種伝送器の出力信号線に通信装置を接続し、通
信装置から伝送器側に動作条件の設定、変更等を行うと
ともに伝送器から送られるデータの監視を行っている。
(B) Conventional technology Conventionally, a communication device is connected to the output signal line of various transmitters, and the communication device sets and changes the operating conditions on the transmitter side, as well as monitors the data sent from the transmitter. There is.

(ハ)発明が解決しようとする課題 伝送器が、たとえば電磁流量計、温度変換器、圧力伝送
器などと、接続したい相手の1云送器の種類が異なると
それぞれの伝送器で設定するデータの種類が異なるため
通信装置の中c二それぞれの伝送器毎に個別のプログラ
ムを用意する必要がある。
(c) Problems to be solved by the invention If the transmitter has a different type of transmitter, such as an electromagnetic flowmeter, temperature converter, or pressure transmitter, etc., the data to be set for each transmitter may be different. Because the types of transmitters are different, it is necessary to prepare separate programs for each of the two transmitters in the communication device.

この種の通信装置は携帯用であり、処理内容自体は比較
的簡単であることがら、CPUは通常8ビツトのものが
使用される。しかし、普通8ビ、トCPUはメモリ空間
が64にハイドしがないため、接続する機種の数が増や
せなかったり、ROMを差し替えねばならないという問
題があった。
Since this type of communication device is portable and the processing content itself is relatively simple, an 8-bit CPU is usually used. However, since 8-bit CPUs usually do not have a memory space of 64, there are problems in that the number of connected models cannot be increased or that the ROM must be replaced.

また、いったんある伝送器と接続して通信を開始した後
、他の伝送器に接続した場合、通信W置は、それ自体、
そのことを知らないため、そのまま動作を継続すると通
信装置は前に接続された伝送器りこ引き続き接続されて
いるものとして動作するために全く誤った操作を行って
しまい事故の原因となるおそれがあった。
Additionally, if you connect to one transmitter and start communication, and then connect it to another transmitter, the communication W device itself will
If you do not know this and continue to operate, the communication device will operate as if the previously connected transmitter is still connected, which may lead to completely incorrect operation and may cause an accident. Ta.

この発明は上記問題点に着目してなされたものであって
、メモリ空間の小さいCP[Jを持つ通信装置でも、多
くの伝送器に接続でき、また接続変更時に誤動作の起き
にくい通信装置を提供することを目的としている。
The present invention has been made in view of the above problems, and provides a communication device that can be connected to many transmitters even if the communication device has a small memory space and CP[J, and is less likely to malfunction when changing connections. It is intended to.

(ニ)課題を解決するための手段及び作用この発明の通
信装置は、各種伝送器の出力信号線に随意に接続して、
伝送器と通信を行うものにおいで、各種伝送器に共通の
プログラムを記憶する第1の記憶領域と、伝送器毎に固
有のプログラムを別々に記憶する第2の記憶領域と、前
記伝送器の出力信号への接続の有無を検知する接続検知
手段と、この接続検知手段による接続検知毎に接続され
た伝送器に対し機器名を問い合わせる指令を送信する手
段とを備え、伝送器から読み呂した機器名に応じて伝送
器ごと二こ異なるプログラムを第2の記憶領域から読み
出して動作させるようにしている。
(d) Means and operation for solving the problems The communication device of the present invention can be optionally connected to the output signal line of various transmitters.
A device that communicates with a transmitter includes a first storage area that stores programs common to various types of transmitters, a second storage area that separately stores programs specific to each transmitter, and The apparatus includes a connection detection means for detecting the presence or absence of connection to an output signal, and a means for transmitting a command to inquire about the device name to the connected transmitter each time the connection detection means detects the connection, and Two different programs are read from the second storage area and operated for each transmitter depending on the device name.

この通信装置では、伝送器の出力信号線に接続されると
、接続検知手段で自動的に接続状態を検知し、伝送器に
対して機器名の問い合わせを行い、第2の記憶領域から
そON B↓こ対応したプログラムを読み出し動作させ
る。これ二こよりCPL○メモリ空間を越えたメモリ量
のアクセスが可能となる。また、途中で接続伝送器の種
類を変更しても再接続時間に機器名を問い合わせ、その
機器名に対応したプログラムを動作させるので、誤動作
は防止できる。
In this communication device, when connected to the output signal line of the transmitter, the connection detection means automatically detects the connection state, queries the transmitter for the device name, and then outputs the ON from the second storage area. B↓ Read and operate the corresponding program. From these two points, it becomes possible to access a memory amount that exceeds the CPL○ memory space. Furthermore, even if the type of connected transmitter is changed during the process, the device name is queried at reconnection time and the program corresponding to the device name is run, so malfunctions can be prevented.

(ホ)実施例 以下、実施例により、この発明をさらに詳細に説明する
(E) Examples The present invention will be explained in more detail with reference to Examples below.

第1図は、この発明の一実施例を示す回路図である。同
図において、伝送器1の出力信号線2に通信装置3の接
続線4が接続されている。なお、5は負荷抵抗、6は電
源である。出力信号線2には[−4〜20mAの出力型
ン蚕が流れる。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, a connection line 4 of a communication device 3 is connected to an output signal line 2 of a transmitter 1. Note that 5 is a load resistance and 6 is a power supply. An output type current of -4 to 20 mA flows through the output signal line 2.

通信装置3は、接続検知部11.CPU12、アドレス
指定レジスタ13、プログラムメモリ14、キーボード
15、表示部16及びゲート17、]8を備えている。
The communication device 3 includes a connection detection unit 11. It includes a CPU 12, an address designation register 13, a program memory 14, a keyboard 15, a display section 16, and gates 17, ]8.

伝送器1の出力信号線2は接続線4、ゲート17.18
を介してCPU12に接続されている。接続検知部11
は伝送器1の出力型/lLrを流す抵抗21と、基準電
#22と、コンパレーク23とから構成されている。通
信装置3の接続線4が出力信号線2に接続されると抵抗
21に電流[が流れ、抵抗2Iの両端電圧が基準電源2
2の電圧よりも高くなり、コンパレータ23の出力が°
“ハイパとなり、通信装置3が出力信号線2に接続され
たことを意味する信号がCPU12の割り込み入力端子
に加えられる。
Output signal line 2 of transmitter 1 is connection line 4, gate 17.18
It is connected to the CPU 12 via. Connection detection unit 11
is composed of a resistor 21 through which the output type /lLr of the transmitter 1 flows, a reference voltage #22, and a comparator 23. When the connection line 4 of the communication device 3 is connected to the output signal line 2, a current flows through the resistor 21, and the voltage across the resistor 2I becomes the reference power supply 2.
2, the output of comparator 23 becomes
“The signal becomes hyper and a signal indicating that the communication device 3 is connected to the output signal line 2 is applied to the interrupt input terminal of the CPU 12.

通信装置3のメモリ構成を第2図に示している。The memory configuration of the communication device 3 is shown in FIG.

CPU12は内部に共通部分のプログラムを記憶する領
域と、伝送器の固有部分のプログラムを記憶する領域を
有するメモリを備えている。プログラムメモリ14は、
CPU12の内部メモリ記憶領域より大きい領域を持ち
、その最初の8イ)分ζこ各機種共通の処理に関するプ
ログラムが書き込まれ、その後に機器固有の部分のブロ
ク゛ラムが機器毎に書き込まれている。機器固有部分の
先頭アドレスは、それぞれアドレス1.2.3、・・・
と予め定められている。アドレス指定レジスタ13に機
器部分の先頭アドレスを書き込むことによってCPU。
The CPU 12 includes a memory having an area for storing programs for common parts and an area for storing programs for transmitter-specific parts. The program memory 14 is
It has an area larger than the internal memory storage area of the CPU 12, and the first 8 sections are written with programs related to processing common to each model, and after that, blocks of parts specific to each device are written for each device. The first address of the device-specific part is address 1, 2, 3, etc., respectively.
is predetermined. CPU by writing the start address of the device part into the address specification register 13.

12が自身のメモリ領域の機器固有部分をアクセスする
とプログラムメモリ14の対応機器のプログラム領域が
アクセスされるようになっている。
12 accesses the device-specific portion of its own memory area, the program area of the corresponding device in the program memory 14 is accessed.

たとえばアドレス指定レノスクI3乙こ機器1の固有領
域の先頭アドレスであるアドレス1を書き込んで、CP
UI 2が機器固有領域をアクセスすると、機器1固有
部分の内容が読み出され、機器2の固有領域の先頭アド
レスであるアドレス2を書き込めば、機器2の固有部分
の内容が読み出されて実行されることになる。
For example, write address 1, which is the start address of the unique area of address specification Renosk I3, and device 1, and
When UI 2 accesses the device specific area, the contents of the device 1 specific area are read out, and when address 2, which is the start address of the device 2 specific area, is written, the contents of the device 2 specific area are read and executed. will be done.

第3図にCPUI 2とアドレス指定レジスタ】3とプ
ログラムメモリ14の接続構成を示している。CPU1
2が共通部分をアクセスするとプロダラムメモリ14の
共通部分がそのままCPUI2へ送られるが、固有部分
をアクセスすると、アドレス指定レジスタ13に書き込
まれた先頭アト−レスの値によってプログラムメモリ1
4上の対応した部分がCPU12のデータバスへ送られ
る。
FIG. 3 shows a connection configuration between the CPU I 2, the address designating register 3, and the program memory 14. CPU1
2 accesses the common part, the common part of the program memory 14 is sent as is to the CPU 2, but when accessing the unique part, the program memory 1
The corresponding portion on 4 is sent to the data bus of CPU 12.

以上のように構成される実施例装置において、通信装置
3が伝送器1の出力信号線2に接続されていない状態で
は抵抗21に電流rが流れないので、コンパレータ23
は“′O°゛出力であり、つまり接続検知信号を出力せ
ず、したがってCPUI2は割込動作を実行しない。
In the embodiment device configured as described above, when the communication device 3 is not connected to the output signal line 2 of the transmitter 1, the current r does not flow through the resistor 21, so the comparator 23
is a "'O°" output, that is, it does not output a connection detection signal, and therefore the CPU 2 does not execute an interrupt operation.

通信装置3の接続線4が出力信号線2に接続されると、
伝送器1の出力電流■が抵抗21を流れ、そのため抵抗
21の両端電圧は、基準電源22の電圧よりも大となり
、コンパレータ23は信号“1°゛、つまり接続検知信
号を出力する。この信号によりCPUI 2には割り込
み入力が入り、第4図のフロー図に示すように、先ず伝
送器1に対し機器名を問い合わせ指令を発しくステップ
5T1)、伝送器1から送られて来る機器名を受信する
(ステ、ブ5T2)。そして、機器名乙こ対する固有部
分の先頭アドレスをアドレス指定レジスタ13にセット
する(ステップ5T3)。次乙こ、プログラムメモリ1
4よりアドレス指定レジスタ13で指定されるアドレス
よりMAL固有のプログラムを読み出し、機器固有の処
理を実行する(ステップ5T4)。なお、第4図に示し
た割り込み処理は、通信装置3の接続線4が接続される
ことにより実行される。例えば、伝送器1の出力信号線
2より接続線4を外して、再度接続した場合は、その伝
送器の機器名を問い合わせ、その機器名に対応した固有
の処理を再度実行する。したがって機器名が相違する誤
動作を生しることはない。接続線4をある機器から、他
の種類の機器↓こ接続した場合でも、必ず機器名を問い
合わせ、固有部分はその機器名に対応した内容を読み出
して実行するので、やはり誤動作することはない。
When the connection line 4 of the communication device 3 is connected to the output signal line 2,
The output current ■ of the transmitter 1 flows through the resistor 21, so the voltage across the resistor 21 becomes higher than the voltage of the reference power supply 22, and the comparator 23 outputs the signal "1°", that is, the connection detection signal.This signal As a result, an interrupt input is input to the CPU 2, and as shown in the flowchart of FIG. Receive it (step 5T2).Then, set the start address of the unique part for the device name in the address specification register 13 (step 5T3).Next, program memory 1
4, the MAL-specific program is read from the address specified by the address designation register 13, and device-specific processing is executed (step 5T4). Note that the interrupt processing shown in FIG. 4 is executed when the connection line 4 of the communication device 3 is connected. For example, if the connection line 4 is disconnected from the output signal line 2 of the transmitter 1 and then reconnected, the device name of the transmitter is queried and the specific processing corresponding to the device name is executed again. Therefore, malfunctions due to different device names will not occur. Even if the connection line 4 is connected from one device to another type of device, the device name is always queried and the unique part reads and executes the content corresponding to the device name, so malfunctions will not occur.

(へ)発明の効果 この発明によれば、各種伝送器に共通のプログラムを記
憶する第1の記憶領域と、伝送器毎に固有のプログラム
を別々に記憶する第2の記憶領域と、前記伝送器の8力
信号への接続の有無を検知する接+lE検知手段と、こ
の接続検知信号二こよる接続検知毎に接続された伝送器
に対′−R器名を問い合わせる指令を送信する手段とを
備え、伝送器から読み出した機器名に応じて伝送器ごと
に異なるプログラムを第2の記憶領域から読み出して動
作させるものであるから、メモリ領域の小さいCPUで
大きいメモリ領域を利用することができ、単一の通信装
置でプログラムメモリの交換などを行うこと無く各種の
伝送器に接続することが可能となる。また伝送器への接
続を常時監視し一旦接続が切り離され、再度接続された
場合には、機器問い合わせを行って対応機種のプログラ
ムに切り替えた後動作を行うため、従来のように通信装
置をその都度リセットする必要がなく、接続変更時に誤
動作の心配がない。
(f) Effects of the Invention According to the present invention, the first storage area stores a program common to various transmitters, the second storage area separately stores a program specific to each transmitter, and the connection detection means for detecting whether or not the device is connected to the 8-power signal; and means for transmitting a command to the connected transmitter to inquire about the name of the pair'-R device each time a connection is detected based on the connection detection signal. A program that is different for each transmitter is read out from the second storage area and operated according to the device name read from the transmitter, so a large memory area can be used by a CPU with a small memory area. , it becomes possible to connect various transmitters with a single communication device without replacing the program memory. In addition, the connection to the transmitter is constantly monitored, and if the connection is disconnected and then reconnected, the device is inquired and the program is switched to the compatible model before operation is performed. There is no need to reset each time, and there is no need to worry about malfunctions when changing connections.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例を示す通信装置のブロッ
ク図、第2図は、通信装置のメモリ構成を示す図、第3
図は、回通1:乞置のCPUとプログラムメモリ、アド
レス指定レー7:スフの接続を示すブロック図、第4図
は、同通信装置のhすり込み処理を示すフロー図である
。 1:伝送器、     2・出力信月綿、3:通信装置
、    11:接続検知部、12:CPU、    
13ニブログラムメモリ。 特許出願人      株弐会社島律製作所代理人  
弁理士   中 村 茂 信第 図 第 図
FIG. 1 is a block diagram of a communication device showing an embodiment of the present invention, FIG. 2 is a diagram showing a memory configuration of the communication device, and FIG.
The figure is a block diagram showing the connections between the communication device 1: the CPU, the program memory, and the address designation system 7. FIG. 4 is a flow diagram showing the h slipping process of the communication device. 1: Transmitter, 2. Output wire, 3: Communication device, 11: Connection detection unit, 12: CPU,
13 Niprogram memory. Patent applicant Shima Ritsu Seisakusho Co., Ltd. Agent
Patent Attorney Shigeru Nakamura

Claims (1)

【特許請求の範囲】[Claims] (1)各種伝送器の出力信号線に随意に接続して、伝送
器と通信を行う通信装置において、 各種伝送器に共通のプログラムを記憶する第1の記憶領
域と、伝送器毎に固有のプログラムを別々に記憶する第
2の記憶領域と、前記伝送器の出力信号への接続の有無
を検知する接続検知手段と、この接続検知手段による接
続検知毎に接続された伝送器に対し機器名を問い合わせ
る指令を送信する手段とを備え、伝送器から読み出した
機器名に応じて伝送器ごとに異なるプログラムを第2の
記憶領域から読み出して動作させることにより、多種類
の伝送器に接続可能とした通信装置。
(1) In a communication device that is optionally connected to the output signal line of various transmitters and communicates with the transmitter, there is a first storage area that stores a common program for various transmitters, and a first storage area that stores a program common to each transmitter. a second storage area for separately storing programs; a connection detection means for detecting the presence or absence of connection to the output signal of the transmitter; and a device name for the connected transmitter each time the connection detection means detects a connection. By reading a different program for each transmitter from the second storage area and operating it according to the device name read from the transmitter, it is possible to connect to many types of transmitters. communication equipment.
JP2188791A 1990-07-16 1990-07-16 Communication equipment Pending JPH0477039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2188791A JPH0477039A (en) 1990-07-16 1990-07-16 Communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2188791A JPH0477039A (en) 1990-07-16 1990-07-16 Communication equipment

Publications (1)

Publication Number Publication Date
JPH0477039A true JPH0477039A (en) 1992-03-11

Family

ID=16229861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2188791A Pending JPH0477039A (en) 1990-07-16 1990-07-16 Communication equipment

Country Status (1)

Country Link
JP (1) JPH0477039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040049A (en) * 2008-08-06 2010-02-18 Robert Bosch Gmbh Device and method for detecting amount measured

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040049A (en) * 2008-08-06 2010-02-18 Robert Bosch Gmbh Device and method for detecting amount measured

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