JPH0474674B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention generally relates to a multi-channel signal measuring device,
In particular, it relates to an oscilloscope suitable for measuring logic signals.

[Conventional technology]

Waveform measurement devices are broadly divided into two types: one is a regular oscilloscope, and the other is a logic (timing) analyzer.
It is. The former is a general-purpose waveform measurement device that displays input analog signals in real time. Although many efforts have been made to increase the number of channels, the number of channels is severely limited. The latter was developed to measure more than 100 multichannel logical (binary) signals temporally related to each other. This is done by using voltage comparison means.
It is distinctive in that the input signal is converted into a high or low (binary) signal before being stored in a semiconductor or other memory.

A disadvantage of logic analyzers is that it is impossible or difficult to measure noise below the threshold level as well as actual waveforms such as overshields, ringing, and rise times; Even if there is a difference, it will be reproduced as a different signal depending on the sampling clock frequency and threshold level, misleading the operator. Therefore, especially when designing high-speed logic circuits, it is not possible to perform detailed circuit analysis using only the display obtained from a logic analyzer, and an analog signal display such as an oscilloscope is sometimes required. However, there is no conventional oscilloscope that triggers and displays input signals in accordance with a predetermined level relationship of a plurality of input signals, like a logic analyzer.

[Problem to be solved by the invention]

Accordingly, it is an object of the present invention to provide a new waveform measurement device that combines the advantages and features of both a real-time oscilloscope and a logic analyzer.

Another object of the invention is to display in real time a plurality of input signals and/or selected Blue algebraic signals of these input signals.

It is a further object of the present invention to provide a real-time multi-channel oscilloscope that can trigger a time base based on various combinations of input signals.

Another object of the present invention is to provide a multi-channel signal measuring device that is optimal for repairing faults and designing digital circuits.

[Means and actions to solve the problem]

The multi-channel signal measuring device of the present invention observes the waveforms of multiple digital input signals as they are without converting them into high and low binary signals, and further converts them into binary signals using a comparator and converts them into binary signals using a Boolean logic circuit. A Boolean algebraic output was obtained and displayed simultaneously with the digital input signal using a multiplexer, which is a parallel to serial converter. This makes it possible to observe the correlation between a plurality of digital input signals and their binary Boolean output signals.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a simplified block diagram illustrating the principles of the invention. A plurality of input signals under test are coupled to respective input circuits 12a, . . . , 12n via input connectors 10a, . The input circuit includes a switchable attenuator (or multistage attenuator), a buffer amplifier, and the like. Input circuits 12a-1
2n output analog signal is multiplexer
The signals are supplied to the MUX 14 via delay circuits 30a...30n. The output signal selected by MUX 14, after the necessary amplification by vertical output amplifier 16, is used to drive the vertical deflection means of cathode ray tube CRT 18.

The output signals of the input circuits 12a-12n are also coupled to comparison means 20 having a plurality of voltage comparators, and these output signals corresponding to the input signals applied to the input terminals 10a-10n are coupled to a threshold level generator 22. are compared to their respective corresponding threshold levels. These threshold levels may be fixed at predetermined logic levels (eg ECL, TTL, etc.) or may be controllable by analog or digital means. The output of comparison means 20 is provided to MUX 26 and Boolean logic circuit 24. The Boolean logic circuit 24 includes, for example, AQD, OR, NAND, and
It generates the desired Boolean output signals, including the NOR output. The Boolean algebra output of logic circuit 24 is provided to both MUX 14 and 26.
MUX 26 selects a positive-going or negative-going output from comparator means 20 or Boolean logic circuit 24 under control of a trigger control signal. MUX
The output of 26 is used to drive a trigger and sweep circuit 28 which generates a sweep slope signal that is applied to the horizontal polarization means of CRT 18.

The MUX 14 operates under the control of a vertical control signal applied thereto such that any of the input signals is time-divisionally selected into an intermittent (CHOP) mode or an alternating (ALT) mode. CHOP mode is used to select input signals one after the other at a constant frequency (eg 1MHz) regardless of the timebase sweep rate. On the other hand, ALT mode is used to select input signals sequentially from sweep to sweep. The former mode is generally used at low sweep speeds, while the latter mode is used at higher sweep speeds. Delay lines 30a-30n compensate for time differences between each channel and signal delays caused by comparator 20 and Boolean logic circuit 24, thereby achieving highly accurate timing measurements of input signals and Boolean outputs. do.

The operation of the multi-channel signal measuring device shown in Fig. 1 is as follows:
This will be explained with reference to FIG. 2, which shows signal waveforms from various circuits. Waveforms A and B are input signals derived from input circuits 12a and 12n. The waveforms A and B are compared with respective threshold levels V _{ref 1} and V _{ref 2} by the comparison means 20, and the comparison means 20 obtains comparison output binary signals A' and B'. However, for simplicity, the signal delay caused by the comparison means 20 will be ignored. Waveforms (A′・B′) and (A′+
B′) is the AND and
Represents the OR output signal. Again, the logic circuit 24
The propagation delay of is ignored.

Trigger and sweep circuit 28 generates a sweep (ramp) signal that is synchronized with the selected trigger output signal from MUX 26 . AND output signal (A′・
If B') is selected as the trigger signal, the sweep signal is triggered at the leading edge of each pulse of the AND signal waveform (A', B'). However, if the sweep rate is sufficiently slow compared to the sweep and pause periods, the sweep signal is triggered on the leading edge of every Nth pulse (N being a positive integer greater than 1) after the end of the pause period. The sweep signal can also be set to either select a negative trigger slope or
By using the output signal from the NAND gate as the pulse, it can also be activated at the trailing edge of the pulse. Of course, the Boolean logic circuit 24 and MUX
26, the output waveforms A′,
It is also possible to trigger the sweep generator with other signals including B' and (A'+B').

On the other hand, the deflection signal to be supplied to the vertical deflection means of the CRT 18 can also be selected by a vertical control signal applied to the vertical channel MUX 14. That is, one or any combination of vertical signals from input circuits 12a-12n and Boolean logic circuits.
It can be displayed on CRT18. Separate or simultaneous display of an input signal and its Boolean output provides measurement convenience to operators in a variety of applications. For example, the above input signals can be AND, OR,
When applied to NAND or other gates, it is possible to simulate the situation where these gates operate at different threshold level settings. Therefore, the operator does not need to actually configure these logic circuits. Another application is to test the operation of any logic circuit for fault finding/repair or other purposes. The inputs and outputs of the logic circuit are coupled to input connectors 10a-10n, and the input signals are also sent to the Boolean logic circuit 24. Boolean logic circuit 24 is then selected to perform the logic operation desired for the logic circuit in question. Comparing the output of the logic circuit with the output of the Boolean logic circuit 24 helps the operator make necessary decisions.

FIG. 3 is a detailed block diagram showing a specific example of the present invention. Since this example has parts in common with those in FIG. 1, these parts are given the same or similar reference numerals, and only the differences will be explained below.

DC level (or position) control means 15a...,
The amplifiers 13a, . . . , 13n having 15n are
Performs the necessary signal amplification or attenuation coupled to input circuits 12a, . . . 12n, respectively. The DC level is controlled manually or automatically to sequentially position each waveform at a different vertical position so that multiple signal waveforms can be distinguished. The outputs of the amplifiers 13a to 13n are
The first channel switching circuit 14a causes the second channel switching circuit 14b to
multiplexed before being applied to the signal channels, so that only one delay circuit 30 is required for multiple signal channels. Both switching circuits 14a and 14b are controlled by a controller 17, which may include a microprocessor. The output of the switching circuit 14b is
The vertical amplifier 16 of FIG.

Digital data is sent from a microprocessor or the like to a threshold DAC (digital-to-analog converter) 22', which functions as the threshold generator 22 in FIG.
The voltage is supplied to a DVM (digital voltmeter) 23 that digitally measures the level. Also, DVM23
receives the attenuation information (ATT) and switches the measurement to match the selected attenuation factor of the attenuator in the input circuit 12.

The output of the comparator is connected to the Boolean logic circuit 24 and the edge
A trigger circuit 32 is applied to generate a trigger pulse when a selected logic condition is met or upon each conversion at the comparator output, respectively. Filter circuit 38 may be of conventional design and smoothes the signal to eliminate noise. “A then B” circuit 4
0 is used to generate a trigger output pulse when logic condition A is followed by B. Conditions for A and B can be programmed by the operator.

External trigger terminal 34 is coupled to an external input circuit or buffer circuit 36 and is used to receive external trigger pulses. Such an external trigger pulse is applied to the edge trigger circuit 32 and also to the switching circuit 26 along with the output of the "A the B" circuit 40. Switching circuit 26
supplies its output to the trigger/sweep circuit 28 of FIG. 1 and also to the switching circuit 14b via the trigger/view circuit.

The operation of the apparatus shown in FIG. 3 is generally the same as that shown in FIG. 1, with the addition of functions such as displaying external trigger pulses applied to external trigger terminal 34. Filter circuit 38 and "A the B" circuit 4
0 means pause if not needed. When the number of vertical channels is n, the channel switching circuit 14a selects each channel every n switching pulses, and the channel switching circuit 14b selects each channel (n+1).
Operates to select each switching pulse,
All signals are displayed for equal minute time.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a plurality of digital input signals can be
Unlike an analyzer, the threshold level is not converted into a high/low binary signal, but it is displayed as an analog signal for observation, so signal characteristics, such as the absolute values of high and low levels, waveform ringing, overshoot, and rise and fall times, can be observed. , noise such as spikes, and time differences between multiple signals can be investigated in detail. In addition, the comparison output of each digital input signal compared with a predetermined threshold level or its Boolean algebraic output (AND, OR, NOR, etc.) can be used to start the sweep circuit of the waveform display means, so the part of the signal you want to observe can be used. Easy to choose. Furthermore, since not only the multiple digital input signals themselves but also their selected Boolean output signals can be displayed simultaneously, there is no need to actually assemble various logic circuits, and it is also possible to compare the outputs of existing logic circuits. Boolean algebraic signals can be easily obtained. Therefore, it can be used to design digital circuits, find faults, and repair them with great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a simplified block diagram showing the principle of the present invention.
FIG. 2 is a waveform diagram showing the operation of the main blocks in FIG. 1, and FIG. 3 is a detailed block diagram showing a specific example of the present invention. 12a-12n...input circuit, 20...comparator, 24...Boolean logic circuit, 14...multiplexer.

Claims (1)

[Claims] 1. At least one of three or more input signals is selected by a multiplexer and applied to the vertical axis, and all or part of the plurality of input signals is compared with a variable threshold voltage by a comparator. In a multi-channel signal measuring device that displays the selected input signal as an analog signal waveform by applying a sweep signal triggered by the logic signal obtained from the comparator to the horizontal axis, AND,
A Boolean logic circuit is provided to obtain outputs of various logic operations such as OR, NOR, etc., and the output of the Boolean logic circuit is used to start the sweep signal and is applied to the vertical axis via the multiplexer to generate the selected input signal. and a multi-channel signal measuring device that is capable of simultaneously displaying the outputs of the Boolean logic circuit.