JPH0474243A - On-line diagnostic system for multiplex memory device - Google Patents

Abstract

PURPOSE:To enable a CPU to perform an on-line diagnosis of a multiplex memory device by giving an access to a memory unit separated from a system through a memory control means as long as a diagnostic task is shown. CONSTITUTION:A multiplex memory diagnostic program 41 is started and a test mode flag 22 is turned on. Thus an access is given only to an on-line memory unit 12 at a machine word instruction level. If an error is generated by an access given to a multiplex memory device 10 with the flag 22 kept turned on, this information is given to a CPU 20 in the same way as an error that is generated in a normal access. The CPU 20 carries out an error interruption processing routine under the control of an OS 40 in order to check the state of the flag 22. Thus it is possible to decide whether an error is generated or not at an access of the device 10 carried out based on the program 41. Therefore an error interruption processing routine can be branched into an error processing routine included in the program 41. Thus the CPU 20 can perform a proper treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) This invention relates to an online diagnosis method for multiplexed memory devices in a computer system.

(Prior Art) Memory devices such as a main memory device and a shared memory device that can be shared by multiple CPUs are generally multiplexed in order to improve their reliability. Furthermore, due to the characteristics of these memory devices, the CPU accesses them at the machine language instruction level, and write accesses from the CPU are performed on each memory unit that makes up the multiplexed memory device, so that each memory unit stores the same data. written.

On the other hand, read access from the CPU is performed only on one specific unit called a mask unit. If a defective unit occurs, that unit is automatically disconnected from the system and another normal unit is automatically used thereafter. Therefore, a CPU using this type of memory device does not need to be aware that the memory device is multiplexed.

Now, while the system is running, it may be necessary to diagnose a memory unit that has been disconnected from the system due to the occurrence of a failure, or to perform a test before installing a new unit after replacement. However, in the past, the fact that a memory device is multiplexed with several memory units was transparent to the CPU as described above, so a faulty memory unit could be diagnosed by the CPU or online. , or it was impossible to test (only access to normal memory units is possible).

For this reason, in the past, it was necessary to add a special device to the multiplexed memory device to perform a unit test, and to perform the unit test off-line.

(Problem to be Solved by the Invention) As described above, conventionally, each memory unit of a multiplexed memory device can be recognized from the CPU, and therefore the memory unit that has been disconnected from the system due to a failure can be connected online. It was impossible to conduct any tests during the test. For this reason, not only is it necessary to add a special diagnostic device to the multiplexed memory device, but it is also impossible to perform diagnosis and testing without passing through the CPU, so it is only possible to diagnose the multiplexed memory device alone. First, there was a problem in that the diagnostic level was low, making it difficult to integrate the system into the system after replacing the memory unit.

This invention was made in view of the above circumstances, and its purpose is to diagnose and test multiplexed memory devices, without affecting online operations while the system is online, and without requiring special diagnostic equipment. An object of the present invention is to provide an online diagnosis method for a multiplexed memory device that can be performed without using a CPU.

[Configuration of the Invention (Means for Solving the Problems) This invention provides a computer system equipped with a multiplexed memory device having a plurality of memory units, in which a task being executed is transmitted to a CPU accessing the multiplexed memory device. A test mode flag indicating whether the task is a diagnostic task or a general task (non-diagnostic task) is provided, a control register is provided for each task, and the multiplexed memory device is provided with a control register that can be controlled for each task.
A memory control means is provided that controls access to the memory unit in the multiplexed memory device according to the state of the test mode flag in the control register when there is an access request from the CPU by executing an instruction, and diagnosis is performed using the test mode flag. When a task is indicated, by configuring the memory unit that is disconnected from the system among the plurality of memory units mentioned above to be accessed, the disconnected memory unit can be accessed from the CPU under the system online condition. It is characterized by being able to be diagnosed.

(Function) According to the above configuration, when a diagnostic task for diagnosing and testing a multiplexed memory device is executed, the test mode flag in the control register is turned on in response to a request from the diagnostic task. This indicates that the task is being executed or is a diagnostic task and is therefore in test mode for diagnosing and testing the multiplexed memory device.

Now, when the multiplexed memory device is accessed from the CPU in response to a request from the diagnostic task, the memory control means in the multiplexed memory device controls access to the memory unit according to the state of the test mode flag, and turns on the flag as described above. In the case of (test mode), write or read access is performed only to memory units (offline units) that have been disconnected from the system due to occurrence of a failure or the like. As a result, it becomes possible to diagnose and test a memory unit that has been disconnected from the system while the system is online, without using the CPU.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a computer system to which the present invention is applied. In the figure, IO is a multiplexed memory device. The multiplexed memory device IO includes, for example, two memory units 11.12 and a memory controller 1 that controls access to the memory units 11.12.
It has 3. In addition to the well-known control function of disconnecting the failed unit from the system when a failure occurs in any of the memory units 11 and 12, the memory control unit 13 also has test mode access based on the state of a test mode flag 22, which will be described later. It has a new control function that determines whether or not the memory unit is accessed.

20 is a CPU that executes machine language instructions and accesses the multiplexed memory device IO at the machine language instruction level; 21 is a CPU 2;
This is a control register that is provided in 0 and can be controlled for each task. The control register 21 indicates whether the task being executed is a diagnostic task for diagnosing and testing the multiplexed memory device 10 or a general task (non-diagnostic task), that is, whether the access to the multiplexed memory device IO is in test mode. (hereinafter referred to as the test mode flag)
Contains 22.

A bus 30 interconnects the multiplexed memory device 10, the CPU 20, etc., and is used for memory access addresses, data transfer, and the like. This bus 30 is connected to the control register 2
The state of the test mode flag 22 in memory controller 1
It is also used to notify 3.

40 is an operating system (hereinafter referred to as O8) that controls the execution of tasks, and is in charge of saving and restoring the contents of the control register 21 every time a task is dispatched. 41 is a multiplexed memory diagnostic program that provides diagnostic tasks for diagnosing multiplexed memory devices IO under the management of 0840. This multiplexed memory diagnostic program 4
1 includes the test mode flag 22 in the control register 21.
Test mode access ON instruction (hereinafter referred to as ONTM instruction) 4, which is a machine language instruction for turning on the test mode (setting the test mode access state).
2, and a test mode access OFF instruction (hereinafter referred to as OFFTM instruction) 4, which is a machine language instruction for turning off the test mode flag 22 and canceling the test mode.
3 is set.

FIG. 2 is a flowchart for explaining the processing procedure of the multiplexed memory diagnostic program 41 shown in FIG.

FIG. 3 is a flowchart for explaining the operation of the memory control section 13 shown in FIG.

Next, the operation of the configuration shown in FIG. 1 will be explained when diagnosing the memory unit 12 of the multiplexed memory device 10 when a failure occurs in the memory unit 12 and the memory unit 12 is disconnected from the system. will be described with reference to the flowcharts of FIGS. 2 and 3, taking the example of FIG.

First, it is assumed that the multiplexed memory diagnostic program 41 is started under the control of 0840. This allows CPU20
starts diagnostic processing according to the multiplexed memory diagnostic program 41 as shown in the flowchart of FIG.

That is, the CPU 20 first executes the ONTM instruction 42, and
Turn on (set) the test mode flag 22 in the control register 21 provided in the PU 20 (step S in FIG. 2).
1). This will result in a test mode access state.
A diagnostic process targeting the multiplexed memory device 10 is started.

Next, the CPU 20 uses normal machine language instructions to diagnose the multiplexed memory device 10 according to the multiplexed memory diagnostic program 41.
(Step S2 in FIG. 2). During this access, the CPU 20 converts the state of the test mode flag 22 of the control register 21 into memory access information (
address, data, etc.) is sent to the memory control unit 13 in the multiplexed memory device 10 via the lotus 30.

When the memory control unit 13 receives the memory access information from the CPU 20, it checks the state of the test mode flag 22 as shown in FIG. 3 (step 511 in FIG. 3). If the test mode flag 22 is off (that is, not in the test mode access state), the memory control unit 13 performs normal access control operations (step 512 in FIG. 3).
. That is, the memory control part I3 performs read access to only the mask unit of the memory units 11 and 12 in the case of a read request, and performs write access to both memory units 11 and 12 in the case of a write request. control. On the other hand, if the test mode flag 22 is on (that is, if the test mode is accessed)
, the memory control unit 13 has write access only to the offline unit of the memory units 11 and 12,
Control is performed to perform read access (step 813 in FIG. 3).

In this embodiment, the memory unit 12 is disconnected from the system and placed offline. Therefore, when the multiplexed memory diagnostic program 41 is started and the test mode flag 22 is turned on as described above, only this offline memory unit 12 is accessed at the machine language instruction level. Become. This test mode flag 22 is on! If an error occurs when accessing the multiplexed memory device 10 (the off-line memory unit 12 therein) in F3 (that is, the test mode access state), the error occurs in the normal memory (when the test mode flag 22 is off). The CPU 20 is notified in the same way as when an error occurs in access (for example, in the form of an error interrupt).

When this error notification (error interrupt) is received, the CPU 20
Then, an error interrupt processing routine is executed under the control of 0840. In this error interrupt processing routine, the multiplexed memory diagnostic program 41 checks the state of the test mode flag 22 of the control register 21.
It can be determined whether the error occurred when accessing the multiplexed memory according to the following. Therefore, when it is determined that an error occurs when accessing the multiplexed memory according to the multiplexed memory diagnostic program 41, the error interrupt processing routine can branch to, for example, an error processing routine within the multiplexed memory diagnostic program 41, and the CPU 20 Appropriate measures can be taken according to this error handling routine.

The CPU 20 executes the OFFTM instruction 43 at the end of the diagnosis by the multiplexed memory diagnosis program 41, and turns off (resets) the test mode flag 22 of the control register 21 (step S3 in the jff2 diagram). As a result, the test mode access state is released, and the diagnostic processing for the multiplexed memory device 10 ends.

In the embodiment described above, the state of the test mode flag 22 of the control register 21 is transferred to the memory control unit 13 in the multiplexed memory device 10 together with memory access information when the CPU 20 requests access to the multiplexed memory device 10. Although the explanation has been made assuming that the constant memory control unit 1
The configuration may be such that the information is transferred (notified) to the third party.

Further, in the embodiment described above, diagnosis of the multiplexed memory device 10 (offline memory unit therein) by access from the CPU 20 has been explained, but the present invention provides diagnosis from other devices using the multiplexed memory device 10, such as a channel device. It is also applicable to diagnosis using multiplexed memory device access. For example, in the case of a channel device, a flag corresponding to the test mode flag 22 is provided in the device, and turning on of this flag is controlled by the CPU 20 in order to start the device.
This is possible by specifying in the human output command given by.

[Effects of the Invention] As detailed above, according to the present invention, a control register is provided for each task, including a test mode flag indicating whether the task being executed is a diagnostic task or a general task. together with the multiplexed memory device, the CPU
A memory control means is provided that controls access to the memory unit in the multiplexed memory device according to the state of the test mode flag when there is an access request by executing a machine language instruction from the test mode flag. If so, the configuration is configured to access a memory unit that is disconnected from the system.
Diagnosis and testing of this separated memory unit can be performed without affecting online operations while the system is online, and without requiring any special diagnostic equipment.
It can be done from U through. in this way,
Since it is possible to perform diagnosis at the same level as in an online operation mode that includes multiplexed memory devices, it is possible to install the system with confidence after replacing the memory unit.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a computer system to which the present invention is applied, FIG. 2 is a flowchart explaining the processing procedure of the multiplexed memory diagnostic program 41 shown in FIG. 1, and FIG. 2 is a flowchart for explaining the operation of the memory control unit 13 in FIG. 1. FIG. 10... Multiplexed memory device, 11.12... Memory unit, 13... Memory control unit, 20... CPU
, 21... Control register, 22... Test mode flag, 30... Bus, 40... O5 (operating system), 41... Multiplexed memory diagnostic program, 42... ONTM instruction (test Mode access O
N instruction), 43...OFFTM instruction (test mode access OFF instruction). Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (1)

[Claims] In a computer system including a multiplexed memory device having a plurality of memory units and a CPU that accesses the multiplexed memory device, a task being executed is for diagnosing the multiplexed memory device. A control register that includes a test mode flag indicating whether it is a diagnostic task or a general task and that can be controlled for each task, and a control register that can be controlled for each task; memory control means provided in the multiplexed memory device for controlling access to the memory unit according to the state of the test mode flag in the control register, wherein the test mode flag indicates a diagnostic task; By accessing a memory unit that is disconnected from the system among the plurality of memory units, the disconnected memory unit is transferred to the CPU.
An online diagnosis method for a multiplexed memory device, characterized in that the diagnosis can be made while the system is online.