JPH0474033A - Error insertion circuit - Google Patents

Abstract

PURPOSE:To generate a test signal with an optional frame error by using a 1st setting device and a 2nd setting device setting a count period to a counter so as to insert an error pulse in a frame B in a frame A optionally. CONSTITUTION:A counter 3 counts frame pulses F of an input data Di by a number A set at a 1st setting device 1, a comparator 4 compares the count A with a count number B set by a 2nd setting device 2 and outputs an output C of a level H only when the number A is smaller than a 2nd number B. Then an output of an AND circuit 5 ANDing the output C of the comparator 4 and an error pulse E to be inserted and the input data Di are exclusively ORed by an EX-OR circuit 6, then a test signal Do for a frame error is obtained in which an error pulse E is inserted to frame of an optional number B in a prescribed frame A of the data Di.

Description

[Detailed Description of the Invention] [Summary] Counts the number of frame pulses of input data with a counter,
Regarding an error insertion circuit that outputs a test signal in which an error pulse is inserted into a predetermined number of frames A, a frame error test is performed by inserting an error pulse into an arbitrary number B of frames of a predetermined number of input data frames. The first setter is intended for a circuit that generates a signal, and causes the counter to count a predetermined number of frame pulses of input data, and the second setter causes the counter to count an arbitrary number B smaller than the predetermined number A.
a setter and a comparator that outputs an H level output only when the number A set and counted by the first setter is smaller than the number B set and counted by the second setter, the comparator and the error pulse to be inserted into the input data.The output of the EX-OR circuit takes the exclusive OR of the output of the ND circuit and the input data. The configuration is such that error pulses are inserted into an arbitrary number B of frames to serve as a frame error test signal.

[Industrial application field]

The present invention relates to data transmission, and in particular to a frame error alarm circuit that monitors a predetermined number of frames of input data and generates or cancels an alarm when an error frame among them exceeds or falls below the number of frames B. The present invention relates to an error insertion circuit that inserts error pulses into input data to generate test signals when testing.

As a test signal for a frame error alarm circuit, it is necessary that the number A of frames to be monitored and the number B of error frames that provide a limit value for generating or canceling an alarm can be arbitrarily set and easily changed.

[Conventional technology]

The conventional frame error test signal generation circuit is as shown in FIG. Count only A.

The counter 23 outputs one carry-out Ca every time the number of frames reaches the set number,
The AND circuit 25 takes the AND of the carryout Ca and the error pulse E to be inserted, and the EX-OR circuit 26 takes the exclusive OR of the AND output and the manual data Di, and the output is , an error pulse E is input to the input data Di.
The test signal Doa was generated with the inserted test signal Doa.

[Problem to be solved by the invention]

The conventional frame error test signal generation circuit described above is
A problem has arisen in that the error pulse E can only be inserted into one frame of the predetermined number of frames set by the setting device 21 for the counter 23 that counts the number of input data row 10 frame pulses F. .

An object of the present invention is to provide a circuit that generates a frame error test signal by inserting an error pulse into an arbitrary number B of frames of a predetermined number of input data Di.

[Means to solve the problem]

As shown in the principle diagram of FIG.
A second setting device 2 that counts the number A, and outputs an output C at level H only when the number A set and counted by the first setting device is smaller than the number B set and counted by the second setting device 2. An EX-OR circuit 6 which includes a comparator 4 and takes the exclusive OR of the output of an AND circuit 5 which takes the logical product of the output C of the comparator 4 and the error pulse E to be inserted, and the input data Di. This problem is solved by the present invention, in which the output of the input data Di is configured to be a frame error test signal Do in which an error pulse E is inserted into a predetermined frame of the input data Di and an arbitrary number B of frames.

C action] Counter 3 receives input data DiO frame pulse F,
Count only the number A set with the first setting device 1, and set the number B with the second setting device 2 to that count value.
A comparator 4 compares the numbers and outputs a level H output C only when the number A set and counted by the first setter 1 is smaller than the number B set and counted by the second setter 2. And the output C of this comparator 4 and the error pulse E to be inserted
An EX-OR circuit 6 calculates the exclusive OR of the AND circuit 5 and the input data Di, and outputs the output from an arbitrary value in a predetermined frame A of the input data Di. It is assumed that a frame error test signal Do is obtained by inserting an error pulse E into several B frames.

Therefore, the error insertion circuit of the present invention generates a frame error test signal by inserting an error pulse E into an arbitrary number B of frames of a predetermined number of frames of input data Di, so one problem can be solved. resolved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the error insertion circuit according to the embodiment of the present invention.
Count the number A set in step 1, for example A・100
Assuming that the counter 13 is set to a decimal counter by the setting device 11, the counter 13 will be a decimal counter from 0 to 9.
9, and 100 frames of input data Di are counted. On the other hand, the second setter 12 sets the number B of frames into which the error pulse E is inserted. For example, assuming B.50, the comparator 14 becomes level H when A<B, that is, when the count value of the counter 13 is between 0 and 49, and outputs an error pulse via the AND circuit 15 and the EX-OR circuit 16. Insert E into input data Di. When the count value of the counter 13 is between 50 and 99, A>B, so the output of the comparator 14 is at level L, the error pulse E is masked by the AND circuit 15, and the error pulse E is inserted into the input data Di. Not done. Therefore, the error pulse E is inserted into 50 frames out of 100 frames of the input data Di.

As described above, the error insertion circuit according to the embodiment of the present invention shown in FIG. If it is determined arbitrarily under the following, it becomes possible to generate a frame error test signal by inserting the error pulse E into an arbitrary number B of frames of the input data Di, so the problem is solved. None.

〔Effect of the invention〕

As explained above, according to the present invention, an error pulse is inserted into a B frame in an arbitrary A frame by the first setting device and the second setting device that set the counting period for the counter, and an error pulse is inserted into an arbitrary B frame in an arbitrary A frame. This has the effect of generating a frame error test signal.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the basic configuration of the error insertion circuit of the present invention, FIG. 2 is a block diagram showing the configuration of the error insertion circuit of the embodiment of the present invention, and FIG. 3 is a diagram of the conventional frame error test signal. FIG. 2 is a block diagram of a generating circuit. In the figure, 1, 11.21 is a setter for the number of frames,
2.12 is a setter for the number of frames B, 3, 13.23 is a counter that counts the number of frames, 4, 14 is a comparator, 5.15.25 is an AND circuit that masks error pulses, 6, 16 .26 is an EX-OR circuit that inserts an error pulse.

Claims (1)

[Claims] A signal (D) is obtained by counting the number of frame pulses (F) of input data (Di) with a counter (3) and inserting error pulses (E) into an arbitrary number B of frames among a predetermined number A of frames.
In the error insertion circuit that outputs the counter (o), the counter (
3) a first setter (1) that makes the frame pulse (F) of the input data (Di) count by a predetermined number A; and a second setter that makes the frame pulse (F) of the input data (Di) count by an arbitrary number B smaller than the predetermined number A. (2), and a comparator (4) that outputs an H level output (C) only when the number A set and counted by the first setter is smaller than the number B set and counted by the second setter. ), the AND circuit (5) takes the logical product of the output (C) of the comparator and the error pulse (E) to be inserted into the input data (Di).
The output of the EX-OR circuit (6) which takes the exclusive OR of the output of the input data (Di) and the input data (Di) is
An error insertion circuit characterized in that an error pulse (E) is inserted into a predetermined number B of frames of the predetermined number A of frames of i) to serve as a frame error test signal (Do).