JPH0469748A - Logical cache memory - Google Patents

Abstract

PURPOSE:To improve the system performance by checking whether a block loaded by referring to a physical tag by a real address of a block load request exists on a cache already or not, so that the same block is not subjected to mapping to plural compartments. CONSTITUTION:Logical tags 8, 9 are read out by an offset part of a logical address register 14, and hold a logical page address with respect to a block registered in a cache. Also, physical tags 12, 14 are read out by an offset part of a real address register 20 for holding a real address, and hold an effective bit V and a real page address P with respect to the block registered in the cache. In such a state, a controller 28 executes the control so that the same block on a real address space is not subjected to mapping to plural compartments by referring to the real address logical tags 8, 9 of block load at the time of block load to a cache memory 4 actuated by a mishit of the logical tags 8, 9. In such a way, the system performance is improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to logical cache memories.

[Conventional technology]

As a means of speeding up memory access, a cache memory is used, which has a copy of the memory within the processor and is comprised of high-speed RAM.

In traditional cache memory, blocks, which are units of mapping with memory, are managed using real addresses, and physical tags for this are generally indexed using real addresses, and are called real address caches. However, in this real address cache, in order to find the real address,
It is necessary to perform address translation from a logical address to a real address.

Therefore, in recent years, logical cache memories have appeared that have logical tags for managing blocks using logical addresses and index the blocks using the logical addresses. It can be said that the logical cache memory is advantageous because it does not involve address translation when a hit occurs.

For example, in the logical cache memory, as shown in FIG. 6, when the block at logical address 40000 of task A and the block at logical address 20000 of task B share the block at address 3000 in the same real address space. , 40000 of task A on the logical cache memory
Assuming that the address block and the 20000 address block of task B are stored in separate compartments, the execution results of task A will not be reflected in the block stored in the compartment of task B on the logical cache memory. , task B after executing task A
When task B executes , task B reads old data that does not reflect the execution result of task A from the logical storage memory.

Therefore, in order to solve this problem, the following means have been used in conventional logical cache memories.

The first is to adopt a direct map method consisting of a single compartment rather than a set associative method consisting of multiple compartments.

The second method is to flush (invalidate) all entries in the logical cache memory every time a task is switched.

[Problem to be solved by the invention]

The above-mentioned direct map method has the drawback of not only not being able to obtain a high cache hit rate but also of being limited in cache capacity.

In other words, in order to automatically reflect updates to the address translation table and memory updates by DMA from other processors or input/output devices to the logical cache memory, these are monitored using real addresses and the corresponding updates to the logical cache memory are performed. Blocks must be flushed (invalidated). To do this, it is possible to read both logical and physical tags by having physical tags in addition to logical tags, and reading each tag at an offset section (intra-page address) where the logical address and real address have the same value. It is necessary to match.

Therefore, since the entry address of the cache must be determined by this offset section, there is a drawback that the capacity of the direct map logical cache memory having an auto-flush function using real addresses cannot be made smaller than the page size.

Furthermore, with the method of flushing (invalidating) all the entries in the logical cache memory each time a task is switched, not only does it take a long time to switch tasks, but the cache hit rate decreases due to clearing all the entries. It also imitates (and causes) a decline in system performance.

[Means to solve the problem]

The memory of the present invention manages blocks, which are units of mapping to a cache memory storing copies of memory, using logical addresses, and in a set-associative logical cache memory composed of a plurality of compartments, the plurality of compartments are managed by addresses. A logical tag that is indexed using a task ID and logical page address assigned to each read task in an offset section as a key, and a physical tag corresponding to the logical tag that is indexed using a read real page address as a key in an offset section of the same address. and, when loading a block into the cache memory triggered by a miss in the logical tag, the same block in the real address space is mapped into multiple compartments by referencing the physical tag with the real address of the block load. The invention is characterized in that it has a controller that controls not to do so.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a memory, 2 indicated by a dashed line indicates a first processor including a logical cache memory, and 3 indicates a second processor having the same configuration as the first processor 2, and is connected to an address bus 101 and a data bus 102, respectively. Exchange data with each other.

The first processor 2 includes a requester 5 that requests instructions or data, a logical cache memory 4 configured to immediately output data to an arithmetic unit 6 according to a logical address output by the requester 5, and a logical cache memory. 4 comprises an address conversion unit 7 including a TLB for converting a logical address into a physical address when memory access is required.

In this embodiment, the logical cache memory 4 is composed of two compartments, including two logical tags 8, 9, 2 data arrays 10, 11, and 2 physical tags 12, 13.
including.

The logical tags 8 and 9 are read at the offset part of the logical address register 14 that holds the logical address, and as shown in FIG. Holds a logical page address consisting of table number P.

Whether or not a block is registered in the cache is determined by address comparators 16 and 17 comparing the index address on the logical address register 14 and the contents in the logical tags 8 and 9.

Data arrays 10.11 each store data corresponding to block addresses corresponding to logical tags 8.9.

Therefore, when the address comparators 16 and 17 detect a match between the registered address and the index address, data is read out from the corresponding compartment to the read data register 18 via the selection circuit 15.

The physical tag 12.13 is read at the offset part of the real address register 20 that holds the real address, and holds the valid bit V and real page address P for the block registered in the cache, as shown in FIG. .

The offset portion of both the real address and the logical address indicates an address within the page and has the same value.

Therefore, each of the physical tags 12 and 13 can hold a real address corresponding to the content of the logical address of the logical tag 8.9.

The address bus 101 determines whether the block pointed to by the address on the address bus 101 is registered in the cache.
After loading the value into the real address register 20, the physical tag 12.13 is read, and the address comparators 22, 2
3 is determined by comparison with the index address on the real address register 20. The judgment results are held in flip-flops 24 and 25, and the offset portion of the index address is held in the flash address register 21.

Next, according to the instructions of the flip-flops 24.25, the selection circuits 2 of the logical tags 8, 9 and the physical tags 12.13, respectively.
6.27 to reset the valid bit V of the block pointed to by the flash address register 21.

The logical cache memory configured as described above operates as shown in the flowchart of FIG. 4, and this control sequence is realized by the controller 28.

That is, in FIG. 4, when a memory access request is generated from the requester 5, the logical address thereof is temporarily set in the logical address register 14. If the memory access request is a read request, logical tag 8
.

On the other hand, if a match is not detected in either of the address comparators 16 and 17, a cache miss occurs, and it is determined which of the two conversion blocks should be evicted. As this eviction algorithm, the conventional LRU method or FIFO method is used.

Next, the logical address on the logical address register 14 is converted into a real address by the address conversion section 7. At this time, if an address translation table already exists in the TLB in the address translation unit 7, address translation can be performed immediately by indexing that TLB.

If the TLB does not have an address translation table,
After expanding the address translation table on memory 1 into TLB, address translation is executed.

Then, the converted real address is output onto the address bus 101, set in the real address register 20, and the physical tags 12 and 13 are indexed.

If there is no match in either of the address comparators 22 or 23, it indicates that the block to be loaded does not exist on the logical cache 4, but if a match is detected by the address comparators 22 or 23, the block to be loaded does not exist in the logical cache 4. Indicates that the current block is already registered with another logical address.

At this time, the registration of this block is once invalidated (flushed).

To do this, as described above, the entry address of the cache to be flushed is held in the flash address register 21, and the logical tags 8, 9 and The valid bit V of the block pointed to by the flash address register 21 of the physical tag 12.13 is reset.

After waiting for the above cache block invalidation processing, a block load request is made to the memory 1. The block data is outputted from the memory 1 to the data bus 102, and after being temporarily held in the write data register 19, the block is loaded after the aforementioned evicted block. Also, a new address is registered in the corresponding logical tag 8.9 and physical tag 12.13. Next, data is read from the new block on the data array 10.11 to the data register 18, and is supplied to the arithmetic unit 6.

If the memory access request is a ride request, there is no difference from ride request processing in general cache control. That is, index logical tags 8 and 9,
If it is a hit, the write data from the arithmetic unit 6 is written into the hit block via the write data register 19. When there is a miss, writing to this cache is inhibited, but the write operation to the memory 1 is executed regardless of whether it is a hit or a miss.

That is, if the logical address is converted into a real address by the address conversion unit 7, and the result of indexing the TLB is a miss, the address conversion table in the memory 1 is converted to the TLB.
Address translation is performed after the expansion. Then, write data from the arithmetic unit 6 to the memory 1 is sent to the address bus 101 . Write to memory 1 via data bus 102.

By the way, in the case of a logical cache memory, the data in the logical cache of the corresponding page must be invalidated every time the address translation table is updated. At this time, the real page address of the evicted page is sent to address bus 10.
1, and by taking this into the real address register 20, the physical tag 12.13 is referenced, and if the corresponding block exists in the logical cache memory 4, it is controlled to be invalidated by the above-mentioned procedure. do.

Furthermore, when a memory write occurs by DMA of a CPU or an input/output device of another system, if a corresponding block exists in the cache of the own CPU, this block must be invalidated. At this time as well, the write address output to the address bus 101 is monitored, and by taking it into the real address register 20, the physical tag 12.1
3, if the corresponding block exists in the logical cache memory 4, it is controlled to be invalidated by the above-mentioned procedure.

The above embodiment has been described with respect to a write-through type cache memory in which data is written to the cache and also written to the memory 1 at the same time in response to a write memory access. However, even for write-back method (copy pack method) cache memory, if when loading a block, physical tag 12.13 is referenced at the block load real address and a block registered at a different logical address is detected. For example, by saving or invalidating this in the memory 1, it is possible to control so that the same block in the real address space 2 is not mapped to multiple compartments. This situation is shown in the flowchart of FIG.

〔Effect of the invention〕

As explained above, the present invention reads a plurality of compartments using the offset part of the address, uses a logical tag that indexes the task ID and logical page address assigned to each task as keys, and executes reading using the offset part of the same address. It has a physical tag that is indexed using an address as a key, and when loading a block to the cache memory that is triggered by a logical tag mishit, attempts to load by referring to the physical tag using the real address of the block load request. After checking whether the block already exists in the cache at another logical address,
By controlling the mapping so that the same block is not mapped to multiple compartments, it is possible to solve mapping problems associated with logical cache memories.

As a result, a large capacity set-associative logical cache memory consisting of multiple compartments can be configured.
In addition, since it can be configured without the need to disable the IJ (all the cache data every time a task is switched), this speeds up the task switching time and improves system performance.
This has the effect of doing two things.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a diagram showing the contents of a logical tag, FIG. 3 is a diagram showing the contents of a physical tag, and FIG. 4 is a diagram showing the control method of the present invention in a write-through cache memory. 5 is a flowchart showing the control method of the present invention in a copy-back cache memory, and FIG. 6 is a diagram showing an example of a case where two tasks share the same block in the real address space. It is. DESCRIPTION OF SYMBOLS 1... Memory, 2... First processor, 3... Second processor, 4... Logical cache memory, 5...
・Requester, 6... Arithmetic unit, 7... Address conversion unit, 8゜9... Logical tag 1.10.11... Data array, 12゜13... Physical tag, 14... Logical address register, 15.26.27... selection circuit, 1
6.17,22゜23...address comparator, 1
8...Read data register, 19...Write data register, 20...Real address register, 21...
-Flash address register, 24.25...Flip-flop, 28...Controller.

Claims (1)

[Scope of Claims] In a set-associative logical cache memory consisting of a plurality of compartments, a block, which is a unit of mapping to a cache memory that stores a copy of the memory, is managed by a logical address, and the plurality of compartments are managed by an address. A logical tag that is indexed using a task ID and logical page address assigned to each read task in an offset section as a key, and a physical tag corresponding to the logical tag that is indexed using a read real page address as a key in an offset section of the same address. and, when loading a block into the cache memory triggered by a miss in the logical tag, the same block in the real address space is stored in multiple compartments by referencing the physical tag with the real address of the block load. A logical cache memory comprising: a controller that controls mapping so as not to perform mapping.