JPH0465860A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent crosstalk and mutual interference of signals by arranging a third conducting film insulated from a first conducting film and a second conducting film, between the first and the second conducting films, and connecting the third conducting film with a low impedance voltage source. CONSTITUTION:A metal wiring layer 3 us connected with a P<+> type diffusion region 12 of low resistance through a contact part 3-1, and again connected with a metal wiring layer 3' through a contact part 3'-1. Said wiring layer 3 is a first conducting film. A second conducting film intersecting the first conducting film is a metal wiring layer 5 formed on the P<+> type diffusion region 2, and both of them intersect each other without electric connection. A polysilicon layer 6 is formed in an insulating layer 4 on the P<+> type diffusion region 2, and connected with a very low impedance power supply like power supply electric potential or earth potential. Hence the polysilicon layer 6 acts as electrostatic shield, and the coupling due to the parasitic capacitance between the P<+> type diffusion layer 2 and the metal wiring layer 5 is remarkably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of intersecting wiring in a semiconductor integrated circuit device, and more particularly to a structure of intersecting wiring in which signals propagating through intersecting wiring do not interfere with each other.

[Conventional technology]

Due to advances in LSI technology, semiconductor integrated circuits are increasingly required to have higher density and higher reliability in recent years.

Along with this, the wiring part of semiconductor integrated circuits has become multilayered,
Increasingly, there is a need to cross each other.

In the second case, a metal wiring layer is used as the wiring layer and the wiring layers are crossed, or a diffusion layer in the semiconductor substrate or a polysilicon layer on the semiconductor substrate is used as a part of the wiring layer.

Examples of these will be explained with reference to FIGS. 6 and 7.

FIG. 6 is an example of cross wiring formed by a diffusion layer and a metal layer formed in a semiconductor substrate. In FIG. 6, 71 is a P-type Si substrate, 72 is an N-type scattering layer 73.73', 73' is a silicon oxide film, 74.74' is a wiring layer made of a metal or polysilicon layer, and 75 is a metal Shows the wiring layer. The N-type resistive diffusion layer 72, which is a high impurity concentration diffusion region provided in the semiconductor substrate 71, is used as one wiring layer.

That is, the wiring layer 74 made of metal or polysilicon layer
, the diffusion layer 72 and the wiring layer 74' made of a metal or polysilicon layer are used as one wiring layer, and the metal wiring layer crossing the N' diffusion [72] is formed on the silicon oxide film 73' on the N' type scattering layer 72. 75 is another wiring, and the two are crossed.

FIG. 7 shows cross-wiring made of a polysilicon layer and a metal layer. In FIG. 7, 81 is a semiconductor substrate on which an element region (not shown) is formed, 82, 82' is a silicon oxide film, 83 is a polysilicon film, and 84 is a metal wiring layer, which is formed through the silicon oxide film 82'. The polysilicon film 83 and the metal wiring layer 84 have an intersecting structure.

In addition, cross-wirings are commonly used, including a conductive film made of a metal layer or a polysilicon layer formed on an MOS (MOS) transistor structure in a conductive state and an insulating film therebetween.

These structures have the advantage that one wiring layer can be formed by directly utilizing the manufacturing process for each element region of a semiconductor integrated circuit. For example, the N-type resistive diffusion layer 72 in FIG.
When used as a wiring layer, the diffusion layer 72 can be formed at the same time as the manufacturing process of the N-type MO3L transistor, and no special process is required for forming the wiring layer.

However, these structures have a parasitic capacitive coupling structure via an insulating film such as a silicon oxide film, and when a signal is applied to both wiring layers, a change in the signal applied to one wiring layer is caused by a type of capacitive coupling. This will affect the signal of the layer. In other words, cross-crossing between two signals due to parasitic coupling capacitance at the intersection of these wirings and mutual interference occur, resulting in malfunction of the semiconductor integrated circuit and failure to obtain desired performance and characteristics. This will cause inconvenience.

For this reason, especially when designing semiconductor integrated circuits, including circuits with high sensitivity, circuits that handle high-frequency signals, circuits that handle weak signals, and cases where both analog and digital circuits are formed on the same chip, Although these circuit blocks are placed separately, they are placed together only in a specific part of the semiconductor integrated circuit chip, and the design is such that the signals do not cross each other. This consideration is especially necessary when forming both analog and digital circuits on the same chip.

In other words, when the analog signal and digital signal intersect,
This is because, for example, noise for digital processing may be added to the analog signal, causing malfunctions in the analog processing.

[Problem to be solved by the invention]

However, in recent years, the scale of semiconductor integrated circuits has been increasing, and the scale of circuits formed on a chip has increased, resulting in higher density, and there are cases where control signals for analog circuits are generated from digital circuits. Furthermore, as the integration of circuits progresses, it has become difficult to design such that wiring for each signal does not intersect with wiring for other signals, which has been an obstacle in the design of semiconductor integrated circuits.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a cross-wiring structure free from signal crosstalk and mutual interference in a semiconductor integrated circuit device, in order to eliminate or significantly reduce the above-mentioned problems.

[Means and effects for solving the problem] In order to achieve the above object, the present invention provides a first conductive film formed in or on a semiconductor substrate to connect a second conductive film to a second conductive film via an insulating film. In a semiconductor integrated circuit device having a structure in which wiring formed by conductive films crosses each other, a third conductive film insulated from both the first conductive film and the second conductive film is provided between the first conductive film and the second conductive film; The structure is such that the third conductive film is connected to a low impedance voltage source.

By disposing a third conductive film connected to a low impedance power source between the wirings that intersect with each other, this conductive film acts as an electrostatic shield.

That is, coupling due to parasitic capacitance between the first conductive film and the second conductive film is extremely reduced, and mutual interference such as crosstalk between signals flowing through both conductive films can be extremely reduced. .

〔Example〕

(1) First example A first embodiment of the invention will be described with reference to FIG.

In Figure 1, a low-resistance diffusion region is used as one wiring layer,
This is an example in which the other layer is a metal wiring layer and a polysilicon layer is used as the third conductive film of the present invention.

In FIG. 1, l is an N-type silicon substrate, 2 is a P diffusion region, 3.3' is a metal wiring layer made of aluminum (Af), and 3-1.3'-1 is a metal wiring layer and diffusion region. 2, 4 is an insulating layer, 5 is, for example, Al
1 is a metal wiring layer, and 6 is a polysilicon layer which is grounded.

In the structure shown in FIG. 1, the metal wiring layer 3 is connected to the contact portion 3-1.
It is connected to the low-resistance P diffusion region 2 through the contact portion 3'-1, and again to the metal wiring layer 3' through the contact portion 3'-1, which is the first conductive film.

The second conductive film that intersects with this is P through the insulating layer 4.
゛゛A metal wiring layer 5 formed on the diffusion region 2,
The two intersect without being electrically connected to each other.

In the present invention, a polysilicon layer 6 is provided in the insulating layer 4 on the P diffusion region 2, and this polysilicon layer 6 is connected to a power supply with extremely low impedance such as a power supply potential or a ground potential. There is.

With this structure, the polysilicon layer 6 connected to the low impedance power source acts as an electrostatic shield, and coupling due to parasitic capacitance between the P diffusion region 2 and the metal wiring layer 5 is extremely reduced. As a result, mutual interference such as signal crosstalk can be minimized.

(2) Second embodiment A second embodiment of the present invention will be explained with reference to FIG.

In Fig. 2, the same symbols as in Fig. 1 indicate the same parts, and 2
0.20' is P' diffusion region, 21 is P.

The mold injection area is shown.

In the structure shown in FIG. 2, a P type region used as the first conductive film is used as a P type scattering layer 2020' and a P type implanted region 21 for forming a P type depletion MOS transistor or capacitor. This embodiment differs from the first embodiment in that .

The metal wiring layer 5, which is the second conductive film, is mutually insulated by an insulating layer 4, and the polysilicon layer 6 disposed in the insulating layer 4 is connected to a low impedance voltage source. Therefore, coupling due to parasitic capacitance between the metal wiring layer 5 and the P implanted region 21 can be reduced.

As in this embodiment, the P゛ type region is a P° type diffusion region 20.
．． 20' By using the P' type implantation region 21,
The LSI manufacturing process for forming a P-type depletion MO3I-transistor can be applied as is, and there is an advantage that no special process is required for forming a conductive film for wiring. In this case, the polysilicon layer 6 is preferably connected to the ground terminal (D0).

As a result, the number of holes in the P° type injection region 21 can be increased, and the resistance of the P° type injection region 21 can be reduced.

(3) Third embodiment The third embodiment of the present invention will be explained in the third part.

In Fig. 3, the same symbols as in Fig. 1 indicate the same parts, and 7
is the P-type well region, 8.8' is the N' diffusion region, and 9 is the N
゛The large areas of note are shown respectively.

The third embodiment includes a metal wiring 3 as a first conductive film, an N-diffused region 8,8' and an N-implanted region 9 formed in a P-type well region provided in an N-type Si substrate l. Second in that it uses
This is different from the example.

A metal wiring layer 5 as a second conductive film that intersects with the N-implanted region 9 of the first conductive film is insulated from each other by an insulating layer 4. By applying a positive power supply potential to the polysilicon film 6 as the third conductive film, the polysilicon II 6 acts as a shield and prevents parasitic interference between the N-type implantation tujJ9 and the metal wiring layer 5. Coupling due to capacitance is reduced.

This N゛゛ diffusion region 8.8' and N゛ type compression region 9N
The process for manufacturing N-type or CMO3 LSIs that can form MO3) type depletion transistors can be applied as is.

In this case, it is preferable that the polysilicon layer 6 be connected to the power supply terminal Vec. As a result, N゛゛ injection region 9
The number of conduction electrons can be increased, and the resistance of the N injection region 9 can be reduced.

(4) Fourth example A fourth embodiment of the present invention will be explained with reference to FIG.

In FIG. 4, 51 is a semiconductor substrate on which an element region (not shown) is formed, and 52, 52', and 52'' are, for example, 5iO21.
1, 53 is a polysilicon layer, 54.5
For example, 4' and 54' are A! a first metal layer consisting of 55
indicates the second metal layer.

The structure of this embodiment includes a polysilicon layer 53 and a first metal layer 54 formed on a semiconductor substrate 51 via an insulating layer 52.
．． 54' is a first conductive film, and a second metal layer 55 is formed on the polysilicon layer 53 via an insulating film 52''.
is the second conductive film, and the double-door conductive films are arranged to intersect. An insulating film 52' 52 is placed between the two.
The first metal layer 54'' is sandwiched between the first metal layer 54'' and the first metal layer 54''.
54', and by connecting this first metal layer 54'' to a ground potential or a power supply potential, it can be used as a shielding electrode.

This structure allows the polysilicon layer 53 to be formed at the same time as the gate electrode of the MO3I-transistor formed in another region on the semiconductor substrate. Also, the first metal layer 54.54
', 54' can be formed by the same process, and this cross-wiring structure can be formed by directly applying the manufacturing process of MO3LSr, which allows two-layer metal wiring.

(5) Fifth example A fifth embodiment of the present invention will be explained with reference to FIG.

In Fig. 5, the same reference numerals as in Fig. 5 indicate the same parts;
3 represents the first polysilicon layer, 53' represents the second polysilicon layer, and 54 and 54' represent the first metal layer.

The structure of this embodiment is that the first conductive film and the second conductive film that intersect are the same as the fourth embodiment shown in FIG. 4, but the third conductive film arranged for shielding is The difference is that a second polysilicon layer 53' is used. This second polysilicon layer 53' is connected to both the first polysilicon layer 53, which is the first conductive film, and the second metal layer 55, which is the second conductive film that intersects with the insulator layer 52'. , 52'' and are connected to be kept at ground potential or power supply potential, and therefore act as an electrostatic shield.

This structure is an LSI that can form two polysilicon layers.
It has the advantage that it can be formed by applying the same manufacturing process as before.

In addition, in addition to these embodiments, if three metal layers can be formed through insulating layers, it is possible to replace the lowest polysilicon layer 53 with a metal layer in the fourth embodiment. Needless to say.

〔Effect of the invention〕

By adopting the structure of the present invention for the cross-wiring portion in a semiconductor integrated circuit, parasitic capacitive coupling occurring between the two intersecting conductive films can be extremely reduced due to the electrostatic shielding effect of the third conductive film. As a result, mutual interference such as cross-crossing of signals flowing through two intersecting conductive films is significantly reduced, making it possible to increase the density and reliability of the semiconductor integrated circuit device. This is particularly effective when an analog circuit and a digital circuit are formed on the same semiconductor chip, and their signals flow on intersecting wiring.

The cross-wiring structure of the present invention also has the advantage that it can be applied and formed without changing the manufacturing process of ordinary semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of the first embodiment of the present invention, FIG. 2 is an explanatory diagram of the configuration of the second embodiment of the invention, and FIG. 3 is an explanatory diagram of the configuration of the second embodiment of the invention.
4 is an explanatory diagram of the configuration of the fourth embodiment of the present invention; FIG. 5 is an explanatory diagram of the configuration of the fifth embodiment of the present invention;
FIG. 6 and FIG. 7 are explanatory diagrams of the configuration of a conventional example. 1.51-semiconductor substrate, 2.20.20', 21-P"
Mold region, 3.3', 54.54' 54 First metal wiring layer, 4.52.52' Insulator film, 5.55-Second metal wiring layer, 6.53.53'-Poly silicon layer. Patent applicant: Hitachi, Ltd. Fuji Xeronx Co., Ltd.

Claims (4)

[Claims] (1) A low-resistance diffusion region formed in a semiconductor substrate is
In a semiconductor integrated circuit device having a structure in which a wiring made of a conductive film intersects with a wiring made of a second conductive film formed insulated from the first conductive film, the first conductive film A semiconductor integrated circuit device, characterized in that a third conductive film is disposed between the first conductive film and the second conductive film, the third conductive film being insulated from both the conductive films and connected to a low impedance voltage source. (2) Wiring using a first conductive film formed via an insulator layer on a semiconductor substrate, and wiring using a second conductive film formed on top of the first conductive film insulated from the first conductive film. In the semiconductor integrated circuit device, a third conductive film is provided between the first conductive film and the second conductive film, the third conductive film being insulated from both and connected to a low impedance voltage source. A semiconductor integrated circuit device characterized in that: (3) The semiconductor integrated circuit device according to claim 1 or 2, wherein a polysilicon layer is used as the third conductive film. (4) The semiconductor integrated circuit device according to claim 1 or 2, wherein a metal layer is used as the third conductive film.