JPH0465746A - Bus - Google Patents

Abstract

PURPOSE:To make it possible to use a bus for both of synchronous communication and asynchronous communication in common by providing the bus with a means for controlling a synchronizing signal and a means for controlling an asynchronizing signal. CONSTITUTION:In the case of reading out a data from a storage part 3 or an I/O part 4 by a data processing part 2 e.g., an access request output part 8 outputs an asynchronous access request signal 21 to a common bus 6. An access information output part 9 outputs access information 22 received from a data processing part 2 to the bus 6 synchronously with a reference clock 19 for the bus 6, and simultaneously the output part 8 outputs a synchronous access request signal 20. An asynchronous access request receiving part 17 synchronizes the signal 21 with an I/O part reference clock 27, an asynchronous response signal output part 18 outputs an asynchronous response signal 25 and an asynchronous response signal synchronizing part 12 synchronizes the signal 25 with the clock 19. Consequently, a part synchronized with the reference clock and an asynchronous part can use on bus in common.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to buses, particularly buses between central processing units and storage devices or input/output devices.

[Conventional technology]

Conventionally, this type of bus has used either a bus using synchronous communication means that sends and receives data based on a reference clock, or a bus that uses asynchronous communication means that sends and receives data not based on a reference clock. was.

[Problem to be solved by the invention]

The above-mentioned conventional bus has the disadvantage that the devices that can be connected to the bus can only be selected from either synchronous communication means or asynchronous communication means. When using synchronous communication means, all devices are controlled by a single reference clock, so the frequency of the reference clock must be set within the operating range of the main parts of the device. The lock may not be optimal, which has the disadvantage of reducing performance. Furthermore, since the entire device depends on the reference clock, it is difficult to change the frequency of the reference clock.

In addition, when using asynchronous communication methods, the main part and peripheral parts each operate with separate reference clocks, so data communication between each part always requires signal synchronization, which significantly reduces performance. There were drawbacks.

[Means to solve the problem]

The bus of the present invention is a bus for exchanging data between a data processing device, a storage device, and an input/output device, and includes a synchronous communication means for transmitting and receiving data based on a reference clock, and a synchronous communication means for transmitting and receiving data not based on a reference clock. means for outputting access information to the bus; means for controlling a synchronization signal for using the bus in synchronization with a reference clock; and means for returning a response signal in synchronization with the bus; A means for controlling asynchronous signals for use without synchronization with a clock, a means for asynchronously returning a response signal, and a means for controlling address signals, bus control signals, and data signals in both synchronous communication means and asynchronous communication means. shared,
The present invention is characterized by comprising: access request means and response means used in the synchronous communication means; and means and response means for making a preliminary access request to access information used in the asynchronous communication means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment of a synchronous asynchronous shared bus according to the present invention.

The synchronous asynchronous shared bus 1 is centered around a shared bus 6, has a reference clock generator 7 that generates a reference clock for the shared bus 6, and is connected to each of the data processing section 2, storage section 3, input/output section 4 and the shared bus 6. It consists of the parts that connect the

The space between the data processing section 2 and the shared bus 6 includes an access request output section 8 , an access information output section 9 , a data input/output section 10 , a response signal reception section 11 , and an asynchronous response signal synchronization section 12 .

A reference clock receiving unit 13 is connected between the storage unit 3 and the shared bus 6.
, synchronous access request receiving unit 14 and access information receiving unit 1
5, a data input/output section 10, and a synchronization response signal output section 16.

Between the input/output unit 4 and the shared bus 6 are an asynchronous access request receiving unit 17, an access information receiving unit 15, and a data input/output unit 1.
0 and an asynchronous response signal section 18. Input/output section 4
receives a clock supply from the human output section reference clock generation section 5.

The data processing unit 2 is a part that receives data from the synchronous asynchronous shared bus 1, performs various processing, and outputs it to the synchronous asynchronous shared bus 1. The storage unit 3 receives data from the synchronous asynchronous shared bus 1, stores it, The input/output unit 4 outputs data received from the synchronous asynchronous shared bus 1 to the outside in response to a request, and outputs data 23 input from the outside (see Fig. 2). ~FIG. 5) This is the part that outputs to the synchronous/asynchronous shared bus 1.

Here, cases in which the data processing section 2 reads and writes data from the storage section 3, and cases in which the data processing section 2 reads and writes data from the input/output section 4 will be explained. Note that the storage section 3 operates in synchronization with the reference clock 19 (FIGS. 2 to 6), and the input/output section 4 operates in synchronization with the human output section reference clock 27 (the fourth
It is assumed that the reference clock 19 operates in synchronization with the reference clock 19 (Figs. to 6) and asynchronously with the reference clock 19.

First, when reading data in synchronization with the reference clock 19 as shown in FIG. 2, an example in which the data processing section 2 reads data from the storage section 3 will be described. When the data processing unit 2 reads data from the storage unit 3, the data processing unit 2
outputs the access request to the access request output section 8.

In response to this, the access request output unit 8 first outputs the asynchronous access request signal 21 to the shared bus 6. Then, the access information output section 9 outputs the access information received from the data processing section 2 to the shared bus 6 in synchronization with the reference clock 19, and at the same time, the access request output section 8 outputs a synchronous access request signal 20. At this time, the storage unit 3 connected to the synchronous asynchronous shared bus 1 checks the access information 22 indicated by the access information receiving unit 15 in response to the synchronous access request from the synchronous access request receiving unit 14, and determines whether it has been selected for reading. If so, the read data specified by the access information 22 is output to the data input/output section 10.

At the same time, a response signal is also output to the synchronous response signal output section 16. As a result, the data input/output section 10 is connected to the shared bus 6.
The synchronization response signal output unit 16 outputs the data 23 in synchronization with the reference clock 19 to the shared bus 6.
Since the synchronization response signal 24 and the synchronization response signal 26 (Figs. 4 to 6) are monitored according to the synchronization response signal 24
When it indicates a response, it outputs a response signal to the data control section 2.

The data processing section 2 that received the response signal is the data input/output section 10.
Data is fetched from the synchronous and asynchronous shared bus 1, and access to the synchronous and asynchronous shared bus 1 is terminated.

Next, when writing data in synchronization with the reference clock 19 as shown in FIG. 3, an example will be described in which the data processing section 2 writes data to the storage section 3. When the data processing unit 2 writes data to the storage unit 3, the data processing unit 2
outputs the access request to the access request output section 8. In response to this, the access request output unit 8 first outputs the asynchronous access request signal 21 to the shared bus 6. Then, the access information output unit 9 outputs the access information received from the data processing unit 2 to the shared bus 6 in synchronization with the reference clock 18, and the access request output unit 8 outputs the synchronous access request signal 2.
Outputs 0.

At this time, the storage unit 3 connected to the synchronous asynchronous shared bus 1 checks the access information 22 indicated by the access information receiving unit 15 in response to the synchronous access request from the synchronous access request receiving unit 14, and determines whether it has been selected for writing. If so, the data is taken in from the data input/output unit 10 and written to the location specified by the access information 23. When writing is completed, a response signal is outputted to the synchronous response signal output section 16. Due to this, the synchronous response signal output section 16
outputs a synchronous response signal 24 to the shared bus 6 in synchronization with the reference clock 19.

Thereafter, since the response signal receiving section 11 monitors the synchronization response signal 24 and the synchronization response signal 26 in accordance with the reference clock 19, when the synchronization response signal 24 indicates a response, it outputs a response signal to the data control section 2. do. Upon receiving the response signal, the data processing unit 2 terminates access to the synchronous asynchronous shared bus 1.

Next, when reading data 23 not synchronized with the reference clock 19 as shown in FIG. 4, an example in which the data processing section 2 reads data from the input/output section 4 will be described. When the data processing section 2 reads data from the input/output section 4, the data processing section 2 outputs an access request to the access request output section 8. In response to this, the access request output unit 8 first outputs the asynchronous access request signal 21 to the coexistence bus 6. Then, the access information output section 9 outputs the access information received from the data processing section 2 to the shared bus 6 in synchronization with the reference clock 19, and at the same time, the access request output section 8 outputs a synchronous access request signal 20.

At this time, the asynchronous access request receiving section 17 synchronizes the asynchronous access request signal 21 with the human output section reference clock 27 and passes the access request signal to the output section 4. The input/output section 4 receives the access information receiving section 15 based on this access request.
The access information 22 indicated by is checked, and if it is selected for reading, the read data specified by the access information 22 is output to the data input/output unit 10. At the same time, a response signal is also output to the asynchronous response signal output section 18. As a result, the data input/output section 10 outputs the data 23 to the coexistence bus 6, and the asynchronous response signal output section 18 outputs the asynchronous response signal 25 to the shared bus 6.

Thereafter, the asynchronous response signal synchronizing section 12 synchronizes the asynchronous response signal 25 with the reference clock 19 and outputs the synchronized synchronized response signal 26 to the response signal receiving section 11 .

Since the response signal receiving section 11 monitors the synchronization response signal 24 and the synchronization response signal 26 in accordance with the reference clock 19, it outputs a response signal to the data control section 2 when the synchronization response signal 26 indicates a response. Data processing unit 2 that received the response signal
takes in data from the data input/output unit 10 and ends access to the synchronous asynchronous shared bus 1.

Next, when writing data that is not synchronized with the reference clock data 9 as shown in FIG. 5, an example will be described in which the data processing section 2 writes data to the input/output section 4. When the data processing section 2 writes data 23 to the input/output section 4, the data processing section 2 outputs an access request to the access request output section 8. In response to this, the access request output unit 8 first outputs the asynchronous access request signal 21 to the shared bus 6. Then, the access information output section 9 outputs the access information received from the data processing section 2 to the shared bus 6 in synchronization with the reference clock 19, and at the same time, the access request output section 8 outputs a synchronous access request signal 20.

At this time, the asynchronous access request receiving section 17 synchronizes the asynchronous access request signal 21 with the input/output reference clock 27 and passes the access request to the input/output section 4.
checks the access information indicated by the access information receiving section 15 based on this access request, and if writing is selected, takes in the data from the data input/output section 10 and writes it to the location specified by the access information 23.

Thereafter, the response signal is also output to the asynchronous response signal output section 16. As a result, the data input/output unit 10 outputs the data 23 to the shared bus 6, and the asynchronous response signal output unit 16 outputs the asynchronous response signal 25 to the shared bus 6.

Thereafter, a response signal is also output to the asynchronous response signal output section 16. As a result, the data input/output section 10 is connected to the shared bus 6.
The asynchronous response signal synchronizing section 12 synchronizes the asynchronous response signal 25 in accordance with the reference clock 19 and outputs a synchronized response signal 26 to the response signal receiving section 11 . Since the response signal receiving section 11 monitors the synchronization response signal 24 and the synchronization response signal 26 in accordance with the reference clock 19, when the synchronization response signal 26 indicates a response, the data control section 2
Outputs a response signal to The data processing unit that has received the response signal ends access to the synchronous asynchronous shared bus 1.

Finally, FIG. 6 shows a case where an asynchronous access request according to the present invention is not made. Input/output section 4 when not using the present invention
Since the start of synchronization of the access request 20 with the human output section reference clock 27 is delayed by one clock, the access time of the input/output section 4 requires seven clocks. In the case of the present invention, as shown in FIG. 4 described earlier, the clock is 6, which is one clock shorter.

〔Effect of the invention〕

As explained above, the present invention realizes both a synchronous communication means and an asynchronous communication means with one bus.
The part synchronized with the reference clock and the part asynchronous to the reference clock can share one bus, which has the advantage of saving the number of signal lines used for the bus.

In addition, since you can choose between synchronous and asynchronous communication means, you can use the synchronous communication means if you frequently communicate data, and if you want to operate with a highly independent reference clock, you can gradually set the standard. When a change in the clock is expected, using an asynchronous communication means has the advantage of being able to flexibly respond to changes in the device while ensuring the performance of the device.

Further, in the case of asynchronous access, synchronization loss can be reduced by issuing the access request signal in advance, and this embodiment has the advantage that the asynchronous access time is shortened by one clock.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a synchronous asynchronous shared bus according to the present invention, FIGS. 2 and 3 are timing charts of synchronous communication according to the present invention, and FIGS. 4 and 5 are timing charts of asynchronous communication according to the present invention. FIG. 6 is a timing chart of conventional asynchronous communication. 1...Synchronous asynchronous shared bus, 2...Data processing unit,
3... Storage section, 4... Input/output section, 5... Person output section reference clock generation section, 6... Shared bus, 7... Reference clock generation section, 8... Access request section , 9... access information output section, 10... data input/output section, 11.
...Response signal receiving section, 12... Asynchronous response signal synchronizing section, 13... Reference clock receiving section, 14... Synchronous access request receiving section, 15... Access information receiving section, 1
6. -...Synchronous response signal output unit, 17...Asynchronous access request receiving unit, 18...Asynchronous response signal output unit.

Claims (1)

[Scope of Claims] A synchronous communication means for transmitting and receiving data based on a reference clock in a bus for exchanging data between a data processing device, a storage device, and an input/output device; and a synchronous communication means for transmitting and receiving data not based on the reference clock. means for outputting access information to the bus; means for controlling a synchronization signal for using the bus in synchronization with a reference clock; and means for returning a response signal in synchronization with the bus; A means for controlling asynchronous signals for use without synchronization with a clock, a means for asynchronously returning a response signal, and a means for controlling address signals, bus control signals, and data signals in both synchronous communication means and asynchronous communication means. shared,
A bus comprising: access request means and response means used in synchronous communication means; and means and response means for making a preliminary access request to access information used in asynchronous communication means.