JPH0465598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase switching method for switching the phase between 0 degrees and 180 degrees using a phase switching signal, and a circuit thereof, in particular, a phase switching method for switching the phase between 0 degrees and 180 degrees using a phase switching signal, and a circuit thereof. The present invention relates to a phase switching method and its circuit that can be applied to a color signal processing circuit of a simple magnetic recording/reproducing device (VTR) that converts and records data.

Conventional configuration and its problems As a method to improve image quality deterioration due to chrominance signal crosstalk in the above-mentioned simple VTR with two rotating heads, the phase of the chrominance signal low frequency carrier wave is set to 0 degrees for each line only during one field. , 180 degrees and a recording method has been devised and put into practical use. As a circuit for this purpose, a phase switching circuit is used in the color signal processing circuit.

In the above method, during recording, the color signal carrier wave (frequency c, approximately 3.58MHz in the NTSC system) is converted to the color signal low frequency carrier wave (frequency s, approximately 700KHz, for example);
During reproduction, the frequency is (c+s) and the phase is 0 degrees due to the phase switching input signal (signal with half the line frequency _H , or frequency 1/2 _H ) to convert the frequency of the color signal low frequency carrier wave to the color signal carrier wave. A signal that switches 180 degrees is required. However, (c+
It is not easy to create and switch two signals whose phases are exactly 0 degrees and 180 degrees at a frequency of +s) (approximately 4.3 MHz). This is because one degree of phase at 4.3 MHz corresponds to approximately 0.6 ns in time, and time delays due to differences in signal propagation paths in electronic circuits cannot be ignored. Therefore, in the past, by inputting the carrier wave of frequency (c + s) to a transformer with an intermediate terminal on the output side, the phase was accurately set to 0.
The phase switching circuit obtains two signals that are 180 degrees and 180 degrees, and the phase is 0 by the phase switching circuit that switches using the phase switching input signal.
There is a method of obtaining the signal of the frequency (c+s) switched between 180 degrees and 180 degrees. However, since it uses a transformer, it has problems such as not being able to be made into a semiconductor circuit and making it difficult to miniaturize.

If the frequency is low enough, even an electronic circuit that does not use a transformer can create a signal with a phase of exactly 0 degrees and 180 degrees. So first of all, low frequency o
By performing phase switching with the phase switching signal at , and then converting the frequency, the frequency (c + s) at which the phase is switched between 0 degrees and 180 degrees with the phase switching signal.
There is a method to obtain the signal. However, if a conventional phase switching circuit without a transformer is used in this method, a problem arises. In order to explain this problem, a conventional phase switching circuit will first be explained.

FIG. 1 shows a configuration diagram of a conventional phase switching circuit. Reference numeral 1 denotes a reference clock input terminal, into which a clock having a frequency twice or four times that of a carrier wave is input. 2 is a phase switching input signal terminal, 3 is a phase 0
4 is a switch circuit that selects one of the 2-phase clocks, and 5 is a synchronization circuit that eliminates phase errors due to propagation delays in switch circuit 4. , 6 are output terminals.

FIG. 2 shows operating waveforms of each part in the configuration of FIG. 1. In FIG. 2, A and B are two-phase clock outputs that are the outputs of the two-phase clock generation circuit 3, and C, D, E, and F are output waveforms of the synchronization circuit 5. If the reference clock has a frequency twice that of the carrier wave, the waveform when switching the phase will be C or D. If the reference clock has a frequency four times the frequency of the carrier wave, the waveform when switching the phase will be C or D or E or It becomes like F. Ta, Tb in Figure 2,
Tc and Td indicate phase switching periods.

A specific circuit example of the conventional phase switching circuit shown in FIG. 1 is shown in FIG. 3, and its operating waveform diagram is shown in FIG.
The operation will be explained below. Assuming that the frequency of the carrier wave whose phase is switched is o, a reference clock with a frequency of 2o is inputted to the terminal 37, and the frequency is divided by 2 by the flip-flop 31, and carrier waves with phases of 0 degrees and 180 degrees are obtained from the output Q, respectively. The reference clock and two-phase clock are respectively A and A in Figure 4.
Shown in B and C. The reason for frequency division by 2 is to set the duty cycle of the carrier wave to 50% and to remove the second-order component of the carrier wave, that is, the frequency 2o component, which is an unnecessary component that is difficult to remove with a filter.

A phase switching signal is applied to the terminal 38, and when the input is at the "Hi" level, the AND gate 33 opens and the signal becomes 0.
The carrier wave with a phase of 180 degrees is input to the OR gate 35, and when the input is at "Lo" level, the AND gate 34 is opened via the inverter 32, and the carrier wave with a phase of 180 degrees is input to the OR gate 35.
It is input to the OR gate 35. The carrier wave whose phase has been switched by the phase switching input signal applied from the terminal 38 is outputted from the OR gate 35 and inputted to the D-type flip-flop 36. A reference clock with a frequency of 2o input from an input terminal 37 is input to the clock input terminal of the flip-flop 36, and the output of the OR gate 35 is synchronized with this clock and output. The waveforms of the phase switching input signal, the output of the OR gate 35, the output of the flip-flop 36, that is, the output of the phase switching circuit are shown in D, E, and F of FIG. 4, respectively. In F of FIG. 4, the periods indicated by Ta and Tb coincide with the phase switching periods Ta and Tb in FIG.

Figure 5 shows a block diagram of the above-described method of obtaining the signal of frequency (c+s) whose phase is switched between 0 degrees and 180 degrees using the phase switching input signal by performing phase switching at frequency o and then converting the frequency. The problems encountered when a conventional phase switching circuit is used in this configuration will be described below. frequency o is s
Since there will be no inconvenience if you choose equal to
Let's explain by assuming o=s.

In FIG. 5, 9 is a phase switching circuit,
Reference numerals 7 and 8 are input terminals of the phase switching circuit, to which a reference clock and a phase switching input signal are applied, respectively. The output of the phase switching circuit 9 is applied to a balanced modulator 11 together with the output of an oscillation circuit (oscillation frequency c) 10 for frequency conversion. Since the frequency of the carrier wave of the phase switching circuit 9 is s, the balanced modulator 11 has a frequency of (c±
output the frequency component of s). A BPF 12 for extracting the necessary frequency component (c+s) is connected to the output of the balanced modulator 11. The frequency difference between frequencies (c+s) and (c−s) is approximately 1.4MHz
Since this BPF 12 is relatively small, a filter having a narrow band and steep characteristics is used. FIG. 6 shows, as an example, the frequency characteristics (shaded area) of the BPF 12 that extracts the (c+s) component.

Frequency of input signal at BPF12 and BPF1
The greater the difference from the center frequency (c+s) of the second passband, the greater the amount of output attenuation. Now, consider the output amplitude of the BPF 12 during the phase switching period.
During the phase switching periods Ta and Tb shown in FIG. 2, the frequency s component of the output of the phase switching circuit 9 decreases as is clear from the waveform, and the frequency 1/2s becomes the main frequency component, and the balanced modulator The frequency (c±s) component decreases in the output of 11, and the frequency (c±1/
2s) component is the main component. The frequency (c+1/2s) is
Since it is separated by 1/2s from the center frequency (c+s) of the passband of the BPF 12, the amplitude of the frequency (c+1/2s) component is attenuated by the gain G _A shown in FIG. Therefore, the phase switching period, BPF12
The output envelope of causes large attenuation. This situation is shown in FIG.

Similarly, the phase switching period Tc shown in FIG.
At Td, the frequency s component of the output of the phase switching circuit 9 decreases as is clear from the waveform, and the frequency
2s becomes the main frequency component, and the frequency (c±s) component decreases in the output of the balanced modulator 11, and the frequency (c±2s) component becomes the main frequency component. Frequency (c+2s)
is the center frequency of the passband of BPF12 (c+s)
Since the gain shown in Figure 6 is s apart from
The (c+2s) component is attenuated by G _B. Therefore, the output amplitude of the BPF 12 is greatly attenuated during the phase switching period. The output waveform of BPF12 at this time is the 7th
As shown in the waveform shown in the figure, since the deviation of the passband of the BPF 12 from the center frequency is large, the attenuation of the envelope of the output signal becomes larger.

During this phase switching period, the large fluctuation in the output amplitude of BPF12, especially the attenuation, is caused by the S/N of the carrier wave.
For example, if the next stage circuit is a balanced modulator, a carrier leak will occur in its output during the period when the level of the carrier wave (carrier signal) is attenuated. The problem arises as follows.

The above explanation was based on a configuration example of a VTR color signal processing circuit in which the necessary frequency components are obtained using the BPF after converting the frequency of the output of the phase switching circuit, but in general, the output of the phase switching circuit is directly passed through the BPF to obtain the necessary frequency components. Conventional phase switching circuits that do not use transformers also have the same problem when c = _0.
This becomes clear when you think about it.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
It is an object of the present invention to provide a phase switching method and circuit for generating a phase inversion signal that reduces fluctuations in the output envelope during a phase switching period and does not impair the stability of the circuit operation of the next stage.

Structure of the Invention The present invention sets the phase of the carrier wave to 0 degrees and 180 degrees in the input signal.
A phase switching method and a phase switching circuit suitable for implementing the method, in which the waveform at the phase switching point is a waveform of approximately one cycle having a frequency 2/3 times that of the carrier wave when switching between the carrier waves, and the waveform at the phase switching point is When the output of the phase switching circuit is input to a narrow band BPF with the carrier wave frequency as the center frequency by making it approximately one cycle with a frequency 2/3 times that of the carrier wave, the envelope of the output during the phase switching period of the BPF output It is possible to suppress fluctuations in the output voltage, especially attenuation, to a small level.

DESCRIPTION OF EMBODIMENTS Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram of an embodiment of the present invention, FIG. 9 is a specific circuit diagram thereof, and FIG. 10 is an operating waveform diagram thereof. In FIG. 8, 14 is an input terminal for a reference clock, 15 is an input terminal for a phase switching input signal, 16 is a 4-phase clock generation circuit, 17 is a gate pulse generation circuit, 18 is a switch circuit, 19 is a synchronization circuit, and 20 is the output terminal. A detailed explanation of the operation will be given in FIG. 9, so a brief explanation will be given here. The four-phase clock generation circuit 16 divides the reference clock input to the input terminal 14 by four to generate four-phase clock signals φ1, φ2, φ3, and φ4 whose phases are shifted by 90 degrees of the frequency s. The gate pulse generation circuit 17 synchronizes the phase switching input signal with φ2 or φ4 and outputs the phase switching input signal with φ1, φ4.
Gate pulses are generated to select each of φ2, φ3, and φ4. The switch circuit 18 selects one of the input four-phase clock signals using the gate pulse from the gate pulse generating circuit 17. The phase switching signal switches between φ1 and φ3, which have an inverted phase relationship with each other. When switching the phase from φ1 to φ3, φ2 must be selected for one cycle, and when switching the phase from φ3 to φ1, φ4 must be selected for one cycle. The gate pulse generating circuit 17 generates a gate pulse to select a cycle period. As a result, the waveform of the output of the switch circuit 18 during the phase switching period from φ1 to φ3 and from φ3 to φ1 is a 1-cycle waveform of a signal with a period of 1.5 times that of the clock signal, that is, a frequency of 2/3 s. becomes.

50, 51, 57, 58, 59 in Figure 9
is a D-type flip-flop, 52, 53, 54,
55, 60, 61, 62, 63 are AND gates,
56 is an OR gate. 14 is an input terminal for inputting a reference clock, 15 is an input terminal for a phase switching input signal, and 20 is an output terminal. The four-phase clock generation circuit 16 includes D-type flip-flops 50 and 51.
This is a 4-frequency divider circuit consisting of: In FIG. 10, A shows the waveform of the reference clock, and B, C, D, and E show the waveforms of the four-phase clock signals φ1, φ2, φ3, and φ4. The gate pulse generation circuit 17 includes D-type flip-flops 58, 59 and AND gates 60, 61,
It consists of 62 and 63. The phase switching input signal input to the terminal 15 is input to a D-type flip-flop 58 as a clock signal φ2, and the Q output of the D-type flip-flop 58 is input to a D-type flip-flop 59 as a clock signal φ2. This 2
Gate pulses are created by gates 60, 61, 62, and 63 based on the Q outputs and outputs of the flip-flops 58 and 59. In FIG. 10, which is a timing diagram, F is the phase switching input signal, G and H are the Q outputs of flip-flops 58 and 59, respectively.
Gates 60, 61, 6 for I, J, K, and L, respectively.
The output of 2,63 is shown. Gate 60, 61, 5
The outputs of 2 and 63 are clock signals φ1 and φ, respectively.
2, φ3, φ4 with the gate pulse to select φ1
These will be referred to as gate pulses, φ2 gate pulses, φ3 gate pulses, and φ4 gate pulses. As can be seen from the figure, after the φ1 gate pulse is output, the φ2 gate pulse is output for one cycle of the clock signal φ2 before the next φ3 gate pulse is output, and after the φ3 gate pulse is output, , φ4 for one cycle period of clock signal φ2 until the next φ1 gate pulse is output.
It is configured to output a gate pulse. The switch circuit 18 has gates 52, 53, 5
One of the four-phase clock signals φ1, φ2, φ3, and φ4 is selected by the gate pulse and outputted from the gate 56. gate 5
The output waveform of No. 6 is shown in M in FIG. The waveforms of the period Te of switching from clock signal φ1 to φ3 and the period T of switching from clock signal φ3 to φ1 shown in the waveform diagram correspond to the frequency of the four-phase clock signal.
2/3 times the frequency of s, or exactly 1 of the 2/3s signal
It can be seen that the waveform is a cycle. The switch circuit output has a phase error due to the propagation delay difference between the internal gates. Therefore, the output of the switch circuit is connected to the D input terminal of the flip-flop 57 corresponding to the synchronization circuit 19, and the phase error is removed by reading it with the reference clock.

The output of flip-flop 57 is the phase switching circuit output. This output waveform is shown at N in FIG.
In the frequency components of this output waveform during the phase switching period, the s component decreases and the frequency 2/3s component becomes the main component.

Now, when the phase switching circuit of this embodiment is used in the configuration shown in FIG. 5, the frequency component of the output of the balanced modulator 11 in FIG.
The component decreases, and the (c±2/3s) component becomes the main component. Since the frequency (c±2/3s) is 1/3s apart from the center frequency (c+s) of the passband of BPF12, the frequency (c+2/3s) is separated by the gain Gc shown in Figure 6.
s) The amplitude of the component is attenuated. However, since the attenuation can be made smaller than in the case shown in the conventional example,
It can be seen that fluctuations in the envelope of the output of the BPF 12, especially attenuation, can be reduced.

As described above, according to this embodiment, when the phase of the carrier wave is switched to the inverted phase, the waveform at the switching point is a one-cycle waveform with a frequency 2/3 times the frequency of the carrier wave, so that the phase switching circuit output
Envelope fluctuations, especially attenuation, of the BPF output when input to the BPF can be reduced, and deterioration of the S/N ratio at the phase switching point of the carrier wave and instability of the circuit operation of the next stage can be improved. In addition, since no transformer is used, it can be integrated into an integrated circuit and the circuit can be made smaller.

It also has the advantage of being able to have a large tolerance for variations in the gain-frequency characteristics of the BPF 12, that is, deviations in the center frequency.

Effects of the Invention The present invention allows only the carrier wave to pass by making the waveform at the phase switching point a waveform of approximately one cycle with a frequency 2/3 times the frequency of the carrier wave.
Obtained by inputting the phase switching circuit output to BPF
Envelope fluctuations, especially attenuation, at the phase switching point of the BPF can be reduced, and the S/N ratio of the carrier wave at the time of phase switching and the stability of the next stage circuit operation can be improved, which is highly effective. In addition, it is easy to integrate the circuit, it is easy to miniaturize the circuit, and the BPF
It is possible to have a large tolerance for variations in the center frequency.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional phase switching circuit, Figures 2 A to F are operating waveform diagrams of a conventional phase switching circuit, and Figure 3
The figure is a circuit diagram of an example of a conventional phase switching circuit, Figures 4A to 4F are its operating waveform diagrams, Figure 5 is a configuration diagram of an example of the use of the phase switching circuit, Figure 6 is a frequency characteristic diagram of BPF, 7 is an output waveform diagram of the BPF, FIG. 8 is a configuration diagram of a phase switching circuit according to an embodiment of the present invention, FIG. 9 is a detailed circuit diagram thereof, and FIG. 10 is an operational waveform diagram thereof. 9... Phase comparison circuit, 16... 4-phase clock generation circuit, 17... Gate pulse generation circuit, 18... Switch circuit, 19... Synchronization circuit.

Claims (1)

[Claims] 1. When converting the frequency of a color signal to the low frequency range of a frequency-modulated luminance signal and recording it, the phase of the low frequency carrier wave is switched between 0 degrees and 180 degrees every horizontal period. , in a magnetic recording and reproducing method in which the obtained output is frequency-converted, and then the necessary frequency components are selected by a band-pass filter, and the obtained waveform is used to frequency-convert the color signal to a lower frequency band. A magnetic recording and reproducing device characterized in that when the phase is switched between 0 degrees and 180 degrees using a phase switching input signal, a waveform at a phase switching point is a waveform of one cycle having a frequency 2/3 times that of the carrier wave. Method. 2. When converting the frequency of the color signal to the low frequency range of the frequency-modulated luminance signal and recording it, the phase of the low frequency carrier wave is switched between 0 degrees and 180 degrees every horizontal period, and the resulting output is In a magnetic recording and reproducing device that frequency-converts the color signal to a low frequency range using a waveform obtained by selecting necessary frequency components using a band-pass filter, the phase of the low-frequency carrier wave is adjusted horizontally. A phase switching circuit for switching between 0 degrees and 180 degrees for each period inputs a reference clock with a frequency four times that of the carrier wave, and divides the frequency by four to produce clock signals φ1 and φ whose phases are delayed by 90 degrees.
2, a clock generation circuit that generates φ3, and φ4;
The phase switching input signal generates a gate pulse that selects clock signals φ1 and φ3 that have an inverted phase relationship, and when switching from clock signal φ1 to clock signal φ3, clock signal φ2 is selected for one cycle period, and clock signal φ3 is selected. When switching from clock signal φ1 to clock signal φ4,
a gate pulse generation circuit that generates a gate pulse that selects the clock signal for only one cycle period, and a switch circuit that switches and outputs one of the clock signals φ1, φ2, φ3, and φ4 using the gate pulse from the gate pulse generation circuit; 1. A magnetic recording and reproducing apparatus comprising: a synchronization circuit that receives the output of the switch circuit as an input, synchronizes with the reference clock, and outputs the synchronized circuit.