JPH0465472B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal recording and reproducing device,
The object of this invention is to compensate for the time phase difference in signals due to the distance between a preceding reproduction head provided upstream of a recording head by means of an electrical memory time delay.

Digital signal recording and reproducing equipment that converts analog signals such as music signals into digital codes and records and plays them not only performs recording and playback independently, but also uses electronic equipment that edits and connects music tapes without cutting them. Punch-in function for editing and additional recording while monitoring the playback of already recorded music.
In order to perform recording, it is necessary to arrange a plurality of recording or reproducing heads to record and reproduce at the same time, or to reproduce previously recorded contents of the track being recorded.

In order to realize such a function, as shown in FIG. 1, a generally considered method is to arrange a pre-play head 2 on the upstream side of the tape 1 running,
There is a method of providing the recording head 3 on the downstream side. Furthermore, downstream of the necessary recording head 3, there is a monitor reproduction head 4 for simultaneously checking the recording state during recording.
may be provided.

The signal detected by the advance playback head 2 is processed by the playback signal processing circuit 5 from the signal in the format recorded on the tape 1 through demodulation, noise absorption, error correction, etc., into a signal string containing only data without redundant parts. converted. 6 is an output terminal, and 8 is an input terminal. The switch 7 selects either the external input or the detection output of the preceding reproduction head 2 as the input to the recording head 3.
The output of the switch 7 is further delayed by a delay circuit 9 for a certain period of time, and then converted again into the recording signal format on the tape 1 by the recording signal circuit 10, and recorded on the tape 1 by the recording head 3. At this time, the elapsed travel time of the tape 1 from the advance playback head 2 to the recording head 3 is detected by the advance playback head 2, and is transferred to the recording head via the playback signal processing circuit 5, switch 7, delay circuit 9, and recording signal circuit 10. The delay circuit 9 is set so that the time delay is equal to the time delay of the signal reaching 3. Therefore, when punching in and out,
Alternatively, during electronic editing, if the recording head 3 is driven and the switch 7 is in the state shown in FIG.
written). In order to perform such an operation perfectly, the delay amount of the delay circuit 9 must be set accurately.

The distance between the advance reproducing head 2 and the recording head 3 depends on the mechanical installation accuracy, and there are differences from device to device. The method of increasing the accuracy of the mechanism design and eliminating the need for adjustment requires adjustment accuracy of about one sample word of data (although it cannot be generalized because the recording wavelength varies depending on the tape speed and tape format, it is 10 to 20 μm). It is difficult to achieve this accuracy due to the technical difficulty and cost increase factors, and it is desirable to adjust the delay amount of the delay circuit.

When overwriting the same signal using electronic editing or punch-in-out, the recording format on the tape requires that the newly recorded data be recorded at approximately the same position as the previously recorded data. More precisely, due to low flutter when the tape runs, it is not possible to re-record in exactly the same location.
However, this difference is absorbed during playback by the jitter absorbing memory. However, the positional relationship between the synchronization code and each data must be maintained as it is in the newly recorded data string. Otherwise, data continuity will not be maintained at the point where overwriting starts or ends, and not only data loss and duplication will occur, but the generation of error correction code combinations between frames or blocks will be disrupted, and errors will occur. If it gets too hot, you won't be able to make correct corrections. Therefore, the relationship between the frame or block synchronization code and the data position of the newly recorded portion must be the same as that of the already recorded portion. The reproduction signal processing circuit 5 removes redundant parts such as synchronization codes from the recording format on the tape 1,
Outputs a signal containing only data strings. In order to maintain the positional relationship between the synchronization code and the data as described above, conventionally, the processing time in the reproduced signal processing circuit 5 and the delay time in the delay circuit 9 have to be adjusted even for the synchronization code after the synchronization separation. It is necessary to delay the total amount, and this requires a memory with a large capacity equal to the amount of delay of the data signal and complicated operations.

The present invention solves these problems and provides a digital signal recording and reproducing apparatus that allows accurate setting of delay amount with a simple configuration and easy adjustment.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a reproduction signal processing circuit, 12 is a reproduction signal control circuit that supplies a clock to the reproduction signal processing circuit 11, and 13 is used for delaying a data signal. Random access memory (RAM), 14 is an address counter of the RAM 13, 15 is a preset means such as a switch that can set the count value of the address counter 14, that is, the amount of delay in the RAM 13, 16 is a recording signal processing circuit, and 17 is a recording signal processing circuit. A recording signal control circuit supplies a clock to the circuit 16, 18 is a presettable counter that can be preset, and 19 is presetting means such as a switch for setting the initial value of the counter 18.

FIG. 3 shows a tape pattern for explaining the operation of the above embodiment. A is a diagram of the tape pattern at time t=T as seen from the advance playback head 20, and B is a diagram of the tape pattern at time t=T' (T Recording head 2 at <T')
1 is a tape pattern diagram seen from 1, and the shaded area 22
indicates frame synchronization or block synchronization code.

Next, the operation of the above embodiment will be explained.

In electronic editing, etc., as described above, when editing connections are made by additional recording, the blanking section (or the frame section that does not contain data and consists only of error correction codes) that precedes the editing point is first The recording mode is switched to the recording mode (which may be used), and the same signal that has been recorded on the tape is then recorded again. At the editing point, a switch is made to the signal input to be connected for editing, and recording continues. Therefore, if the delay of the data signal cannot be properly obtained in accordance with the distance between the advance reproduction head and the recording head, the continuity of data at the recording mode switching point will be impaired. The reproduction signal processing circuit 11 shown in FIG. 2 demodulates the detection signal from the preceding reproduction head 20.
Synchronization is separated and jitter is absorbed by memory. Furthermore, operations such as correction and correction are performed to output a data signal that does not include redundant signals. The reproduced signal control circuit 12 supplies a timing block to the reproduced signal processing circuit 11, and also provides frame synchronization without jitter to the presettable counter 18.
Alternatively, a block synchronization signal is supplied, and further a bit clock and a word clock synchronized with data are supplied to the address counter 14 and presettable counter 18. The output signal of the reproduced signal processing circuit 11 is delayed by the RAM 13 according to the value preset by the switch 15 in units of data words. On the other hand, the frame synchronization or block synchronization signal serves as a load pulse for the presettable counter 18, and initializes the counter 18 to a value preset in units of data words by the switch 19. The presettable counter 18 counts the word pulse as a clock, and uses the carry output as a trigger pulse to control the recording signal control circuit 17.
Enter. The recording signal control circuit 17 initialized by the trigger pulse sends the output of the RAM 13 again to the recording signal processing circuit 16 to form a recording tape pattern signal by adding a synchronization signal, error correction, detection code, etc. Supplies timing clock.

When the series of operations described above are carried out as desired, as shown in FIG.
3 is applied to the recording head 21 at time t=T',
recorded on tape. The sample word 23 on the tape travels for a time Δt=T'-T and almost reaches the position of the recording head 21, although an error due to wow and flutter occurs. The synchronization signal is also delayed by the same amount. Synchronization signal 22 in Fig. 3 A and B
The relative positional relationship between the sample word 23 and the sample word 23 remains unchanged even after being re-recorded.

When this operation is fully executed, switch 15
Looking at the relationship between . That is, the presettable counter 18 and the address counter 14 are driven by a common synchronized clock pulse, and the presettable counter 18 is initialized by a frame synchronization or block synchronization signal synchronized with the data after jitter absorption. The sum of the delay time in the RAM 13 and the data delay time in the reproducing circuit 11 and the recording circuit 16 matches the delay time of the synchronizing signal from the load pulse input to the carry output in the presettable counter 18. Therefore, when adjusting the head when installing the head, if the set value of one switch is obtained by adjustment, the other value can be obtained by calculation.

Next, a specific method for adjusting the delay time with respect to the distance between heads will be described. As a method of adjusting the data signal delay time with an accuracy of about one sample,
One possible method is to monitor the analog output signal after D/A conversion and adjust it based on the phase difference, but this is not an easy method to achieve with high accuracy. On the other hand, matching using the phase of the synchronization signal is easy. Specifically, arbitrary signals are recorded on two channels simultaneously. At this time, the frame synchronization signals are recorded in the same phase. In this state, the tape is rewound once, and one channel is used as a reference, and the other channel is recorded while being monitored by the advance playback head. In accordance with the above embodiment, the value of the switch 19 in FIG.・Repeat playback.
Once the value of switch 19 is determined, the value of switch 15 is also determined by calculation. The delay time can be easily adjusted by the above adjustment method.

As described above, according to the present invention, when setting the signal delay amount according to the distance between the advance playback means and the recording means, which differs for each recording and playback device, it is possible to easily set the delay amount of the signal according to the distance between the advance playback means and the recording means, without using a particularly large capacity memory for the synchronization signal. The circuit configuration allows the relationship between the data and the synchronization signal to be kept constant, and the amount of delay can be set indirectly based on the delay amount of the synchronization signal, which itself can be easily adjusted. Work is also much easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a tape pattern diagram for explaining its operation. 11...Reproduction signal processing circuit, 12...Reproduction signal control circuit, 13...Random access memory, 1
4...Address counter, 15...Switch, 1
6... Recording signal processing circuit, 17... Recording signal control circuit, 18... Presettable counter, 19...
...Switch.

Claims (1)

[Claims] 1. Converting an analog signal into a digital signal, and recording and reproducing the digital signal by configuring a frame including an error detection/correction code and a synchronization code from a plurality of sample words, or further configuring a block from a plurality of frames. A digital signal recording and reproducing device that performs the following: a pre-reproducing means is provided at a position preceding the recording means, and a signal detected by the pre-reproducing means can be recorded again by the recording means via a delay means. In the apparatus, the delay means includes an address counter of the random access memory capable of setting a delay amount according to a distance between the random access memory for delaying the sample word, the recording means, and the advance reproduction means; a counter capable of giving a delay amount corresponding to a distance between the recording means and the preceding reproduction means to the frame synchronization code or block synchronization code detected by the advance reproduction means and from which time axis fluctuations have been removed; A digital signal recording and reproducing device comprising: