JPH0462509B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an imaging device using a solid-state imaging device.

(Prior Art) When a solid-state image sensor, such as a CCD (charge-coupled device), is used in a television camera, by changing the driving method of the solid-state image sensor, the field (or frame) time of the television signal can be improved. It has been proposed in the past that the accumulation time can be shortened.

For example, in a solid-state image sensor called a frame transfer type, the charge in the light receiving part that performs photoelectric conversion and charge accumulation is removed by vertical transfer once in the middle of the vertical period, and then the remaining vertical period is effectively The driving method that operates as the accumulation time is
For example, this is proposed in Japanese Patent Application No. 55-61098.

According to the above method, for example, in an NTSC TV camera, the accumulation time is usually 1/60 seconds, but this can be changed to 1/120 seconds, 1/500 seconds, etc., which allows for a large amount of light. It has the advantage of not having a small aperture even when it is incident, and preventing blurring of images of objects moving at high speed. However, when performing the above-mentioned operation, when eliminating the charge accumulated up to the middle of the vertical period without extracting it as a signal as described above, especially when the actual accumulation time is shortened, this elimination is The amount of charge becomes extremely large. For example, if the effective accumulation time t ₁ is 1/500 seconds, the ratio of the accumulation time t ₂ of the charge to be removed and t ₁ is t ₂ /t ₁ = (1/60−1/500)/1/500 ≒7.3, which is about 7.3 times, and assuming that the charge accumulated at t ₁ is at the standard level, at t ₂ it will be at the standard level.
7.3 times more charge is accumulated. When such a large amount of charge is accumulated, it is very difficult to eliminate it all so that it does not affect the actual accumulation time. In particular, the amount of charge generated in so-called highlight areas on the screen is extremely large, and when vertical transfer is performed to discharge charge in the middle of the vertical period, a large amount of charge remains and is output on the screen. There will be a negative impact on.

In addition, this remaining charge becomes 4 to 10 times the signal level (approximately the saturation signal level of the image sensor) at the output of the image sensor, causing an abnormal response of the signal processing circuit, or causing gain control or aperture control. This may cause malfunction.

Furthermore, an imaging device has been proposed in which charges in both the light receiving section and the storage section are removed during the vertical period. In this case, no output signal is obtained in the period before the intermediate transfer, and aperture control, gain control, etc. become inaccurate.

(Objective) It is an object of the present invention to propose a solid-state imaging device that can eliminate the drawbacks of the conventional example described above and at the same time eliminate the adverse effects on the screen when the substantial storage time is varied.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a frame transfer type CCD solid-state imaging device that can be applied to the present invention. 1
is a frame transfer type CCD solid-state image sensor,
2 is a light receiving section that photoelectrically converts incident light from an imaging optical system (not shown) and accumulates charge; 3 is a storage section that transfers the charge of light receiving section 2 and further reads it out every horizontal period; 4 is a storage section 3 is a horizontal register that horizontally transfers the charge transferred every horizontal period by φT, 5 is a charge-voltage converter that converts the charge from the horizontal register 4 into a voltage and outputs it, and DG is provided along the register 4. gate or barrier, DR is the overflow drain.

Figure 2a shows the drive waveform of the frame transfer CCD image sensor 1 in the short time mode, and φI
indicates the driving waveforms of the light receiving section 2, φS of the storage section 3, φT of the horizontal shift register section 4, and φR of the charge-voltage conversion section 5, respectively.

IV is the vertical period of the television signal, and _T2 is the effective accumulation period.

At the beginning of the vertical period, the charge in the light receiving section 2 is vertically transferred to the storage section 3 by the vertical transfer pulse shown in , and the charge is transferred to the horizontal register 4 one line per horizontal period by the subsequent pulse. The signal is horizontally transferred to the charge-voltage converter 5 by the pulse , where it is converted into a charge voltage by the pulse and taken out as an output.

After photoelectric conversion and charge accumulation in the light receiving section 2 during the T ₁ period, only the light receiving section is vertically transferred by the pulse, and the charges accumulated during the T ₁ period are removed from the light receiving section. Thereafter, the charges received and accumulated during the _T2 period are vertically transferred to the accumulation section 3 by the pulse. The following operations are similar to those described above.
In addition, in the standard mode in which the accumulation time is about one field period as shown in FIG. 2b, the pulses in FIG. 2 are omitted. Here, only the light receiving section 2 performs vertical transfer due to the pulse in the short time mode, and when eliminating the charge accumulated during the T ₁ period, T ₁ is compared with T ₂ .
Since the amount of charge accumulated in is large, it cannot be completely eliminated and remains.

FIG. 3 shows the output waveform of the image thus obtained.

Vsat is the saturated output voltage of the image sensor, Vav is the standard average output voltage of the image sensor, and T _BLK is the vertical blanking interval. As described above, the remaining charge that could not be eliminated in the vertical transfer before the actual accumulation period _T2 is output, and an output at the Vsat level is generated in the initial period _T3 of the vertical period. If T ₃ is short, it will not appear on the screen. But Vsat is Vav
Since it is very large, about 3 to 5 times as large as that of , it has a large influence on the signal processing circuit.

FIG. 4 shows a first embodiment of the present invention. 101
Reference numeral 102 includes a sample and hold circuit as a masking means for removing the clock signal from the output of the image sensor and converting a part of the video signal to a signal at a predetermined level; 102 includes a low-pass filter, a clamp circuit, a gamma circuit, and a clip circuit; Luminance signal Y including
Process circuit, 103 is sample hold circuit 1
01 is a color separation circuit that separates red R, blue B, and green G signals from the output; 104 is a color processing circuit that includes a low-pass filter for R, G, and B signals, a clamp circuit, a gamma circuit, a clip circuit, and a matrix circuit; , 105 is an encoder circuit that synthesizes a television signal using Y, R-Y, B-Y and synchronization signals, 1
06 is a synchronization signal generation circuit including a reference oscillation frequency divider and a decoder; 107 is a mode changeover switch for switching the operation mode of the synchronization signal generator 106; and 108 is a drive pulse for the image sensor from the output of the synchronization signal generator 106. This is a drive circuit.

The output of the image sensor 1 is sent to the sample hold circuit 10
1, the clock is removed and the signal is made continuous, and the Y process circuit 102 forms a luminance signal Y, which is input to the encoder 105. Further, the output of the sample and hold circuit 101 is separated into color components in the image signal by a color separation circuit 103 according to a pattern of a color separation filter (not shown) pasted on the image sensor 1, and the color components are separated into an R signal, a B signal, and a B signal. signal, G signal is formed. The color processing circuit 104 processes the R, G, and B signals, respectively, and further forms color difference signals RY and BY through matrix calculation. The encoder 105 inputs Y, RY,
By using B-Y and the synchronization signal from the synchronization signal generator 106, a television signal such as NTSC is formed and output. The mode changeover switch 107 is for the image sensor 1
Switch the operating mode to standard mode and short speed mode.

Figure 5 shows a timing chart.

In (a), vertical transfer is performed in the vertical blanking interval at φI in standard mode. (b) is _PSH in standard mode and occurs continuously in the video section. (c) shows φI in the short-second time mode, in which a vertical transfer pulse is generated in the middle of the video period to shorten the actual storage time. (d) is P _SH in the short seconds mode, and the video period is slightly longer than the time corresponding to T ₃ in Figure 3 (for example, 1
~ several horizontal periods) P _SH is stopped for a long time T ₄ .

Figure 6 shows the output of the 101 sample and hold circuit in short time mode. The charge that cannot be eliminated by T ₃ does not appear in the 101 sample and hold output,
This has the effect that there will be no adverse effects on subsequent circuits.

FIG. 7 shows the main part of the synchronization signal generation circuit 106. 201 is a crystal oscillator, 202 is a reference oscillator,
203 is a counter 1, 204 is an H pulse decoder, 205 is a counter 2, 206 is a V pulse decoder, 207 is a P _I switching circuit, and 208 is a P _SH
It is a switching circuit. When the 107 mode selector switch is set to "1", P _I and P _SH as shown in Figure 5 a and b are both generated from standard mode pulses I _N and SH _N , and set to "0".
When , P _{I and} P _SH as shown in Fig. 5c and d are generated from the short-second mode pulses I S and S _S .

FIG. 8 is a diagram showing a second embodiment of the present invention.

301 is an adder, and 302 is a character signal generation circuit. When the mode changeover switch 107 is on the standard mode side, the character signal generation circuit 302 does not operate, but when it is on the short speed side, the character signal generation circuit 302 operates and a character signal is generated, and the adder 301 Character data is mixed with the luminance signal. The character signal is configured to insert a character in period _T4 in FIG. 6 using a synchronizing pulse from the synchronizing signal generating circuit 106. The generated signal is not limited to a character signal, but may also be a symbol or the like.

(Effects) According to the present invention, even if the actual storage time of the image sensor is set short, the influence of unnecessary charges on the screen can be removed.

In the above embodiment, in the short time mode of the image sensor, only the light receiving section performs vertical transfer in the middle of the vertical period, but the charges in both the light receiving section and the storage section are eliminated in the middle of the vertical period. Even in this method, the present invention can be implemented since a part of the readout image becomes unsightly.

FIG. 9 is a diagram showing a second embodiment of the present invention, and shows a modification of the short time mode. In this embodiment, high-speed vertical transfer in the storage section is performed in synchronization with high-speed vertical transfer in the light receiving section. Therefore, the charges in the light receiving section and the storage section are collected in the horizontal shift register 4 and overflow occurs. This overflowed charge flows into the drain DR via the gate or barrier DG and is discharged.

Therefore, the output of the charge-voltage converter 5 is missing at the portion , resulting in an unsightly screen.

In addition, various types of image sensors such as interline CCDs, MOS image sensors, etc. that are capable of storage time control have been considered. For example, when controlling the storage time using an interline CCD, Since noise enters the screen at the rear of the vertical period, the video signal level in this area can be controlled to a predetermined level.

In the embodiment, the substantial accumulation time T ₂
is set constant, but may be configured to be variable in multiple stages or steplessly. In this configuration, the amount of charge that cannot be eliminated depends on T ₂ and increases as T ₂ becomes shorter, so T ₄ depends on the length of T ₂ .
may be configured to be variable.

Further, in the present invention, the mask means is configured to stop the operation of the sample and hold circuit, but a gate circuit may be provided before or after the sample and hold circuit to close the gate for the period _T4 . It also includes a switch circuit in which a part of the video signal is replaced with a signal pattern of another predetermined level.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the frame transfer type CCD, Figure 2 a is an explanatory diagram of the short-time mode, and Figure 2 b
3 is an explanatory diagram of the standard mode, FIG. 3 is an explanatory diagram of unnecessary signals in the short-time mode, FIG. 4 is a diagram illustrating a configuration example of the imaging device of the present invention, and FIG. 5 is a diagram of the tine of the first embodiment of the present invention. FIG. 6 is an output diagram of the sample hold circuit according to the first embodiment of the present invention, FIG. 7 is a configuration example diagram of the synchronizing signal generation circuit, FIG. 8 is a diagram of the second embodiment of the present invention, and FIG. The figure shows a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Imaging element, 101...Sample hold circuit, 106...Sync signal generator, 107...Mode change switch.

Claims (1)

[Scope of Claims] 1. An imaging device that photoelectrically converts imaging light from a subject to obtain a charge, an imaging means for obtaining a video signal based on the charge, a driving means for driving the imaging device, and the above-mentioned an accumulation time switching means for switching charge accumulation time in an image sensor; and a storage time switching means for switching charge accumulation time in an image sensor; and a superimposing means for superimposing a signal of a predetermined pattern including a character pattern on a specific portion, and the level setting by the superimposing means and the operating state of the driving means are respectively switched in conjunction with the operation of the accumulation time switching means. According to the present invention, when the accumulation time is switched by the accumulation time switching means, the signal of the predetermined pattern including the character pattern is superimposed on the specific portion of the video based on the video signal. An imaging device that uses 2. The imaging device according to claim 1, wherein the specific portion of the predetermined video signal includes a portion on which noise generated due to switching of the storage time switching means is superimposed.