JPH0461480A - Video signal take-in circuit - Google Patents

Abstract

PURPOSE:To fetch an object signal quickly by deviating a gate signal generating point increasingly and decreasingly in the unit of one line around a generating point of a gate signal generated at first when a fetched signal is not an object signal so as to generate a gate signal of a line for the object signal. CONSTITUTION:When a fetch discrimination circuit 3 discriminates it that a fetched signal is not an object signal, since an error signal NG is inverted to a high level, a frame pulse FD is used as an output signal NGCLK of an AND gate 14 and it is fed to a clock terminal CLOCK of a quinary counter 15. Then the gate signal generating point is deviated increasingly and decreasingly sequentially in the unit of one line around the position of a gate signal generated at first by means of a selector 13 to generate a gate signal by which the object specific signal is able to be extracted. Thus, the object signal is fetched in a short period of time.

Description

Detailed Description of the Invention "Industrial Application Field" The present invention relates to a video signal capture circuit suitable for application to a ghost removal device that captures a signal of a specific line from a video (No. 8) and processes it. Regarding.

"Prior Art" As is well known, in a video signal, signals different from video information (Specific No. 4G), such as a character signal and a ghost removal reference signal, are inserted in the vertical retrace period.

Video signal capture circuits for capturing and processing such specific signals have been proposed.

An example of the capture circuit will be explained with reference to FIG. 5 and the following figures.

In FIG. 5, 1 is, for example, a video detection circuit (not shown)
This input terminal is supplied with the video signal Vin output from the synchronous separator circuit 2 and the waveform capture discrimination circuit 3.

A gate signal GT is formed in a gate signal generation circuit 4 using the frame pulse FD and horizontal pulse HD separated by the synchronization separation circuit 2, and is supplied to the capture determination circuit 3.

The capture determination circuit 3 captures the video signal gated by the gate signal GT, and discriminates whether this signal is a desired specific signal. If it is not the desired signal, an error signal NG is sent to the gate 4R signal generation circuit 4. If it is a target specific signal, the specific signal VSg
is supplied from the captured signal output terminal 5 to various signal processing circuits (not shown).

FIG. 6 shows an example of a gate signal processing circuit, and FIGS. 7 and 8 are timing diagrams of each No. 43 when taking in the signal of line 100 of the input video signal ■in. .

In FIG. 6, the low toy No. 3 generator circuit 6 is
This is a circuit for generating a load signal to initialize the . The rear 98 signal RST supplied to the set input terminal SET is a signal that becomes high level for a short time when the power switch is turned on.

The frame pulse FD is input to the I terminal, and the horizontal pulse HD is input to the clock terminal CLOCK.

When the set input terminal SET is low, the output from the O#j child is also low, but when the set input terminal SET is reversed from high to low, the frame pulse FD inputted immediately after the set input terminal SET is reversed from high to low is output for one clock. minutes, the counter 7 outputs the load signal LOAD from the O terminal as shown in FIG.

Counter 7 is a counter that uses a horizontal pulse as a clock.
When the load signal LOAD becomes high, the initial value is read from the initial value setting circuit 8. In this example, the initial value is 4 as shown in FIG.

Then, counting continues from this initial value. Eventually -1
When the count is reached, the gate signal GT is output from the Q(K-11 terminal) as shown in FIG.

The counter 7 roughly continues counting, and when it counts 524, a high signal is supplied from the Q (524) terminal to the Am terminal of the select circuit 17 and the D terminal of the latch 16.

In Fig. 6, the select circuit 17 is a circuit that selects the reset signal RESET for Carantuff, and the output No. 18 from the Q (524) # child of the counter 7 is input to the A#1 child, and the same output No. 18 is input to the B# child. The output from the Q (524) terminal (a signal obtained by delaying the signal g by one line in the latch circuit 16) has been input.

The select terminal SEL of the select circuit ws17 has a low level error (since the g signal NG is not fully supplied, in this case, the input signal of the A terminal is outputted from the Y terminal.

That is, when the counter 7 counts 524, the select circuit 17 outputs the output signal from Q (524) of the counter 7 as the reset signal RESET.

The reset signal RESET is the reset signal R of the counter 7.
When input from ESET, the count value returns to O as shown in FIG. 7, and counting is repeated again from there. In other words, this counter is a 525-decimal counter.

Here, if the frame pulse FD is disturbed due to the influence of ghost etc. and the gate signal GT shifts to the 11th line as shown in FIG. The signal is determined to be unintended and the error signal NO goes high.

When the select terminal SEL of the select circuit 17 becomes high, the input signal No. 8 to the B terminal is supplied as the reset signal RESET of the counter 7 from the Y terminal as shown in FIG. Then, the count number of Carantuff returns to O is 1
Since there is a clock delay, the counter that normally operates in 525 decimal format operates as a 526 decimal counter in this case.

Therefore, in the next frame which is incorrectly captured, the gate signal GT is delayed by one line, that is, the gate signal GT is generated on the first line.

Since the signal captured by the gate signal GT is the target signal, the error signal NG from the capture discrimination circuit 3 becomes low, and the output of the select circuit 17 becomes A again.
You can switch to input from the terminal. As a result, the counter 7 becomes a 525-base counter as before, and thereafter a gate signal is always generated on the 1st line.

"Problem to be Solved by the Invention" In the conventional method, when the vertical synchronization signal (or frame pulse) is disturbed due to ghosts, etc., in order to match the target signal to a certain line, one direction (for example, rearward) is sent line by line. Since the signal was being shifted in the opposite direction, if the target signal was in the opposite direction, it had to be shifted by about one frame, which took a considerable amount of time.

In addition, in anticipation of this, it is possible to generate gate No. 45 several lines before the target signal line after starting gate No. 45, but in that case, it will take time to match the gate signal when the frame pulse is correctly output. Oops.

This invention solves the above problems.

"Means for Solving the Problem" In order to solve the above-mentioned problem M, the present invention includes a synchronization separation means for separating a synchronization signal from an input video signal, and a gate signal of a specific line by counting horizontal synchronization signals. means for generating the gate signal, a means for successively connecting a plurality of gate signals and sequentially delaying the gate signal one line at a time, and a means for sequentially delaying the gate signal by one line at a time; The gate No. 45 comprises a selection means for making a gate signal for taking in the specific signal inserted therein, and a means for determining whether the specific signal extracted by the gate signal is the specific signal for the purpose. When the signal extracted by the above is not the desired specific signal, the gate can extract the desired specific signal by sequentially shifting one line back and forth around the position of the first gate signal generated by the selection means. (It is characterized by generating No. 5.

"Function" If the captured signal is not the desired signal, the gate signal is shifted forward or backward in units of one line with the position of the first gate signal generated as the center (see gate signal GT in Figure 3).
The shift convergence is increased to generate a gate signal for the target signal line.

Embodiment Next, a video signal capture circuit according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

The overall configuration of the video No. 45 capture circuit is the same as the conventional example, so a description thereof will be omitted.

FIG. 1 shows a specific example of the gate signal generation circuit 4 when taking in the first line of the input video signal Vin, and FIG. 3 is a timing diagram of various signals in the configuration.

In FIG. 1, the quirk 98 signal RST, which goes high for a short time when the power switch is turned on, is supplied to the set input terminal SET of the load signal generation circuit 6 and the reset input terminal RESET of the quinary counter 15. .

When the high level set signal RST is completely supplied to the reset terminal RESET of the quinary counter 15, the counter 15
is reset and the output signals QA, QB.

All QCs are low.

As described above, the load signal generation circuit 6 is a circuit for generating a load signal for initializing the carantuff.

When the load signal is at a high level, the counter 7 reads the initial value (4 in this example) from the initial value setting circuit j88, and
Counting continues from this initial value. When the count reaches -3, a pulse QO is output from the Q (K-31 terminal) as shown in FIG.

'c T, 524 count Sult Q (524) High level reset signal RESET from fvi child to counter 7
is supplied to the reset terminal RESET. Therefore, this counter 7 becomes a 525-decimal counter.

Output from Q (K-3) terminal of counter 7 (ε QO
are delayed by l lines by latch circuits 9, 10, 11, and 12 respectively. Q2. Q3. Q4 (Fig. 3).
Q11 goes to C terminal, Q2 (No. 8 goes to A:4 child, Q3
(No. 8 is input to the B terminal, and Q4. signal is input to the D terminal.

The output signals QA, QB, and QC of the quinary counter 15 are outputted to the selectors 13, Sl, S2 . The selector 13 is controlled as shown in FIG. 2 by the states of these QA, QB, and QC signals.

That is, the reset signal R5T causes the quinary counter 1 to
5 is reset and all of the QA-QC (no. 8) become low level "0", the Y terminal of the selector 13 outputs the Am child's Q2 (no. 8 as the gate No. 4g GT) as shown in Figure 2. Ru.

No. Q22 is the QO defect signal output from the Q (K-) terminal of the counter 7 delayed by two lines as shown in Figure 3, so it is a signal that becomes high level on the 1st line of the input video signal Vin. .

Here, if G1-(g@GT is output accurately, a low-level error signal N
G is output. Therefore, since the output signal NGCLK of the AND gate 14 is also supplied to the clock terminal CLOCK of the quinary counter 15 while remaining low, the quinary counter 15 does not start counting. Therefore, the output signals QA, QB, QC
remains at a low level, and 02 (No. 8 is always output as a gate (No. g GT) from the Y terminal of the selector 13 (FIG. 3).

Next, a case will be considered in which the frame pulse FD is disturbed and the gate signal GT is shifted due to the influence of a ghost or the like. FIG. 4 shows various timing charts at that time.

When the capture determination circuit 3 determines that the captured signal is not the desired signal, the error signal NG is inverted to high level, so the frame pulse FD becomes the output signal NGCLK of the AND gate 14, and this becomes the output signal NGCLK of the quinary counter 15. It is supplied to the clock terminal CLOCK.

First, as shown in FIG. 4(I), since the quinary counter 15 is reset at reset No. 4g RST, the output signal Q
A, QB, and QC are all low. Therefore, Q22 is output from the Y#I terminal of the selector 13 as the gate signal GT.

If the signal taken in by the gate signal GT is not the desired signal, the error signal NG remains at a high level, so the next frame pulse FD causes the 53Ik counter 15 to be output signal Q
A becomes high. Therefore, from the Y terminal of the selector 13, Q33, which is delayed by one line from the 02 signal, can be output as the gate signal GT.

Similarly, if the signal taken in by the gate signal GT is not the desired signal, the signal Q1 one line before No. Q22 becomes the next gate signal GT, as shown in FIG. 4(II).

Roughly speaking, if the error signal NG remains at a high level, the next gate signal GTL is activated as shown in FIGS. 4(IV) and (V).
The signal Q4 is two lines after the tQ2 signal, and the next signal is the signal QO two lines before.

In other words, as can be seen from FIG. 4, the gate signal GT
are generated before and after the signal Q2, which becomes the correct gate signal when the frame pulse FD is accurately generated,
When the target signal cannot be acquired, it will gradually move away from the center.

Then, when the gate signal GT is generated on the first line, since the signal to be captured is the target signal, the error signal NG from the capture discrimination circuit 3 becomes low level, so the counter 15 stops counting and the output of the selector 13 changes. Fix it. Therefore, after that, the gate signal GT is always applied to the first line.
will begin to occur.

In the embodiment described above, four latch circuits are used, and the gate signal GT is generated for two lines before and after the center line. must be adjusted.

Although the above-described embodiment shows a case in which one line of gate signals GT is generated in one frame, the present invention can be similarly applied to a case in which a number of lines of gate signals GT are generated in one frame.

Although a frame pulse is used as the load signal LOAD of the counter 7, a vertical synchronization signal or the like may be used instead.

Further, although the quinary counter 15 is used to select the gate signal by the selector 13, the present invention can be similarly applied by controlling with a CPU or the like instead.

"Effects of the Invention" As explained above, according to the present invention, a gate signal can be immediately generated on a line into which a target signal has been inserted, despite disturbances in the vertical synchronization signal (or frame pulse) due to ghosts, etc. be able to.

Therefore, since the target 4F signal can be captured in a short time, the present invention is suitable for application to the circuit system for extracting the above-mentioned ghost removal reference signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for capturing a video signal according to the present invention, FIG. 2 is a truth table of a selector, and FIGS. 3 and 4 are waveform diagrams for explaining the operation of gate signal generation.
FIG. 5 is a block diagram of a video signal capture circuit, FIG. 6 is a block diagram of a gate signal generation circuit used therein, and FIGS. 7 and 8 are waveform diagrams for explaining its operation. 2...Synchronization separation circuit 3...Intake discrimination circuit 4...Gate signal generation circuit 6...Load signal generation circuit 7...Counter 8...Initial value setting circuit 9.10, 11.12 ... Latch circuit 13 ... Selector 14 ... AND gate 15 ... Quintal counter 17 ... Select circuit

Claims (1)

[Claims] (1) A synchronization separating means for separating a synchronizing signal from an input video signal, and a means for counting horizontal synchronizing signals to generate a gate signal for a specific line. means for sequentially delaying each gate signal; a selection means for selecting one gate signal from among the gate signals respectively delayed and selecting this as a gate signal for taking in a specific signal inserted into a specific line; It serves as a means for determining whether the specific signal extracted by the gate signal is the desired specific signal, and when the signal extracted by the gate signal is not the desired specific signal, the selection means first generates the signal. A video signal capture circuit characterized in that the gate signal is generated by sequentially shifting one line back and forth around the position of the gate signal so as to extract a target specific signal.