JPH0455029B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver suitable for application to, for example, a television receiver in which display with twice the field frequency is performed.

BACKGROUND TECHNOLOGY AND PROBLEMS The current television system uses a scanning method called interlace. That is, 1
A single image (frame) is transmitted by two vertical scans (fields), and the aim is to increase the number of scanning lines as much as possible without causing flicker to the viewer's eyes in a limited frequency band. It was designed to do this.

However, in the CCIR system mainly used in Europe, the field frequency is 50Hz, and flickering cannot be completely eliminated at this frequency, and flickering can be felt, especially on screens with high brightness.

Therefore, conventionally, a television receiver has been proposed in which the field frequency is doubled. FIG. 1 shows an example.

In the figure, 1 is an antenna, 2 is a tuner,
3 is an intermediate frequency amplifier, and 4 is a video detection circuit.
From the video detection circuit 4, a video signal S _V of 625 lines/50 fields, 2:1 interlaced format, for example, is obtained.

This video signal S _V is converted into a digital signal by an A/D converter 5, and then supplied to a conversion circuit 6 to be converted into a field double speed video signal whose field frequency is doubled.

The conversion circuit 6 includes field memories (random access memories having a storage capacity for pixels of one field period (1V)) 6a and 6b, and switch circuits 6c and 6d. switch circuit 6
c is switched to the memory 6a and 6b side every 1V,
On the other hand, the switch circuit 6d is switched to the opposite side. Further, the memory selected by the switch circuit 6c is supplied with a write clock pulse having the above-mentioned pixel timing, and the memory selected by the switch circuit 6d is supplied with a read clock pulse of twice the frequency. be done.

The video signal S _V converted into a digital signal by the A/D converter 5 is supplied to the memories 6 a and 6 b for 1 field every 1 V via the switch circuit 6 c and is written to the memories 6 b and 6 a. One field's worth of video signal written to the immediately preceding 1V is read out twice in succession with a period of 1/2V, and this is obtained via the switch circuit 6d. In other words, a double-speed field video signal S _V ' whose field frequency is doubled is obtained from this switch circuit 6d.

This video signal S _V ' is converted into an analog signal by a D/A converter 7 and then supplied to a signal processing circuit 8. Red, green, and blue primary color signals R, G, and B are obtained from this signal processing circuit 8 and supplied to the picture tube 9, respectively.

In addition, a video signal obtained from the video detection circuit 4
_SV is supplied to the vertical synchronization separation circuit 10. The vertical synchronizing signal P _V obtained from this separation circuit 10 is
The signal is doubled by a multiplier 11 to produce a signal with twice the frequency, and this signal is supplied to a deflection coil 13 through a vertical deflection circuit 12.

In addition, the video signal obtained from the D/A converter 7
S _V ' is supplied to the horizontal sync separation circuit 14. The horizontal synchronizing signal P _H ′ (having twice the normal frequency) obtained from this separation circuit 14 is sent to the horizontal deflection circuit 15.
It is supplied to the deflection coil 13 through.

The example shown in FIG.
Since G and B are supplied and horizontal and vertical deflection scanning is performed at twice the speed, the picture tube 9 displays a color image at twice the field frequency. Therefore, even in the CCIR method mentioned above,
The field frequency is doubled to 100Hz, so you won't notice any flickering.

However, in the case of the example shown in FIG. 1, there is a disadvantage that the horizontal synchronization of the video signal S _V ' obtained from the conversion circuit 6 is periodically disrupted, causing distortion in the upper part of the screen.

That is, the video signal obtained from the video detection circuit 4
The write state of S _V to the memories 6a and 6b is represented as shown in FIG. 2A. F ₁ and F ₂ indicate the first and second fields, respectively. The video signal S _V ' from the conversion circuit 6 is expressed as shown in FIG. 2B. In the figure, the arrow indicates the position of the vertical synchronization signal. As is clear from FIG. 2B, the horizontal synchronization phase of the video signal S _V ' shifts by 180 degrees every two fields, that is, every 1/50 second (indicated by the dashed arrow), and this causes the screen This disrupts the synchronization at the top and causes image distortion.

Therefore, the present applicant has previously proposed a method that does not cause such image distortion. FIG. 3 shows an example. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, the video signal S _V obtained from the video detection circuit 4 is converted into a digital signal by the A/D converter 5, and then converted into a field double-speed video signal whose field frequency is doubled. is supplied to the conversion circuit 16.

The conversion circuit 16 includes field memories (random access memories) 16a and 16b, each having a storage capacity for pixels of 313 horizontal periods (313H) and 312 horizontal periods (312H), and switch circuits 16c and 16d. The switch circuit 16 is alternately switched 313H to the memory 16a side and 312H to the memory 16b side. On the other hand, the switch circuit 16
d is switched to the opposite side. Switching control of these switch circuits 16c and 16d is performed by a control circuit 17. This control circuit 17 includes a synchronization separation circuit 1 from the video signal S _V.
Horizontal and vertical synchronization signals P _H and P _V separated by 8
is supplied.

The memory selected by the switch circuit 16c is supplied with the write clock pulse at the pixel timing described above, and the memory selected by the switch circuit 16c
The memory selected at d is supplied with a read clock pulse having twice the frequency.

The video signal S _V converted into a digital signal by the A/D converter 5 is supplied to the memories 16a and 16b via the switch circuit 16c, and is alternately written by 313H and 312H, respectively. Figure 4A is
It shows the write state of the memories 16a and 16b, and F ₁ and F ₂ indicate the first and second fields. In addition, the other memory 16b and 1
From 6a, the video signals written in the previous 312H and 313H are read out twice in succession, and this is sent to the switch circuit 16 as the field double speed video signal S _V ^* .
Obtained from d. Figure 4B shows the switch circuit 16d.
This shows the video signal S _V ^* obtained from the above, and the same reference numerals are attached to the field portions corresponding to those in FIG. By the way, due to the difference between the writing time and the reading time, the video signal S _V ^* has an excess or omission of one line per field.

In FIG. 4B, for example, in the portion of the F ₁ and F ₁ fields (the portion read from the memory 16a), line 313 is not read out due to time constraints. Further, for example, in the F ₂ and F ₂ field portion (read portion from the memory 16b), 1
There is a shortage of video signals for one line, reading is stopped during that time, and one line of video signals is missing (as shown by a dashed line). Such excess or lack of video signals occurs during the vertical blanking period, and does not cause any problem on the actual screen.

Writing to the above memories 16a and 16b,
Reading is controlled by control circuit 17.

Video signal S _V ^* obtained from switch circuit 16d
is converted into an analog signal by the D/A converter 7 and then supplied to the signal processing circuit 8. Then, from this signal processing circuit 8, red, edge and blue primary color signals R, G
and B are obtained and supplied to the picture tube 9, respectively.

In addition, from the control circuit 17,
The vertical synchronization signal P _V ^* is generated at the timing indicated by the arrow. i.e. the start of the first F ₁ field,
312 lines after this, i.e. the start of the second F ₁ field, 311.5 lines after this, 313 lines after this, 313.5 lines after this, i.e. the first F ₁
The vertical synchronization signal P _V ^* is generated at the start of the field and at similar timing thereafter. This synchronizing signal P _V ^* is supplied to the deflection coil 13 through the vertical deflection circuit 12, and vertical deflection scanning is performed. By generating the synchronization signal P _V ^* at the timing mentioned above,
Scanning lines are formed at the same position between the F ₁ fields and between the F ₂ fields, and the scanning lines formed in the F ₁ field and the F ₂ field are shifted by a 1/2 scanning line interval. That is, the video signal
It is said that the interlace relationship of _SV is maintained as is.

In addition, the video signal obtained from the D/A converter 7
S _V ^* is supplied to the horizontal synchronization separation circuit 14 . A horizontal synchronizing signal obtained from this separation circuit 14
P _H ^* (having twice the normal frequency) is supplied to the deflection coil 13 through the horizontal deflection circuit 15, and horizontal deflection scanning is performed.

According to the example in FIG. 3, the horizontal synchronization of the video signal S _V ^* is continuous as shown in FIG. 4B,
Therefore, there is no synchronization disturbance due to discontinuity of horizontal synchronization as in the example of FIG. 1, and no image distortion occurs due to this.

By the way, let us consider a case where a still display is performed in the example shown in FIG.

When performing this still display, the switching positions of the switch circuits 16c and 16d are fixed starting from a certain field, and the video signal of the same field is repeatedly read out from one of the memories in the read state.

For example, switch circuits 16c and 16d are switched to memories 16b and 16a, respectively, and memory 1
When 6b and 16a are fixed in the write and read states, respectively, as shown in FIG. 5B,
The video signal of the F ₁ field is repeatedly read out from the memory 16a, and therefore, the conversion circuit 16 obtains a double-speed field video signal S _V ^* based only on the video signal of a certain F ₁ field. Therefore, the picture tube 9 displays a still image based on the video signal of a certain _F1 field. Furthermore, in this state, the video signal S _V is always written to the memory 16b. FIG. 5A shows this writing state. In this case, since the memory 16b has a capacity of 312H, there will be a capacity shortage of 1H for every other field, but this is not a problem since no new written data is required for still display.

Next, for example, when the switch circuits 16c and 16d are switched to the memories 16a and 16b, respectively, and the memories 16a and 16b are fixed in the writing and reading states, respectively, as shown in FIG. 6B, the F ₂ The field video signal is repeatedly read out, and therefore, the conversion circuit 16 obtains a field double-speed video signal S _V ^* based only on the video signal of a certain F ₂ field. Therefore, the picture tube 9 displays a still image based on the video signal of a certain _F2 field. In addition, in this state, the video signal S _V is always written to the memory 1.
6a. FIG. 6A shows this writing state. In this case, the memory 16a is
Since it is 313H minutes, there will be 1H worth of data missing every other field, but this is not a problem.

By the way, even in the still display described above, the vertical synchronization signal P _V ^* is generated at the same timing as during normal playback (see Figures 4B, 5B, and 6).
(See the arrow in FIG. B), the displayed still image is an interlaced display in which scanning lines of the same signal are formed with a 1/2 scanning line interval. Therefore, there is a drawback that step-like distortions, so-called "jags", are noticeable in the shaded areas, impairing visibility. This "serration" is described in detail in an earlier application (Japanese Patent Application No. 58-23998) by the present applicant.

Purpose of the Invention In view of the above, the present invention is designed to prevent the above-mentioned "jags" from occurring during still display.

Summary of the Invention In order to achieve the above object, the present invention synchronizes a vertical synchronizing signal with the start position of output data from a field memory during still display, so that scanning lines by the same signal are formed at the same position. It is something.

Embodiment An embodiment of the present invention will be described below with reference to FIG. In FIG. 7, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, a horizontal synchronizing signal P _H and a vertical synchronizing signal P _V obtained from a synchronizing separation circuit 18 are supplied to a clock pulse generator 19, respectively. This generator 19 generates a write clock pulse of a predetermined frequency, for example 3/16 fsc (fsc is the color subcarrier frequency).
WCK is obtained and supplied to the clock terminal CK of the write address counter 20. Also,
A read clock pulse RCK of twice the frequency of the clock pulse WCK, for example 3/8 fsc, is obtained from the generator 19 and is supplied to the clock terminal CK of the read address counter 21.

Further, the generator 19 outputs a predetermined frequency, for example,
3fsc master clock pulse MCK is obtained,
This is supplied to the signal generation circuit 22. Further, the signal generation circuit 22 is supplied with synchronization signals P _H and P _V from the synchronization separation circuit 18 . The signal generating circuit 22 also receives a still display signal from a terminal 23.
S _CS is supplied. This signal generation circuit 2
From 2, the clear signal for counters 20 and 21
WCLR and RCLR, vertical synchronization signal P _V ^* , and switching control signals S ₁ and S ₂ for switch circuits 16c and 16d are obtained.

FIG. 8 shows an example of this signal generation circuit 22.

In the figure, synchronization signals P _V (shown in FIG. 9A) and P _H (shown in FIG. 9B) from the synchronization separation circuit 18 are shown.
is supplied to the phase adjustment circuit 24. From this phase adjustment circuit 24, a vertical synchronizing signal P _V ' (shown in FIG. 9C) is obtained which is sequentially generated every 313H and 312H. This vertical synchronization signal P _V ' is used as a clear signal WCLR of the write address counter 20.

Further, this vertical synchronizing signal P _V ' is supplied to the clear terminal CLR of the counter 25, and its clock terminal
A horizontal synchronizing signal P _H is supplied to CK. and,
The output of this counter 25 is the detection circuit 26 of 313H.
supplied to Therefore, from this detection circuit 26,
A signal 1/2 P _V ' (illustrated in FIG. 9D) is obtained for each start of 314H.

This signal 1/2 P _V ' is supplied to the clear terminal CLR of the counter 27, and its clock terminal CK is supplied with the horizontal synchronizing signal _PH .

The output of this counter 27 is the OH detection circuit 2
8, 156H detection circuit 29, 311H detection circuit 30 and
The signal is supplied to the 468H detection circuit 31. Detection circuit 28
The outputs of 29 and 29 are supplied to an OR circuit 32. In addition, the outputs of the detection circuits 30 and 31 are 0.75H, respectively.
and delay lines 33 and 34 having a delay amount of 0.25H.
The signal is supplied to the OR circuit 32 via the OR circuit 32. delay line 33
and 34 are supplied with a master clock pulse MCK as a clock pulse. Eventually, signals are generated from the OR circuit 32 at timings of 0H, 156H, 311.75H, and 468.25H from the timing of the signal 1/2 P _V ', and these are the vertical synchronization signal P _V ^* (shown in FIG. 9F). be done.

In addition, the output of the counter 27 is the 0H detection circuit 3.
5. 156H detection circuit 36, 312H detection circuit 37 and
The signal is supplied to the 468H detection circuit 38. Detection circuit 35
The outputs of 37 to 37 are supplied to an OR circuit 39. Further, the output of the detection circuit 38 is supplied to an OR circuit 39 via a delay line 40 having a delay amount of 0.5H. A master clock pulse MCK is supplied to the delay line 40 as a clock pulse. As a result, signals are generated from the OR circuit 39 at timings of 0H, 156H, 312H, and 468.5H from the timing of the signal /2P _V ', and these are used as the clear signal RCLR of the read address counter 21 (shown in FIG. 9E). be done.

Further, in FIG. 8, 41 is a toggle circuit to which the vertical synchronizing signal P _V ' from the phase adjustment circuit 24 is supplied. Further, the signal 1/2 P _V ' is supplied to this toggle circuit 41 as a reset signal. Further, the toggle circuit 41 is supplied with a still display signal S _CS . When the still display signal S _CS is not supplied, the toggle circuit 41 performs a toggle operation based on the vertical synchronization signal P _V ′, and the output side of the toggle circuit 41 receives switching control signals S ₁ (see FIG. 9G) and S ₂ ( (see FIG. 9H) is obtained. On the other hand, when the still display signal S _CS is supplied, the toggle operation is stopped and the switching control signals S ₁ and S ₂ are maintained at predetermined states. For example, if the signal S _CS is supplied at time t ₁ , then S ₁
and _S2 maintain the state of high level "1" and low level "0", respectively, as shown by broken lines in FIGS. 9G and 9H.

Returning to FIG. 7, the switching control signals S ₁ and S ₂ are as follows:
They are supplied to switch circuits 16c and 16d, respectively. When the switching control signals S ₁ and S ₂ are at high level "1", they are switched to the memory 16a side, respectively,
On the other hand, when the low level is "0", each is switched to the memory 16b side. That is, the switch circuit 16c is
313H on the memory 16a side, 312H on the memory 16b side
switch circuit 1.
6d is switched to the opposite side. The memory to which the switch circuit 16c is switched is placed in a writing state, while the memory to which the switch circuit 16d is switched is placed in a reading state.

Further, the clear signals WCLR and RCLR obtained from the signal generation circuit 22 are sent to the counters 2 and 21, respectively.
is supplied to the clear terminal CLR. counter 20
The write address W _AD and the read address R _AD from 21 and 21 are supplied to the memories 16a and 16b via an address switching circuit 42, respectively. In this case, by switching the address switching circuit 42, the write address W _AD is supplied to the memory 16a and 16b in the write state, and the read address R _AD is supplied to the memory 16a and 16b in the read state.
Note that since the read clock pulse RCK has twice the frequency of the write clock pulse WCK, reading from the memories 16a and 16b is performed at twice the writing speed.

Further, the vertical synchronizing signal R _V ^* obtained from the signal generation circuit 22 is applied to one fixed terminal 4 of the changeover switch 43.
3a, and a clear signal RCLR is supplied to the other fixed terminal 43b. A still display signal S _CS is supplied to this changeover switch 43, and the switch is switched to the terminal 43b side for still display and to the terminal 43a side for normal display. The signal from this changeover switch 43 is transmitted to the vertical deflection circuit 1.
2.

This example is configured as described above, and its operation will be explained below.

First, during normal display in which the still display signal S _CS is not supplied, the video signal S _V converted into a digital signal by the A/D converter 5 is sent to the switch circuit 16c.
are supplied to memories 16a and 16b via
313H minutes and 312H minutes are written alternately, respectively (see FIG. 4A). In addition, the video signals written in the immediately preceding 312H and 313H are read out twice from the other memory 16b and 16a into the memories 16b and 16a, which are written in one of them, and this is the field double-speed video signal S _V ^* (See FIG. 4B) is obtained from the switch circuit 16d. At this time, a vertical synchronizing signal P _V ^* is supplied to the vertical deflection circuit 12 via a changeover switch 43. This vertical synchronization signal P _V ^* starts from the start of the first F ₁ field, 312 lines (156H) after this, 311.5 lines (155.75H) after this, 313 lines (156.5H) from this
This was generated 313.5 lines (156.75H) after this, that is, at the start of the first F ₁ field (see the arrow in FIG. 4B and FIG. 9F). Therefore, during normal display, scanning lines are formed at the same position between the F ₁ fields and between the F ₂ fields, and the scanning lines formed in the F ₁ field and the F ₂ field are each 1/2 scanning line. It is made to shift by the interval. That is, an image is displayed in which the interlace relationship of the video signal S _V is maintained as it is and the field frequency is doubled.

Next, during still display when the still display signal S _CS is supplied, the switching control signals S ₁ and S ₂ are maintained at predetermined states. For example, switching control signal S ₁
Consider the case where S 2 and S ₂ are set to "0" and "1", respectively. At this time, the switch circuits 16c and 16d are switched to the memories 16b and 16a, respectively, and the memories 16b and 16a are placed in a write state and a read state, respectively. Figure 10A shows the writing state at this time, and Figure 10B shows the field double-speed video signal S _V ^* obtained from the switch circuit 16d, which is obtained only from the video signal of the _F1 field. . At this time, the clear signal RCLR is supplied to the vertical deflection circuit 12 via the changeover switch 43 as a vertical synchronizing signal.
This clear signal RCLR corresponds to the start timing of each field, as shown by the arrow in FIG.
It is generated at the timing of the head position of the output data from the memory 16a. Therefore, in this case, a still image based on the video signal of the _F1 field is displayed, and the scanning lines of each field are formed at the same position, so that interlaced display is not performed. That is, scanning lines using the same signal are formed at the same position.

For example, consider a case where the switching control signals S ₁ and S ₂ are set to "1" and "0", respectively.
At this time, the switch circuits 16c and 16d are switched to the memories 16a and 16b, respectively, and the memories 16a and 16b are placed in a write state and a read state, respectively. FIG. 11A shows the write state at this time, and FIG. 11B shows the switch circuit 16.
This shows the field double-speed video signal S _V ^* obtained from d, which is obtained from only the F ₂ field. Also at this time, the vertical deflection circuit 12 is supplied with a clear signal RCLR (FIG. 11B) which is generated at the start timing of each field via the changeover switch 43.
) is supplied as a vertical synchronization signal. Therefore, in this case, a still image is displayed based on the video signal of the _F2 field, and moreover, the scanning lines of each field are formed at the same position, and no interlaced display is performed.

According to this example, when displaying still images, the scanning lines of each field are formed at the same position, that is, the scanning lines of the same signal are formed at the same position and are not interlaced. , so-called "jags" do not occur.

Effects of the Invention According to the present invention described above, the vertical synchronization signal is synchronized with the leading position of output data from the field memory during still display, so that scanning lines by the same signal are formed at the same position. Therefore, interlaced display is not performed during still display, and therefore, there is no step-like distortion, or so-called "jaggies", in the shaded area, which impairs visibility.

[Brief explanation of the drawing]

Figures 1 and 3 are configuration diagrams of the conventional example, respectively.
4 to 6 are diagrams for explaining conventional examples, FIG. 7 is a configuration diagram showing an embodiment of the present invention, FIG. 8 is a specific configuration diagram of the main part, and FIG. 9 - FIG. 11 are diagrams for explaining one embodiment, respectively. 4 is a video detection circuit, 9 is a picture tube, 16 is a conversion circuit, 18 is a synchronization separation circuit, 19 is a clock pulse generator, 20 and 21 are write and read address counters, respectively, 22 is a signal generation circuit, 42
is an address switching circuit, and 43 is a changeover switch.

Claims (1)

[Scope of Claims] 1. A television receiver configured to receive an interlaced video signal, convert the field frequency of the video signal using a field memory, and then supply the field frequency of the video signal to a picture tube. A sync separation circuit that supplies a signal to separate horizontal and vertical sync signals; and 1 frame of the received video signal is divided into integer lines, respectively, based on the horizontal and vertical sync signals output from the sync separation circuit. Each field is divided into multiple fields and written to the above field memory, and the 1 field written to the above field memory is
If the frame worth of video signals is read out multiple times in succession for each of the above fields at multiple times the writing speed, and the two continuously read out field signals are based on the same field signal, this is not applicable. Controlling the vertical deflection of the picture tube so that the scanning lines based on the field signals are formed at the same position, and when based on different field signals, the scanning lines based on the field signals are formed shifted by a predetermined amount so as to perform interlacing. A control circuit for controlling writing and reading of the field memory is provided so as to generate a vertical synchronization signal with a timing such that the vertical synchronization signal is generated at the beginning of the data read from the field memory during still display. A television receiver characterized in that it is controlled by the control circuit described above so as to be synchronized with the position.