JPH0449197B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention is a static type transistor composed of MOSFETs (insulated gate field effect transistors).
Regarding RAM (Random Access Memory).

Prior to this invention, a method of equalizing the data line D using an n-channel MOSFET in a MOS static RAM using a positive power supply voltage +V _CC was considered. This equalization refers to making the potentials of the data line D equal when reading from the memory cell to the data line D.
Such an operation prevents a time delay when reading data that is inverted from the level of the data line D in the previous operation cycle from the memory cell, thereby realizing high-speed operation. However, when using the above positive power supply voltage (usually +5 volts) V _CC , the efficiency of short-circuiting both data lines D using an n-channel MOSFET is extremely poor due to the following reasons. was revealed through research by the inventor of the present application.

Generally, the signal level of data line D is set to about 3 to 3.5 volts. Therefore, even if an on-voltage of 5 volts is applied to the gate of an n-channel MOSFET, the gate-source voltage V _GS is as small as about 1.5 volts, so its on-resistance becomes relatively large, and in a short period of time It is practically impossible to equalize the levels between the data lines D and the effect thereof is small.

The object of the present invention is to provide a MOS static type RAM that improves the effect of equalization and speeds up read operations.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1A shows a MOS static RAM (hereinafter referred to as S-RAM) to which the present invention is applied.
A block diagram is shown.

This figure shows the internal configuration of an S-RAM integrated circuit (hereinafter referred to as IC) with a storage capacity of 16k bits and an output of 1 bit.

Each 16k bit memory cell has 128 columns (rows) x 32 rows (columns) = 4096 bits (4k bits)
It consists of four matrices (memory arrays M-ARY1 to M-ARY4) with a storage capacity of
They are arranged separately.

Row address selection lines (word lines WL1~
WL128, WR1 to WR128) have ²⁸ signals obtained based on the address signals A0 to _A5 , _A12 to _{A13 .}
= 256 decoded output signals are row decoder R
- Sent from DCR.

In this way, the memory of each matrix -M-
CEL is word line WL1~WL128, WR1~WR
128 and any one of complementary data line pairs D11, 11 to D132, 132, which will be described later.

Address signals A ₅ and A ₆ are used to select only one of the four memory matrices. Address signal A ₇ to select one column in one selected memory matrix
~A ₁₁ is used.

The memory matrix selection signal GS is decoded into four combinations based on the address signals A ₅ and A ₆ .

Column decoders C- _DCR1 to C- _DCR4 each perform ²⁵ =
Provides 32 different decode output signals for column selection.

During reading, common data line pair CDL,
CDL is a common data line dividing transistor (Q ₁ ,
Q ₁ ;...;Q ₄ , ₄ ) for each memory array, and the common data line pair CDL is commonly coupled during writing.

Sense amplifiers SA1, SA2, SA3, and SA4 are provided corresponding to the divided commo data line pairs CDL, respectively.

In this way, the common data line pair CDL is divided, and the sense amplifiers SA1, SA2, and SA are connected to each other.
3. The purpose of installing SA4 is to provide a common data line pair.
The objective is to divide the parasitic capacitance of the CDL and speed up the memory cell information read operation.

The address buffer ADB generates 14 pairs of complementary address signals a ₀ to a ₁₃ from the 14 external address signals A 0 to A 13, respectively, and generates 14 pairs of complementary address signals a ₀ to a ₁₃ from the 14 external address signals A 0 to A 13, and decoder circuits (R-DCR,
C-DCR, GS).

The internal control signal generation circuit COM-GE receives two external control signals (chip select signal) and (write enable signal) and generates CS1 (row decoder control signal), SAC (sense amplifier control signal),
Sends we (write control signal), DOC (data output buffer control signal), DIC (data input buffer control signal), etc.

The circuit operation of the S-RAMIC shown in FIG. 1A will be explained with reference to the timing diagram in FIG. 1B.

All operations in this IC, that is, address setting operations, read operations, and write operations, are performed only while one of the external control signals is at a low level. At this time, if the other external control signal is at a high level, a read operation is performed, and if the other external control signal is at a low level, a write operation is performed.

First, address setting operation and read operation will be explained.

The address setting operation is always performed based on the address signal applied during this period when the external control signal is at a low level. Conversely, by keeping the external control signal at high level,
Address setting operations and read operations based on uncertain address signals can be prevented.

When the external control signal becomes low level, the row decoder R-DCR receives a high level internal control signal CS1 synchronized with this signal and starts operating. The above row decoder (also word driver) R-
DCR has eight types of complementary pair address signals a ₀ to a ₅ , a ₁₂
~a ₁₃ is decoded to select one word line and drive it high.

On the other hand, four memory arrays M-ARY1 to M-
Any one of ARY4 is selected by memory array selection signals m1 to m4, and the selected one
one memory array (e.g. M-ARY1)
Two complementary data line pairs (for example, D11, 11) are selected by a column decoder (for example, C-DCR1).

In this way, one memory cell is selected (address set).

Information on a memory cell selected by the address setting operation is sent to one of the divided common data line pairs and amplified by a sense amplifier (for example, SA1).

In this case, four sense amplifiers SA1, SA2,
One of SA3 and SA4 is selected by memory array selection signals m1 to m4, and only the selected sense amplifier operates while receiving the high-level internal control signal SAC.

In this way, the four sense amplifiers SA1, SA2,
Power consumption can be reduced by putting three sense amplifiers out of SA3 and SA4 that do not need to be used into a non-operating state. 3 of the above non-operating states
The outputs of the two sense amplifiers are in a high impedance (floating) state.

The output signal of the sense amplifier is the data output buffer.
Amplified by DOB, IC as output data D _put
Sent to the outside.

The data output buffer DOB operates while receiving the high level control signal DOC.

Next, the write operation will be explained.

When the external control signal becomes low level, a high level control signal we synchronized with it is sent to the common data line dividing transistor (Q ₁ , ₁ :...; Q ₄ ,
_Q4 ) and the common data line pair CDL,
are commonly combined.

On the other hand, while receiving the low level control signal DIC, the data input buffer DIB amplifies the input data signal _Dio from outside the IC and sends it to the commonly coupled common data line pair CDL.

The input data signal on the common data line pair CDL is written into the memory cell M-CEL determined by the address setting operation.

In the S-RAM having the above structure, a circuit as shown in the embodiment of FIG. 2 is newly provided in order to equalize the data line pair D.

The memory cells M-CEL have the same configuration, and although not particularly limited, as shown in detail as a representative in the figure, n
Channel drive MOSFET Q _M1 , Q _M2 and load resistance
A static flip-flop consisting of _R1 and _R2 , and an n-channel transmission gate provided between the input/output terminal of this static flip-flop and a pair of data lines D, respectively.
It consists of MOSFETQ _M3 and Q _M4 .

The memory cell M-CEL has the resistors R ₁ and R ₂
The data is held by supplying the power supply voltage _Vcc to the connection point.

The resistors R ₁ and R ₂ have a high resistance value, for example, several megohms to several gigaohms, in order to reduce the power consumption of the memory cell M-CEL in the data holding state. In addition, the above resistance
R ₁ and R ₂ are relatively high resistance polysilicon layers formed on the surface of a semiconductor substrate forming a MOSFET via a relatively thick field insulating film in order to reduce the area occupied by the memory cell. It consists of

Further, the pair of data lines D are provided with n-channel MOSFETs _{Q L1} and Q _L2 as loads, respectively.

In this embodiment, a pair of data lines D and a word line wL constituting the memory array are shown as representatives.

A p-channel that performs equalization between the pair of data lines D in the memory array.
MOSFETQ _E1 is provided. similar
MOSFETs are also provided in other data line pairs, and the MOSFET Q _E1 is shown as a representative thereof.

A timing pulse φ _E generated by an address input timing detection circuit is applied to the gate of this MOSFET _{Q E1} .

The address input timing detection circuit is configured to detect complementary address signals a ₀ , ₀ to a ₁₃ , ₁₃ formed by the address buffer ADB, although not particularly limited thereto.
Exclusive OR circuits EX ₀ to _{EX 13} each receive
and an OR gate circuit OR which receives the output signals _ex0 to _ex13 , and the timing pulse _φE is obtained from the output terminal of this OR gate circuit.

The operation of this address input timing detection circuit will be explained with reference to the timing diagram of FIG.

When any one of the complementary address signals ai changes, a period in which both ai coincide due to its logic threshold V _T occurs, and its output signal exi changes to a low level (“0”).

Since this match signal exi is output as is through the OR gate circuit, when the address signal ai changes, the timing pulse φ _E changes to a low level (0 volts). Therefore, at this time, the p-channel MOSFET Q _E1 is turned on to short-circuit both data lines D. This allows equalization to be performed to make both levels equal.

In this case, since a p-channel MOSFET is used, as mentioned above, since the level of the data line D is about 3 to 3.5 volts, its gate,
A large voltage of 3 to 3.5 volts can be applied between the sources. Therefore, the on-resistance value can be reduced, and the level difference between the two data lines can be made equal or smaller even in a short period of time. This makes it possible to improve the speed of the next read operation.

Note that even if a complementary circuit is used as the memory cell or the memory cell of the above embodiment,
When configuring the peripheral circuit with a complementary circuit,
No special manufacturing process is required to form the p-channel MOSFET Q _E1 .

The invention is not limited to the above embodiments.

A similar MOSFET for equalization may be provided on the common data line CDL to speed up the operation of the sense amplifier SA.

In addition, the address input timing detection circuit is
It is possible to adopt a reasonable number of embodiments.

Furthermore, it drives the p-channel MOSFET.
Memory cells using MOSFETs use a negative power supply voltage, so the above-mentioned equalization
As the MOSFET, an n-channel MOSFET may be used.

MOS static type to which this invention is applied
RAM can take various embodiments.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing an embodiment of a MOS static RAM to which the present invention is applied;
FIG. 1B is a timing diagram thereof, FIG. 2 is a circuit diagram showing an embodiment of the main part of the present invention, and FIG. 3 is a timing diagram thereof.

Claims (1)

[Scope of Claims] 1. A pair of complementary signal lines to which read information from a selected memory cell is transmitted in a complementary manner, and a pair of complementary signal lines whose gates and drains are at the potential level of a power supply terminal, and whose sources are connected to the complementary signal lines. An n-channel MOSFET provided between the complementary signal line pair and the power supply voltage terminal so as to apply a potential to the pair.
a p-channel that is provided between a pair of data line load elements consisting of a pair of data line load elements and the complementary signal pair and reduces the potential difference between the complementary signal line pair in a conductive state.
MOSFET, and a sense amplifier that receives the signals of the pair of complementary signal lines through a selection means at a pair of input terminals, and connects the p-channel to the pair of complementary signal lines before the signal from the memory cell is transmitted to the pair of complementary signal lines.
A MOS static RAM that is characterized by making the MISFET conductive using a pulse signal. 2. The MOS static RAM according to claim 1, wherein the complementary signal line pair is a data line pair coupled to a memory cell. 3 The memory cell includes a pair of n-channel MOSFETs whose gates and drains are cross-coupled, a pair of load means provided between the power supply terminal and the drain of the n-channel MOSFET, and a drain of the n-channel MOSFET. 2. The MOS static type RAM according to claim 1, wherein the MOS static type RAM is constituted by a pair of transmission gate MOSFETs coupled to each other.