JPH0448715A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the manufacture of a semiconductor, which generates a proximity effect and in which the dimensional error of a pattern at the time of exposure is removed, by conducting first exposure by using a reticule, in which a dummy pattern unnecessary on circuit operation is formed around a sparse pattern, and performing second exposure by employing a reticule, in which only the dummy pattern is taken off. CONSTITUTION:A positive type photo-resist 5 is exposed by employing a reticule 6 shaped by patterning chromium on silica glass in order to form a gate electrode pattern. Since dummy resist patterns 9, 10 are formed adjoined to a sparse resist pattern 11 at that time, the pattern 11 receives the same proximity effect as a dense resist pattern 12. The dummy patterns 9, 10 formed by first exposure are exposed in place of a reticule 13 for exposure for removing the dummy patterns 9, 10 by the reticule 6 after the completion of exposure. Developing is conducted after second exposure, the dummy patterns 9, 10 sections shaped for the first time are taken off, and a photo-resist pattern is formed. Accordingly, dimensional errors in the sparse and dense patterns 11, 12 can be suppressed to one third or less of conventional devices.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming fine patterns with high precision.

[Conventional technology]

In recent years, due to advances in microfabrication technology such as lithography technology and etching technology, the design dimensions of LSIs have become smaller year by year, reaching the submicron range, and subtle dimensional changes have a large impact on the characteristics of LSIs. For this reason, it is extremely important to form fine patterns according to the designed dimensions.

FIG. 7 is a sectional view for explaining a conventional example.

As shown in FIG. 7, a field oxide film 2 and a gate oxide film 3 are formed on a silicon substrate l, and a
A gate electrode layer 4 of approximately A size is formed, and a positive photoresist 5 for forming the gate electrode is applied. The positive photoresist is exposed to light to form a gate electrode pattern using a reticle 20 formed by patterning chromium on quartz glass. The exposed portion is removed by a developer and the photoresist pattern 7 of the gate electrode is removed.
．． 8 is formed (FIG. 8).

In FIG. 9, the repeating patterns are lined up in FIG. 8, and the pattern interval is 2. 2. The size of the dense pattern 7, which is about OF m or less, and the pattern spacing with no surrounding patterns. The dimensions of a sparse pattern 8 of approximately Opm or more were measured at five points within the wafer and graphed. 0
．． For the design dimension of 6pm, the photoresist is patterned almost as designed in dense pattern 7;
For sparse pattern 8, the design dimension is 0. The dimensions have increased by about lpm.

The reason for this is that in dense patterns, light intensity changes (proximity effect) occur due to the influence of neighboring patterns, but in sparse patterns, neighboring patterns are far apart and are not affected by the proximity effect. .

This effect becomes more pronounced as the design dimension of the pattern interval becomes smaller.

In this conventional example, the process of forming the gate electrode has been described, but similar effects occur in other processes as well.

[Problem to be solved by the invention]

With this conventional exposure method, the difference in the proximity effect between patterns with dense pattern density and patterns with sparse density causes differences in the finished dimensions even if the design dimensions are the same. However, there has been a problem in that variations occur in element isolation characteristics, resulting in lower yields and performance deterioration of semiconductor integrated circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the conventional problems by reducing the difference in resist dimension between a sparse pattern and a dense pattern.

[Means for Solving the Problems] In order to achieve the above object, in the method for manufacturing a semiconductor device according to the present invention, a semiconductor integrated circuit pattern consisting of a pattern with a low pattern density and a pattern with a high pattern density is A method of manufacturing a semiconductor device formed in a device, the method comprising: performing a first exposure using a reticle in which a dummy pattern unnecessary for circuit operation is formed around a sparse pattern when exposing the semiconductor device; , a second exposure is performed using a reticle that removes only the dummy pattern.

Further, in the present invention, when exposing the semiconductor device, the first exposure is performed using a reticle in which dummy patterns unnecessary for circuit operation are formed around the sparse pattern and the dense pattern, and then The second exposure is performed using a reticle that removes only the dummy pattern.

[Effect]

According to the present invention, by exposing at least a dummy pattern adjacent to the periphery of a sparse pattern, a proximity effect is generated to eliminate dimensional errors in the pattern during exposure.

〔Example] Next, the present invention will be explained with reference to the drawings.

(Example 1) FIG. 1 is a sectional view showing a semiconductor chip of Example 1 of the present invention.

In FIG. 1, a field oxide M is formed on a silicon substrate L.
A gate electrode layer 4 of about 4000 layers is formed thereon, and a positive photoresist 5 for forming a gate electrode pattern is coated to a thickness of about lpm. The positive photoresist 5 is exposed to light to form a gate electrode pattern using a reticle 6 formed by patterning chromium on quartz glass. In this embodiment, unlike the conventional example shown in FIG.
A dummy pattern 9. is placed adjacent to the dummy pattern 9. Since the pattern 11 forms a to, the pattern 11 is subjected to the same proximity effect as the dense pattern 12. After exposure is completed, the reticle 6 is covered with a dummy pattern 9. In place of the exposure reticle 13 for removing IO, as shown in FIG. 2, a dummy pattern 9. formed in the first exposure is used. Expose IO. At this time, the reticle is prepared so that the exposure area is about 0.2 μm larger, taking into account the alignment error of the exposure machine. After the second exposure, development is performed. The part exposed for the first time by development,
In the second exposure, 9.10 parts of the dummy pattern formed in the first exposure are removed, and a photoresist pattern as shown in FIG. 3 is formed. In this case, the sparse pattern 11 is used as the dummy pattern 9 for the first time. Since it is exposed integrally with lO, it receives the same proximity effect as the dense pattern 12, and the dimensional variation between the sparse and dense patterns 11 and 12 can be suppressed to 1/3 or less of the conventional one.

(Embodiment 2) In the above embodiment, a case was explained in which a dummy pattern was used for a sparse pattern. Next, a case will be explained in which a dummy pattern is also used at an end of a dense pattern. Fourth
The figure is a sectional view of Example 2.

As shown in FIG. 4, a filled oxide film 2 and a gate oxide film 3 are formed on a silicon substrate 1, and a gate electrode layer 4 of about 4,000 layers is formed thereon, and a positive type film for forming a gate electrode pattern is formed. A photoresist 5 is applied to a thickness of about lpm. Positive photoresist 5 is gate 1
In order to form a single-pole pattern, a first exposure is performed using a reticle 14 formed by bonding chromium patterns onto quartz glass.

In Example 1, one side of the pattern at the end of the dense pattern is affected by the proximity effect, but the other side is not affected by the proximity effect. Dimensional differences occur between patterns. In this embodiment, since the dummy patterns 15.16 are also formed in the end patterns 17.18 of the dense pattern 12, the end patterns 17.18 also do not cause a difference in resist dimension. is replaced with the exposure reticle 19 for removing the dummy pattern, and a second exposure is performed (Fig. 5).
, II light and post-development to form a gate electrode resist pattern (FIG. 6), where the gate electrode resist pattern 11.1? , 12.18 are formed as designed dimensions for the reasons stated above, and the dimensional variation due to the pattern is suppressed to 1/3 or less of the conventional size.

In the above embodiments, the gate electrode forming process has been described, but it is obvious that similar effects can be obtained in other processes such as the field forming process.

[Effects of the Invention] As explained above, the present invention exposes a dummy pattern adjacent to the periphery of a sparse pattern to make the influence of the proximity effect equal to that of a dense pattern. The difference in resist dimensions can be reduced. Furthermore, by arranging a dummy pattern at the end of a dense pattern and performing exposure, it is possible to reduce the difference in resist dimension between dense patterns.

[Brief explanation of the drawing]

1, 2, and 3 are sectional views showing a first embodiment of the present invention; FIGS. 4, 5, and 6 are sectional views showing a second embodiment of the present invention; FIG. FIG. 8 is a sectional view for explaining a conventional example, and FIG. 9 is a diagram comparing resist dimensions and design dimensions. 1...Silicon substrate 2...Field oxide film 3...Gate oxide film 4...Gate electrode layer 5...Positive photoresist 6, 13. +4.19.20...Reticle 7.12
...Dense resist pattern 8.11...Sparse resist pattern 9, 10.15.16...Dummy resist pattern 1
7.18...edge pattern

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device in which a semiconductor integrated circuit pattern consisting of a pattern with a sparse pattern density and a pattern with a dense pattern density is formed on a semiconductor device, the method comprising: A semiconductor characterized in that a first exposure is performed using a reticle on which a dummy pattern unnecessary for circuit operation is formed, and then a second exposure is performed using a reticle that removes only the dummy pattern. Method of manufacturing the device. (2) When exposing the semiconductor device, the first exposure is performed using a reticle in which dummy patterns unnecessary for circuit operation are formed around the sparse patterns and dense patterns, and then only the dummy patterns are formed. Claim 1, characterized in that the second exposure is performed using a reticle that is removed.
1) A method for manufacturing a semiconductor device according to item 1).