JPH044774B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a high-precision, high-bit D/A (digital/analog) converter, and is applicable to devices equipped with various D/A converters, such as It is used in voice synthesizers, CD (compact disc) players, etc.

B. Prior Art Conventionally, various types of D/A converters have been put into practical use. Japanese Unexamined Patent Publication No. 57-23321 discloses a D/A converter that combines the advantages of amplitude modulation (AM) type and pulse width modulation (PWM) type, does not require high precision resistors, and has high conversion speed. ing. However, the PWM type D/A converter had the drawback of high harmonic distortion. Japanese Patent Application No. 14032/1983 was made to solve this problem. Unlike conventional PWM type D/A converters, which change the pulse width within one conversion period depending on the content of digital data, this converter has two pulse widths within one conversion period.
Since the analog signal is output so that the potential is widely dispersed according to the input digital data, the harmonic spectrum of the analog signal that is the output of this D/A converter is large in the high range and small in the low range, and the band This restriction aims to reduce harmonic distortion in the low range.

Recently, equipment that requires D/A converters, such as those used in the digital audio field, is required to be lower in price, lower in power consumption, and smaller in size.
Similar demands are made for D/A converters as well.

In order to reduce the size and cost of the D/A converter that combines the AM type and PWM type described in the above-mentioned patent application No. 14032/1980, it is sufficient to reduce the chip size. It is effective to reduce the size of the voltage divider circuit in the AM type D/A conversion section, which occupies a large portion of the power supply. In other words, AM type D/
It is sufficient to reduce the number of bits processed by the A converter. However, if the number of bits processed by the AM type D/A converter is reduced, the number of bits processed by the PWM type D/A converter increases, so the clock pulses in the PWM type D/A converter need to be counted. The base number of the counting circuit increases, and the conversion speed decreases accordingly. In order to avoid this, it is possible to increase the frequency of the clock pulse, but this increases power consumption, which is not preferable for battery drive. In addition, if the frequency of the clock pulse is high, switching noise will increase and unnecessary radiation will occur during mounting, resulting in
The performance as an A converter will deteriorate.

C. Problems to be solved by the invention As mentioned above, there are various difficulties in reducing the chip size of a D/A converter that combines AM type and PWM type. This made it difficult to realize this.

The present invention reduces the number of bits processed by the AM type D/A converter without deteriorating the performance of the D/A converter compared to the conventional one.
The present invention provides a D/A converter in which the voltage dividing circuit in the conversion section can be reduced.

D. Means for Solving the Problems The present invention provides a digital/digital converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data.
A converter, a decoder that decodes the upper M bits of N-bit digital data, and a first reference potential and a second
A first D/A conversion comprising a voltage dividing circuit that divides the voltage between a reference potential and a reference potential of the decoder using ^2M resistors, and a means for selectively extracting two adjacent potentials from the voltage dividing circuit according to the output of the decoder. A clock generating means for generating clock pulses provided for the middle K bits of the N bits of digital data, a ^2K counting circuit for counting the clock pulses from the clock generating means, and a clock generating means for generating clock pulses for the middle K bits of the N bits of digital data; A pulse forming circuit receives digital data of the middle K bits and the count output of the counting circuit and outputs a pulse signal according to the contents of the digital data of the middle K bits, and a pulse forming circuit receives the digital data of the middle K bits and outputs a pulse signal according to the contents of the digital data of the middle K bits, a second D/A converter circuit comprising means for selecting and combining one of two adjacent potentials outputted from the first D/A converter circuit; a first reference potential and a second end connected to the first reference potential and one end of the voltage divider circuit, and between the second reference potential and the other end of the voltage divider circuit, respectively. According to the content of the digital data of the lower J bits among the N bits, the second resistor network maintains the sum of the resistance values of the first resistor network and the second resistor network constant. 1. A third D/A conversion circuit including means for changing the resistance value of the second resistor network.

E. Effect The lower J bit data of the N bit digital data is given to the third conversion circuit, and the potential applied to both ends of the voltage dividing circuit in the first D/A conversion circuit is changed according to the J bit data. , the potential difference is changed in a constant state, and the potential that is divided and taken out from this voltage dividing circuit is changed. Then, the first D/A converter circuit selects and outputs the two adjacent potentials taken out from this voltage divider circuit according to the data of the upper M bits, and the second D/A converter circuit selects and outputs them. One of these two adjacent potentials is selected and combined in accordance with the middle K-bit data, and an analog signal corresponding to the N-bit digital data is output.

F. Embodiment FIG. 1 is a schematic diagram of a D/A converter according to the present invention. (1) is the first D/A conversion circuit, which is composed of a decoder 11 that decodes the upper M bits of digital data of input N (=M+K+J) bits, and ^2M resistors R. and a switching circuit 13 that selects and extracts two adjacent potentials V ₁ and V ₂ from the voltage divider circuit 12 according to the output of the decoder 11. . (2) is a second D/A conversion circuit, which includes a clock pulse generator 21 that generates clock pulses and counts the clock pulses from the clock pulse generator 21.
2 ^K -ary counting circuit 22, a pulse forming circuit which takes as input the middle K bit data of the N bits and the output from the counting circuit 22, and outputs a pulse signal having a pulse width corresponding to the K bit data. 23 and
It is composed of two switching transistors 24b and 24c that act complementary to the inverter 24a, and in response to the pulse signal, the two adjacent potentials V ₁ and V ₂ outputted from the first D/A conversion circuit 1 are a selection synthesis circuit 24 that selects and synthesizes one of the two;
It consists of a low pass filter 25. Reference numeral 3 denotes a level shift circuit as a third D/A conversion circuit, which is connected between the first reference potential Vref1 and one end of the voltage dividing circuit 12, and between the second reference potential Vref2 and the other end of the voltage dividing circuit 12. is established between. Data of the lower J bits among the N bits is input to this level shift circuit 3, and according to this data,
The potential applied to both ends of the voltage dividing circuit 12 is changed while maintaining the potential difference.

Below, N=16 and the input data a15, a14,
..., a0 to the first D/A conversion circuit 1.
8 bits of a15, a14, ... a8 (M = 8) to the second D/A conversion circuit 2 4 of medium a7, a6, a5, a4
A case will be described in which the lower 4 bits a3, a2, a1, and a0 (J=4) are supplied to the third D/A conversion circuit 3.

FIG. 2 is a circuit configuration diagram of the level shift circuit 3, which is the third D/A conversion circuit. This level shift circuit 3 includes a voltage dividing circuit 12 of the first D/A conversion circuit 1, a first reference potential Vref1, and a second reference potential Vref1.
It is provided between Vref2 and receives lower J bit data a3, a2, a1, and a0. Voltage divider circuit 1
Between one end of 2 and Vref1 are resistors R ₁ , R ₂ , R ₃ ,
R ₄ are connected in series in this order, and resistors R ₅ , R ₆ ,
R ₇ and R ₈ are connected in series in this order. resistance
A resistor _R9 and a switch transistor are connected across _R1 .
The series circuit with T ₁ is connected to the voltage dividing circuit 12 side. Similarly, resistors R ₂ , R ₃ ,
Resistors R ₁₀ , R ₁₁ , R ₄ , R ₅ , R ₆ , R ₇ , R ₈ respectively,
A series circuit of R ₁₂ , R ₁₃ , R ₁₄ , R ₁₅ , R ₁₆ and each of the switch transistors T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , T ₇ , T ₈ has a resistor. It is connected so as to be on the voltage dividing circuit 12 side. And J (=4)
Bit data a0, a1, a2, a3 are transmitted directly to the respective gates of switch transistors T ₁ , T ₂ , T ₃ , T ₄ and also to switch transistors T ₅ , T ₆ ,
It is applied to the gates of T ₇ and T ₈ via an inverter 40.

Assuming that the resistance values of the resistors R ₁ to R ₁₆ and the resistor R of the voltage dividing circuit 12 are as indicated by the symbols, each resistance value is determined so as to satisfy the following relational expression.

R ₁ , ~, R ₈ = R R ₉ = R ₁₃ = 255 x R (2 _K+J -1) x R R ₁₀ = R ₁₄ = 127 x R (2 _K+J-1 -1) x R R ₁₁ = R ₁₅ = 63 x R (2 _K+J-2 -1) x R R ₁₂ = R ₁₆ = 31 x R (2 _K+J-3 -1) x R One end A of voltage divider circuit 12 and Vref1 Let R _A be the resistance value between the terminal B and Vref2, and R _B be the resistance value between the other end B and Vref2. When the switch transistor T ₁ or T ₅ is turned on, R _A or R _B becomes R-255R. ×R/(255R+
R) = R/256 smaller. Similarly, when T ₂ or T ₆ is turned on, R _A or R _B becomes R/
128 When T ₃ or T ₇ is turned on, R _A or R _B becomes R/64 When T ₄ or T ₈ is turned on, R _A or R _B becomes smaller by R/32, respectively.

Due to the presence of the inverter 40, switch transistors T ₁ to T ₄ and T ₅ to _{T 8} are turned on and off in a complementary manner, so Vref1 and Vref2 are
The resistance value Rj between the two is maintained at Rj=(2 ¹⁶ +8− ¹⁵ /256)R. That is, while the potential difference between point A and point B is kept constant, R _A ,
Since R _B is changed to 0, R/256, 2R/256..., 15R/256, the level of the divided voltage output terminal of the voltage dividing circuit 12, that is, V ₁ and V ₂ , is changed to 16 gradations (4 bits). Can be shifted.

Here, a case will be described in which one bit of the minimum resolution (1LSB) among N (=16) bit data changes.

J = 4 bits of data a0, a1, a2, a3 are a0 =
When a1 = a2 = a3 = 0, R _A = 4R R _B = 4R - 15R / 256, and the potential V _B (0) at point B is V _B (0) = (Vref1 - Vref2) x (4R - 15R/256) Rj.

Next, when a0=1, a1=a2=a3=0, R _A =4R-R/256 R _B =4R-14R/256, and the potential V _B (1) at point B is V _B (1 )=(Vref1−Vref2)×(4R−14R/256)Rj. Therefore, the potential difference E _LSB between V _B (0) and V _B (1) is E _LSB = {(Vref1 - Vref2) x R/Rj}/256. Since the voltage step e _M between the divided voltage output terminals of the voltage dividing circuit 12 is e _M = (Vref1 - Vref2) x R/Rj, E _LSB is the potential divided by the voltage dividing circuit 12. /256 (=1/2 ₈ ).

In other words, the level shift circuit 3, which is the third D/A conversion circuit, shifts the potential divided and output from the voltage dividing circuit 12 according to the input J=4 bit data a3 to a0. There is.

In the first D/A conversion circuit 1, the input M=
The 8-bit data a15 to a8 are decoded by the decoder 11, and from among the level-shifted divided voltage outputs of the voltage dividing circuit 12, two adjacent potentials V ₁ and V ₂ are selected by the switching circuit 13 based on the decoding results. It is outputting.

Now, in the second D/A conversion circuit 2, the K-bit data inputted while the ^2K- base counting circuit 22 counts ^2K clock pulses output from the clock generator 21 (one conversion period). Pulse signals corresponding to a7 to a4 are output from the pulse forming circuit 23. FIG. 3 shows a schematic circuit diagram of the pulse forming circuit 23 corresponding to K=4 bits.

The pulse forming circuit 23 inputs the count outputs Q ₁ , Q ₂ , Q ₃ , Q ₄ of the counting circuit 22 and the clock pulse CLK from the clock generator 21, receives each clock pulse CLK at its clock input terminal, and receives the clock pulse CLK at its D input terminal. first, second, and third D flip-flops 26, 27, and 28 which input counting outputs Q ₂ , Q ₃ , and Q ₄ respectively;
a first AND gate 29 which receives bit data a7 of the K-bit data and count output _Q1 ;
A second AND gate 30 inputs the bit data a6, the counting output _Q2 , and the output of the first D flip-flop 26, the bit data a5, the counting output _Q3 , and the second D flip-flop 26;
The third input terminal inputs the output of the flip-flop 27.
an AND gate 31, a fourth AND gate 32 which inputs the bit data a4, the counting output _Q4 , and the output of the 3D flip-flop 28;
31, 32, and an OR gate 33 which inputs each output C ₁ , C ₂ , C ₃ , C ₄ .
The output C ₀ is output to the selection and synthesis circuit 24.

In other words, the high and low digits of the input digital data and the high and low output of the counting circuit 22 are combined in reverse order, and the AND gates 29, 30, 31,
Q ₂ , Q ₃ , and Q ₄ other than the least significant digit of the output of the counting circuit 22 are also applied to D flip-flops 26 , 27 , and 28 , which are driven by the clock pulse CLK to be counted, respectively. The outputs of these flip-flops are also applied to AND gates 30, 31, and 32 in the same way as Q ₂ , Q ₃ , and Q ₄ .

FIG. 4 for explaining the typical operation of this pulse forming circuit 23 shows the first, second, and third periods (T ₁ , T ₂ , and T ₃ ) corresponding to one conversion period, respectively. Data “12” (a4=0, a5=0, a6=0, a7=1) as K=4-bit data,
Data “8” (a4=0, a5=0, a6=0, a7=
1), and data “1” (a4=1, a5=0, a6=
0, a7=0) are respectively input to the second D/A conversion circuit 2. First period (T ₁ )
Since significant information "1" is given to bit data a6 and a7, AND gate outputs _C11 and _C21 appear in the first and second AND gates 29 and 30, respectively. On the other hand, the third and fourth AND gate 3
Since there is no significant information in 1 and 32, OR gate 3
The logical sum C ₀₁ of C ₁₁ and C ₂₁ appears in the 3 output C ₀ . This C ₀₁ is a pulse signal that represents "12" as the sum of the pulse widths, that is, the sum of the periods in which it is "1", and the pulses are "1", "1", and "1" almost evenly throughout the first period (T ₁ ). These are the pulse width and pulse period in which each “0” is distributed.

During the second period (T ₂ ), only bit data a7 receives significant information "1", so the OR gate 33 outputs a pulse signal C ₀₂ that matches the output C ₁₂ of the first AND gate 29. This C ₀₂ is a pulse signal that represents "8" as the sum of the A pulse widths, and is a pulse in which "1" and "0" are distributed approximately evenly throughout the second period (T ₂ ). width and pulse period.

Furthermore, the third
During period (T ₃ ), significant information “1” is input only to bit data a4, so OR gate 3
3 outputs a pulse signal C ₀₃ that matches the output C ₄₃ of the fourth AND gate 32.

Regardless of the digital data that is input in this way, the pulse width and pulse period change according to the input data so that the pulses are approximately evenly distributed within one conversion period, and the total pulse width is determined. This means that the number of bits K of input digital data is 4.
The same applies even if the value is larger.

The pulse signal C ₀ output in this way is
It is input to the selection synthesis circuit 24. Selection synthesis circuit 2
4 consists of a switching transistor 24b to which a pulse signal is directly applied to its gate, an inverter 24a to which a pulse signal is applied, and a switching transistor 24c to which a pulse signal is applied to its gate via this inverter 24a. The connection mode of the transistors 24b and 24c is connected to the low-pass filter 25 to generate an analog signal.
You're getting Vout. While the output pulse signal of the pulse forming circuit 23 is “1”, the transistor 24b
is turned on and the first potential V1 output from the first D/A conversion circuit ₁ is selected, and while the pulse signal is "0", the transistor 24c is turned on and the second potential _V2 is selected. be done. These potentials are synthesized in time series, harmonic components are removed by a low-pass filter 25, and output.

V ₁ output from the first D/A conversion circuit 1,
From the above explanation, V ₂ can be expressed as follows.

V ₂ = {(Vref1−Vref2)/Rj}×{4R−15R/
256+(a15×2 ⁷ +a14×z ⁶ …+a8×2 ⁰ )R+
(a3×2 ³ +a2×2 ₂ +a1×2 ₁ +a0×2 ₀ )×R/
256} =Vconst+(a15×2 ⁷ +a14×2 ⁶ +…+a8×
2 ⁰ ) × e _M + (a3 × 2 ³ + a2 × 2 ² + a1 × 2 ¹ + a0 ×
2 ⁰ ) × e _M / 256 V ₁ = V ₂ + e _M However, Vconst = (Vref1 − Vref2) × (4R − 15R /
256)/Rj The output Vout of this D/A converter is
In the A conversion circuit 2, the potential of e _M (=V ₁ - V ₂ ) is set to 16
(= ^2K ) is divided and combined and output, so Vout=V ₂ + (a7×2 ³ + a6×2 ² + a5×2 ¹ + a4×
2 ⁰ )×e ^M /16. Therefore, Vout=Vconst+(a15×2 ⁷ +a14×2 ⁶ +…+a8
×2 ⁰ )×e _M +(a7×2 ³ +a6×2 ² +a5×2 ¹ +a4
×2 ⁰ )×e _M /16+(a3×2 ³ +a2×2 ² +a1×2 ¹
+a0×2 ⁰ ) e _M /256=(a15×2 ⁷ +a14×2 ⁶ +
…+a8×2 ⁰ +a7×2 ³ +a6×2 ² +a5×2 ¹ +a4
×2 ⁰ +a3×2 ³ +a2×2 ² +a1×2 ¹ +a0×2 ⁰ )
×e _M /256+Vconst. In other words, in FIG. 1, it is a 16-bit D/A converter with e _M /256 as the LSB.

D/A converter is a combination of only the first D/A converter circuit and the second D/A converter circuit like the conventional one.
Compared to A conversion circuits, the D/A converter of the present invention reduces the number of bits input to each D/A conversion circuit. When the number of input bits in the second D/A conversion circuit (PWM type) is 8 bits, the clock frequency of the counting circuit is equal to the sampling period.
It requires 11.29KHz or more, which is ²⁸ times 44.1KHz, but
If this is 4 bits, the clock period is ²⁴ times
705.6KHz or higher is sufficient. This is D/
As an A converter, it is possible to realize a high performance device that consumes less power and has less switching noise and unnecessary radiation due to high frequency clock pulses.

Furthermore, if the number of bits input to the first D/A conversion circuit (AM type) is reduced, the number of high-precision resistors can be reduced accordingly, and the chip size can be reduced. Especially since the number of resistors is ^2M , the effect is very large.

Note that the resistors used in the level shift circuit, which is the third D/A conversion circuit, should have a low resistance value of R ₁ to R ₈ .
High resistance values of R ₉ to _{R 16} are connected in parallel and the overall resistance value is digitally converted, so the high resistance values of R ₉ to _{R 16} do not have high accuracy. Not needed. For example, resistors R ₁ , R ₅ , R ₉ ,
R ₁₃ represents the minimum resolution (LSB) of 16 bits, but R ₁ , R ₅ , R ₉ , and R ₁₃ represent the minimum resolution (LSB) of ₁₆ bits. The resistance ratio required for R ₅ , R ₉ and R ₁₃ (±
The range that falls within 1/2LSB is 1:170 to 511,
R ₉ and R ₁₃ do not require as much precision as the resistors used in voltage divider circuits. Therefore, the amount of increase in chip size due to the addition of the third D/A conversion circuit is small.

FIG. 5 shows another example of the third D/A conversion circuit. In FIG. 5, a decoder 41 for J-bit data is provided, and a voltage dividing circuit 12 is provided.
The resistors connected in series are one each on each side of R ₂₀ and R ₃₀ , and one or more high resistances are connected in parallel to these resistors R ₂₀ and R ₃₀ depending on the input digital data. It is.

That is, a series circuit of resistors _{R 21 ,} R ₂₂ , R ₂₃ . . . R _o and a switch transistor Tn is connected in parallel to the resistor R 20, and the transistor Tn and the resistor R ₂₀ are connected to the signal line and each resistor R ₂₁ , R ₂₂ , R ₂₃ ... between the connection mode of R _o and the switch transistors T ₂₁ , T ₂₂ ,
T ₂₃ ..., is connected. Similarly, resistors R ₃₁ , R ₃₂ , R ₃₃ , . . . , Rm and switch transistors T ₃₁ , T ₃₂ , T _{33 , .} . . , Tm are connected to the resistor R ₃₀ side.

J-bit data is input to a decoder 41. The decoder selects one of the switch transistors T ₂₁ , T ₂₂ , T _{23 .} . . , Tn according to the input data,
A signal to turn on one of the switch transistors T ₃₁ , T ₃₂ , T ₃₃ ...Tm is generated, and one or more high resistances are determined by the turned on transistor.
By connecting R ₂₁ , R ₂₂ , . . _. , R ₃₁ , R _{32 ,} .

G. Effects of the Invention As is clear from the above description, the present invention includes an AM-type first D/A conversion circuit, a PWM-type second D/A conversion circuit, and a third D/A conversion circuit using a level shift circuit.
Since one D/A converter is made up of several D/A conversion circuits, the number of bits of data input to each conversion circuit can be reduced, reducing the chip size of the D/A converter and reducing power consumption. It is possible to reduce the noise and reduce the noise.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a third conversion circuit, FIG. 3 is a schematic circuit diagram of a second conversion circuit, and FIG. 4 is a diagram of a pulse forming circuit. A time chart for explaining the operation, and FIG. 5 is a circuit configuration diagram of another embodiment of the third D/A conversion circuit. 1... First D/A conversion circuit, 2... Second D/A conversion circuit, 3... Third D/A conversion circuit,
11...Decoder, 12...Voltage divider circuit, 13...
Switching circuit, 21...Clock generation section, 2
2... Counting circuit, 23... Pulse forming circuit, 24
...Selective synthesis circuit, 25...Low pass filter.

Claims (1)

[Claims] 1 In a D/A converter that outputs an analog signal corresponding to N (=M+K+J) bits of digital data, a decoder that decodes the upper M bits of the N bits of digital data, a first standard. Potential and second
A first D/A conversion comprising a voltage dividing circuit that divides the voltage between a reference potential and a reference potential of the decoder using ^2M resistors, and a means for selectively extracting two adjacent potentials from the voltage dividing circuit according to the output of the decoder. A clock generating means for generating clock pulses provided for the middle K bits of the N bits of digital data, a ^2K counting circuit for counting the clock pulses from the clock generating means, and a clock generating means for generating clock pulses for the middle K bits of the N bits of digital data; A pulse forming circuit receives digital data of the middle K bits and the count output of the counting circuit and outputs a pulse signal according to the contents of the digital data of the middle K bits, and a pulse signal output from the pulse forming circuit is used. said first D/ for a defined period of time.
a second D/A converter circuit equipped with means for selecting one of two adjacent potentials output from the A converter circuit and selecting and synthesizing the other in the remaining period; J bits, and connected between the first reference potential and one end of the voltage divider circuit and between the second reference potential and the other end of the voltage divider circuit, respectively. 1. The second resistor network maintains the sum of the resistance values of the first resistor network and the second resistor network constant according to the content of the digital data of the lower J bits among the N bits. , a third D/A conversion circuit equipped with means for changing the resistance values of the first and second resistance networks, and converts the combined output from the second D/A conversion circuit into a predetermined value. A D/A converter that obtains an analog output by averaging over a period. 2. The pulse forming circuit outputs a pulse signal whose pulse width and pulse period change according to the content of digital data of medium K bits, and whose pulse width in 2 ^K clock periods is determined in total. A D/A converter according to claim 1, characterized in that: