JPH0447492B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a configurable logic element (CLE).
configurable logic elements), and more particularly to configurable logic elements having configurable combinational logic elements, configurable storage elements, and configurable output selection logic.
The output signal of the configurable storage element becomes the input signal to both the configurable combinational logic circuit and the output selection logic circuit. The output signal of the output selection logic circuit is selected from the output signal of the combinational logic element and the output signal of the storage element. The configurable logic element disclosed herein is suitable for application in a microprocessor so that it can be easily interfaced with a microprocessor without utilizing other features of the configurable logic element. with additional circuitry.
In particular, configurable logic elements suitable for application in microprocessors according to the invention include:
a second storage circuit for storing data from the microprocessor and providing signals representative of the data stored in the configurable logic element; It has means for enabling the setter to read, a configurable storage element, and a storage circuit.

<Prior Art> Japanese Patent Application No. 60-121357 filed by the same applicant describes the configuration of an integrated circuit to be finally manufactured when the integrated circuit is assembled into a system. A so-called configurable structure is disclosed, which allows the same integrated circuit to implement any one of a plurality of logical functions by appropriately changing the structure. This refers to multiple "configurable" systems, each of which can be configured to realize any of multiple logical functions depending on the required task/purpose.
This is achieved by providing logic elements (hereinafter referred to as configurable logic elements).

A configurable logic element refers to a plurality of logic elements that can be electrically interconnected by switches activated in response to control bits stored on or transmitted to the chip to implement any of a number of logic functions. means a combination of devices. The configurable logic elements disclosed in the patent application include, for example, AND gates,
flip-flop, inverter, NOR gate,
It includes all the circuit elements necessary to provide one or more functions, such as those provided by exclusive OR gates and combinations of these basic functions to realize more complex functions. The specific function to be accomplished by the configurable logic element is determined by control signals provided to the configurable logic element from the control logic circuit. Depending on this control signal, the configurable logic elements can be configured as AND gates, OR gates,
NOR gate, NAND gate, exclusive
OR gate or any of several other logic functions,
It can be realized without changing its physical structure.

Structures are formed on the chip that can implement any of these functions to be implemented by the configurable logic elements. this is,
This is made possible by providing a control logic circuit that stores and generates control signals that control the configuration of the configurable logic elements.

In some embodiments, control signals are stored and transmitted by control logic that is integrally formed as part of an integrated circuit chip that includes configurable logic elements. However, if desired, the control signals can also be stored and/or generated external to the integrated circuit in which the configurable logic element is formed and transmitted to the pins of the configurable logic element. can.

Generally, a particular set of control signals, such as control bits, are transmitted from a control logic circuit to a configurable logic element to control the configuration of the configurable logic element.
The contents of the actual control bit set to be supplied to the configurable logic elements on the integrated circuit chip are:
It depends on the functionality to be implemented by the configurable logic elements on the chip.

<Problems to be Solved by the Invention> U.S. Patent Application No. 706,429 (Japanese Unexamined Patent Publication No. 61-224520) assigned to the present applicant describes a configurable combinational logic element, a configurable storage element, and a configurable output selection. A highly versatile configurable logic element having a logic circuit is disclosed. The output signals of the configurable storage elements provide input signals for both the configurable combinational logic and the output selection logic. However, if data signals from a microprocessor are stored in a configurable logic element, problems such as the configurable storage element becoming unavailable to receive other output signals from the configurable combinational logic element may cause this configurable logic element to The problem is that it cannot easily communicate with a microprocessor. Moreover, communication between such an array of configurable logic elements and a microprocessor requires the use of a comprehensive interconnect structure for the array of configurable logic elements, which reduces the versatility of the array. It becomes necessary.

Means for Solving the Problems A configurable logic element according to the present invention suitable for application in a microprocessor is disclosed in U.S. Pat. It has a high degree of diversity in configurable logic elements.

A configurable logic element according to the invention suitable for application in a microprocessor has a first storage element, each configured by a control bit, an output selection logic circuit, and a combinatorial logic element. The selected feedback signal from the storage element and the selection input signal provided to the configurable logic element become input signals to the combinatorial logic element. The output signals of the combinational logic elements and the input signals to the configurable logic elements become input signals to the configurable storage elements. The output selection logic circuit provides an output signal selected from the output signals of the combinational logic element and the storage element.

The configurable logic element according to the invention comprises:
It has additional circuitry to allow easy interfacing to a microprocessor without utilizing other functions of the configurable logic element. In particular, a configurable logic element according to the invention stores a bidirectional data bus and data written by a microprocessor, and selects a stored signal from a combinational logic element and an output signal of the combinational logic element. a second memory circuit for providing means for making the status of the microprocessor readable by the microprocessor, and a stateable memory element.

<Embodiments> Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1 shows the logical functions that can be realized by configurable logic elements.
The 28 functions are listed for illustrative purposes only; functions not listed may be implemented by the configurable logic elements as desired.

Table 1 Element Function 1 AND gate 2 NAND gate 3 AND gate with inverted input 4 NAND gate with inverted input 5 OR gate 6 NOR gate 7 Exclusive OR gate 8 Exclusive NOR gate 9 3-input AND gate 10 3-input NAND Gate 11 3-input OR gate 12 3-input NOR gate 13 OR gate with 1 input with AND gate 14 NOR gate with 1 input with AND gate 15 1 input with OR gate
AND gate has one input with 16 OR gates
NAND gate 17 3-input AND gate with one inverting input 18 3-input NAND with one inverting input
Gate 19 Three-input OR gate with one inverting input 20 Three-input NOR gate with one inverting input 21 Multiplexer with alternative input 22 Multiplexer with alternative inverting input 23 "D" flip-flop with reset 24 set Reset latch 25 "D" flip-flop with reset and inverted outputs 26 Set reset latch 27 "D" flip-flop with reset and inverted outputs 28 "D" flip-flop with set and inverted outputs FIG. Figure 2 shows the internal logical structure of one embodiment that may implement all useful basic functions for A and B. This function uses control lead C
Configuration control signal C0,0,C2, applied to 0,0,C2,2,...
2,... is selected. In this example, all control leads are connected to the gate of an N-channel enhancement mode pass transistor. In order to realize the AND gate function with the structure shown in FIG. By applying a signal, pass transistors 29c and 2
9d is made conductive, and the input leads labeled A and B are shunted across the front and rear ends of the inverters 21 and 22.

A low level signal is applied to configuration control leads 0 and 1, causing inverter 21
and 22 are cut off from the AND gate 25. Furthermore, the high level signal on lead C5
is added to AND gate 25, and this AND gate 2
Enable 5. In this way, 3 inputs
AND gate 25 now functions as a two-input AND gate for signals A and B. AND
The output signal of gate 25 provides the input signal of NOR gate 26. A second input signal applied to NOR gate 26 is derived from the output signal of AND gate 24. The output signal of the AND gate 24 is
Logic 0 on configuration control lead C4
It is held in a logic zero state by applying a signal. The control signals C2 and C3 can be at any level, and the output signal of the AND gate 24 is not affected whether these signals are high or low. AND gate 24
Since the output signal of is a logic 0 and the tri-state control input signal to the NOR gate 26 is a logic 0,
It will be readily appreciated that AND gate 25, AND gate 24 and NOR gate 26 together function as a NAND gate for input signals A and B. The three-state control signal applied to NOR gate 27 (except during reset)
Since it is a logic 0, NOR gate 27 functions as an inverter for the output signal of NOR gate 26. The output signal of NOR gate 26 is applied to the gate of N-channel transistor 29A. The source of this transistor 29A is grounded, and its drain is connected to the output lead 28. Then, the output signal of the NOR gate 26 is
It is applied to the gate of N-channel transistor 29b. The source of transistor 29b is connected to the power supply, and the drain of this transistor is connected to output lead 28 and N-channel transistor 29a.
connected to the drain. Therefore, transistors 29a and 29b function as inverters for the output signal of NOR gate 26. Thus, the structure of FIG. 2 constructed as described above functions as an AND gate for signals A and B. In this manner, other logic functions can be realized by applying appropriate control signals to configuration control leads C0-C5 and activating appropriate pass transistors and gates within the structure. .

Figure 3A shows the 16
Indicates bit RAM. Input signals A and B select any of the four columns within the 16-bit RAM by controlling the X decoder. Input signals C and D control the Y decoder and are 16-bit
Select one of the four rows of RAM.
In this manner, the 16-bit RAM produces an output signal corresponding to the bit at the intersection of the selected row and column. There are 16 such intersections, and therefore 16 types of bits can be generated. As a combination of functions represented by 16 bits, 2 = 16
(2 ¹⁶ ) street is possible. Therefore, 16 in RAM
If a NOR gate is simulated by the bits, the Karnot map for the RAM will be as shown in FIG.

In Figure 3C, the first row (A=0 and B=
0) and the first column (C=0 and D=0
All bits are 0 except for the bit at the intersection of If you want to implement a very rarely used function with 16-bit RAM (for example, if A=1,
If it is desired to obtain an input signal "1" for B=0, C=0 and D=0, a binary "1" is stored at the intersection of the second row and the first column. A=
0, when B=0, C=0 and D=0 and A=1,
If you want to obtain a binary "1" even when B = 0, C = 0, and D = 0,
A binary "1" is stored at the intersection of the first row and the second row of the first column. like this
The logic circuitry corresponding to the memory states of the RAM is shown in FIG. 3D. In this way, the RAM in Figure 3A
can express any of the 16 logical functions well and simply.

FIG. 3B shows an alternative structure that can generate any of the 16 select bits. Registers 0-15 in the left vertical column labeled "16 Select Bits" each have a selected signal consisting of a binary "1" or "0". By selecting the appropriate combination of A, B, C, and D, a certain bit stored in one of the 16 positions of the 16 select bit register is transmitted to the output lead. For example, when transmitting the bit of the "1" register to the output lead, the signal A,
B, C and D are added to the reads labeled as such. 16 select bit register
When transmitting the signal labeled "15" out of 16 to the output lead, the signals A, B,
C, and D are added to the appropriate columns. In this way, this structure can be used to implement any of the 2≓16 logic functions.

FIG. 4A shows a configurable logic array (CLA) having nine configurable logic elements.
shows. As shown in FIG. 4A, each of the nine configurable logic elements 40-1 through 40-9 has a plurality of input leads and one or more output leads. Each input lead has a plurality of access junctions connecting selected common interconnect leads to the input lead. Fourth
In figure A, the configurable logic element 40-
The access junctions of input leads 2 of 7 are labeled A1-A4. Access junctions for other input leads are only shown and are not specifically labeled to avoid cluttering the drawing. Similarly, each output lead of each configurable logic element has a plurality of access junctions connecting it to a corresponding one of the general interconnect leads. In FIG. 4A, these access junctions are illustrated for each output lead of each configurable logic element. The access junctions for reading the output of configurable logic element 40-7 are labeled B1-B5. Leads shown in FIG. 4A that are neither input leads nor output leads are referred to as general interconnect leads, and are shown in FIG. 4A that are not access junctions for input leads or output leads. The juncture is what is called a general interconnect juncture.

As shown in FIG. 4A, nine logics with a general interconnect structure having programmable access junctions and programmable general interconnect junctions connecting the general interconnect leads and the various loads to other leads. The elements are integrated on an integrated circuit chip. The general interconnect structure has a set of general interconnect leads and a programmable junction, and the programmable junction connects a specific general interconnect lead within the general interconnect structure for each general interconnect lead within the general interconnect structure. The general interconnect leads having such characteristics that there is a program governing the general interconnect junction connecting to one or more leads of the general interconnect junction. Further, for any particular output lead of any configurable logic element within the configurable logic array, and for any particular input lead of any configurable logic element within the configurable logic array, the particular output lead described above is connected to the particular input lead described above. There is a program that governs the junction as it is connected. The conductive path from a particular output lead to a particular input lead always includes two access junctions and at least a portion of the general interconnect lead. For example, the conductive path from the output lead of configurable logic element 40-8 to the second input lead of configurable logic element 40-7 includes access junctions A7 and B.
7 and a portion P of the general interconnect lead. Generally, the conductive path from the output lead of one configurable logic element to the input lead of another configurable logic element further includes one or more general interconnection junctions.

Each of the logic elements 40-1 to 40-9 may be a circuit as shown in FIG. 2 or a similar circuit constructed as shown in FIG. 2 such that it may implement any of a plurality of logic functions. It consists of a set of circuits with the structure. To program this circuit (to program both the configurable interconnect switch and the configurable logic element), the logic element is The logic elements are interconnected as desired. In FIG. 4A, no leads are specifically identified as input leads for configuration control signals. However, any I/O pad can be used as this lead.

Configuration control bits are input to the configurable logic array in series or in parallel depending on various design conditions, which are typically stored in programmable registers as shown in FIG. Alternatively, the configuration control bits may be stored in on-chip memory. Furthermore,
A separate I/O pad may be used for input clock signals, particularly those used to transmit configuration control signals to program registers. When the configurable logic array shown in FIG. 4A is configured, logic elements 40-
Selected output signals from 1 to 40-9 are provided to selected I/O pads. FIG. 4B shows the meaning of the juncture symbols used in FIG. 4A.

Configurable logic arrays such as those described above are relatively inefficient in terms of effective utilization of on-chip area compared to fixed state circuits that perform the same function. The advantage of this configurable logic array circuit is that it is user programmable and can be reprogrammed if desired. All you need to do is keep one type of chip in stock. If an error is discovered in the program, the chip can be reprogrammed relatively easily by the user. With conventional chips, if an error was discovered in the program, the chip had to be discarded. Delays in development and manufacturing cycles caused by chip manufacturers incorporating programs into chips can be prevented. The chip can be manufactured as a versatile standard product that can be configured after sale to meet the needs of the user.

To configure a logic element such as logic element 40-1 (FIG. 4A), a number of bits may be placed on configuration control leads, such as leads C0-C5 as shown in FIG. must be supplied. For this purpose, for example, a shift register is used as part of each configurable logic element. FIG. 5 shows a shift register that can be used for this purpose. The shift register of FIG. 5A has two basic storage cells. Each storage cell can store one bit of information. Of course, an actual shift register may have as many storage cells as necessary to configure the logic elements of which it is a part into its desired configuration. During actual operation, an input signal is applied to input lead 58.

As shown in FIG. 6D, this input signal is used to configure the configurable logic elements to implement the desired logic function and to configure the access junctions or general interconnect junctions between the general interconnect leads described below. It has a bit string to be applied to the shift register as configuration control bits to configure (program) it. In this manner, the series of pulses applied to input lead 58 is configured such that, when stored in the storage cells of the shift register, the desired functionality and/or interconnection state is achieved in an appropriate manner. generation control bits. For example, when configuring the circuit of FIG. 2 to form an AND gate, pulses C0, C1, C2, C
3, C4 and C5 are represented by 1, 1, X, X, 0 and 1.

The pulse train applied to input lead 58 is synchronized with clock pulses Φ1 and Φ2 applied to leads 57 and 59, respectively. Therefore, in the early stages of operation, when clock pulse Φ1 goes high (FIG. 6A) and clock pulse Φ2 goes low (FIG. 6B), the hold signal (FIG. 6C)
goes low during a shift, facilitating the flow of data through the serially connected storage cells 5-1, 5-2, etc. of the shift register.

When shifting the pattern "01010" into the shift register, the following operations are performed. That is, during approximately the first half period of clock period t1, the input signal on lead 58 is low. The output signal 1 of the inverter 51-1 is the input signal being at a low level,
In response to Φ1 becoming high level, pass transistor 50-1 is enabled. When the first clock period t1 has elapsed for a certain period of time, the clock signal Φ1 becomes low (FIG. 6A), and the clock signal Φ1 becomes low (FIG. 6A).
2 then goes high (Figure 6B), enabling pass transistor 55-1. In this way, high level output signal 1 is transmitted to the input lead of inverter 52-1 through enabled pass transistor 55-1, producing a low level output signal Q1 on the output lead of inverter 52-1. let

In this way, at the final stage of the period t1, the output signal Q1 (FIG. 6F) from the inverter 52-1 becomes low level. Output signals 2 and Q2 from inverters 51-2 and 52-2 in the second cell are transmitted to the second storage cell 5-2 as known signals for changing the signals of these inverters to a known state. As it has not been done yet, it is still in a state of uncertainty.

At the beginning of the second period (indicated by t2 in Fig. 6A), Φ1 goes high (Fig. 6A) and Φ2 is already low before the end of period t1. From then on, it becomes low (Figure 6B). The input signal (FIG. 6D) has risen to a high level representing a binary "1", so the output signal 1 of inverter 51-1 is at a low level. Output signal Q of inverter 52-1
1 is still in a low state because the pass transistor 55-1 is cut off by the low level Φ2 signal. After a certain period of time in the second period, Φ1 goes low first, and after a short time Φ2 goes high. At this time, the output signal 1 passes through the pass transistor 55-1 to the inverter 52-1.
1 and pushes the output signal Q1 from inverter 52-1 to high level.

Q1 is high level and pass transistor 5
3-2, the previous low level signal of Q1 has pushed the output signal 2 of inverter 51-2 to high level, and the pass transistor 5
As Φ2 changes from a low level to a high level in the latter half of the period t2 to enable the inverter 52-2, the output signal Q from the inverter 52-2
2 is pushed low. In this way, the input signal on lead 58 (FIG. 6D) is transmitted to each storage cell 5-1, 5-2, 5- in the shift register.
3, etc.

Once the desired information is transmitted to the shift register,
The hold signal (FIG. 6C) is enabled (i.e., pulled high) and the feedback lead 50- from the output lead of the inverter 52 is
1, 50-2, 50-3, etc. are connected to the input leads of the inverter 51, and information is semi-permanently held in each cell. In actual operation, the signals stored in a particular cell, e.g. 5-1, are connected to a configuration control circuit or an interconnect path device.

Shift register output signals Q1, 1, Q2,
Q2, etc. are connected directly to (configuration) control inputs of logic elements or to pass devices of the general interconnection junction.

When Φ1 is low, the data can be held semi-permanently by pushing Φ1 and the hold signal high. By setting Φ1 and Φ2 high and holding low, the entire shift register can be set or cleared by setting or clearing the input of the shift register. A certain set/reset time is required for this signal to clear the entire shift register and each register. Of course, this time depends on the overall length of the shift register.

In the dynamic process of the shift register,
The information to be shifted is stored as a charge on the gate of a transistor (not shown in FIG. 5, but known) having inverters 51-1, 52-1, 51-2, 52-2, etc. of a shift register. It operates as follows. These inverters are of known type and detailed description thereof will be omitted. It makes sense to use a dynamic shift register because it uses six transistors and therefore requires less area. The dynamic shift register is 1
It can be changed to a static clutch by simply adding one transistor. Therefore, dynamic shift registers (static clutches) can be easily fabricated as part of configurable logic elements without significant circuit complexity and without requiring much semiconductor area. A dynamic shift register can be a static latch because of the presence of the hold signal and because holding the shift register automatically refreshes the data. A separate refresh circuit is therefore unnecessary.

From the above it can be seen that the dynamic shift register (static latch) does not need to be refreshed once it is latched into the hold state. This can be accomplished, for example, by using a feedback circuit including lead 50-1 and pass transistor 54-1 of storage cell 5-1.

FIG. 7 shows the configurable combinational logic circuit 1
00, a configurable logic element 99 according to the present invention having a configurable storage circuit 120 and a configurable output selection logic circuit 140
FIG. Combinational logic circuit 100
receives N binary input signals applied to configurable logic element 99 and M binary feedback signals from storage circuit 120.
Combinational logic circuit 100 can be configured into multiple configurations.
Each state may implement one or more selected combinational logic functions as one or more selected subsets of the input signals to the combinational logic circuit. Since the configuration of combinational logic circuit 100 is changeable, it can be used to implement a plurality of different functions. Moreover, two or more functions can be implemented simultaneously and appear on different output leads of the configurable logic element 100.

Specifically, the combinational logic circuit 100 has M+
K out of N binary input signals (K≦M+N)
Select a binary input signal. The combinational logic circuit 100 includes first
and a second set of values such as to realize a second set of functions that is not equal to the first set of functions. A first set of configuration control signals corresponds to a plurality of sets of values.

In some embodiments, combinational logic circuit 100
is 2〓〓 as a function of K binary signals
(2〓〓K) A first configuration such that one of ( ₂ 2 ^k ) binary values is selected, and K
2〓〓[2
〓〓(K-1)] (i.e. ₂ 2 ^(K-1) ) values and a second K-1 input selected from the K selected binary input signals. and a second configuration for selecting one of 2〓〓[2〓〓(K-1)] binary values as a function of the signal. (The second set of K-1 signals is
It does not necessarily have to be different from the first K-1 signals. ) Such a combinational logic circuit 10
0 will be more easily understood by referring to the embodiment shown in FIG. 8, which will be described later.

The memory circuit 120 is also changeable in its configuration, and can be configured, for example, as a transparent latch circuit with set and reset, a D flip-flop circuit with set and reset, or an edge detection circuit. , a stage of a shift register, a stage of a counter, etc., can be programmed to implement one or more storage elements. The configurable storage circuit 120 has bus 1
61 and a clock signal selected from the N input signals of the combinational logic circuit on input bus 160. Output selection logic circuit 140 is configured to provide an output signal as a selected signal from the output signals of the combinational logic elements and storage circuits.

FIG. 8 shows one embodiment of the configurable logic element shown in FIG. In FIG. 8, the four input signals of configurable logic element 99 are shown as A, B, C and D (ie, N=4). Since memory circuit 120 only supplies one feedback signal Q to switch 107, M=1. In FIG. 8, signals A, B and C and D or Q are divided into five signals A, B, C, D
and Q, so K=4. The combinational logic circuit element 100 includes configurable switches 101 to 107, 113, 114, 8 bits.
RAM108 and 109, 1-8 selection logic circuit 1
10, 111, multiplexer 112, and configuration control leads 115 for switches 113 and 114. As described above, each configurable switch is configured by control bits from a program register (not shown) on the leads (leads other than lead 115 are not shown). Switch 101 can be configured to provide signal A as its output signal or to provide signal B as its output signal. Similarly, switches 102 to 10
7 can be configured to supply a selected one of its two input signals as its output signal.

Thus, for example, if a certain selection is made as the configuration control bits, switch 1
07 supplies signal D, and binary signals A, C and D are applied to switches 101-10 for 1-8 selection logic circuit 110 and 1-8 selection logic circuit 111.
3,104-107. For each of the eight possible combinations of binary signals A, C and D, selection logic 110 selects RAM 10
Select a different storage element within 8 and output the bit stored in the selected position. The 1-8 selection logic circuit 111 performs a similar operation for the 8-bit RAM 109. Multiplexer 112 provides an output signal from selection logic circuit 110 or an output signal from selection logic circuit 111 depending on the state of signal B. In this configuration, a control bit applied to lead 115 causes switches 113 and 114 to combine the output signals from multiplexer 112 into combinational logic element 100.
The signal is transmitted simultaneously to the output leads F1 and F2. Two 8-bit RAMs 108 and 109
can be programmed into 2 = 16 different states using binary bits. 2〓〓16=2〓〓 for the four binary variables A, B, C and D, depending on the state programmed into the 8-bit RAM.
(2〓〓4) Any one of the possible logical functions
Both can be realized by the configurable logic element 100. In this case K=4 and the logic function consists of a function of binary variables with binary values.

If another combination of configuration control bits is selected, switch 107 provides feedback signal 9 from storage circuit 120 to switch 101-103 and 104-107, 11.
The configuration of 3,114 is the same as above. The configurable logic element 100 is
For each program state of the two 8-bit RAMs 108 and 109 four binary variables A, B,
2〓〓16=2〓〓(2〓〓4) in C and Q
implement any one of the following possible logical functions. In this case too, K=4.

If a different configuration control bit is selected, switches 101-103 provide signals A, C, and Q, and switches 104-10
6 provides signals B, C and Q, and a control signal applied to leads 115 connects switches 113 and 11.
Select circuit 1 is connected to lead F2 by switching 4.
10 output signal and select circuit 1 to lead F1.
11 output signals respectively. In this way, on read F1, three binary variables A,
2〓〓8=2〓〓(2〓〓
3) Realize any of the following logical functions and write the three binary variables B, C, and Q for each of the eight program states on read F2 as follows: (2〓〓3)
Realize any of the logical functions.

Generally, 3 variables are selected from the 4 variables A, B, C and D/Q as the first selection, and 3 variables are selected from the 4 variables A, B, C and D/Q as the second selection. 8-bit
RAM 108 2〓〓3 variables chosen as the first choice on lead F2 for each of the 8 possible program states 2〓〓(2〓〓3)
Realizes standard logical functions and uses RAM 109/2.
〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 〓 Each configuration of the configurable logic element 100 exists.

In another embodiment not shown, the variables A,
Two 1-4 select logic circuits in each 8-bit RAM to implement any four binary functions on two variables selected from B, C and D/Q to four additional output leads of the configurable logic element. Each 8-bit RAM is repartitioned to add . Similarly, in another embodiment not shown, a 32-bit RAM, signals A,
The configuration is such that B, C, and D, and the feedback signal Q all realize one of 2〓〓 (2〓〓5) binary functions corresponding to each program state of the 32-bit RAM. Used to enable oscillation. (In this case N=4, M=1 and K=5). For other configurations not shown,
N=4, M=1 and K=5, and variables A and B
and the first binary function for C, variable B,
A second binary function F2 for C and D and a third binary function F3 for variables B, C, D and Q are realized. The important thing here is that 2 ^K1 ′+2 ^K2 ′+2 ^K3 ′=2 ^K (Ki′ is the function Fi for i=1, 2, 3)
is the number of variables. ) is established.

8, it is important to note that configurable switches 101, 102 and 103 select a subset of these input signals and direct the subset of input signals to selected input leads of circuit 110. The point is that it is supplied with a one-to-one correspondence. For example, in response to one set of values of the configuration control signal, the configurable switch 10
1, 102 and 102 lead signal A 110
-3, signal B is applied to lead 110-2, and signal C is applied to lead 110-1.

The output signals on leads F1 and F2 are input signals to configurable storage circuit 120. Signals A, C, and D are also input signals to the storage circuit 120. Configurable memory circuit 120
are programmable switches 122, 123, 1
26-128, exclusive OR gate 12
4, 129 and 130, AND gate 125, 1
31 and 132, and a storage element 121.
The storage elements 121 are S, R, D and Ck, respectively.
It has set, reset, data and clock input leads as indicated by
Has QFF and QLA.

The switches 123, 126-128 are each configured to select one of the respective input signals as an output signal. The SET, CLOCK and RESET functions corresponding to the SET, CLOCK and RESET input leads of storage element 121 are all in a high state and apply logic 1 signals to the INVS, INVC and INVR leads of exclusive OR gates 124, 129 and 130, respectively. Possibly switches 123, 127 and 12
It can be set to a low state for the output signal of 9. A logic 0 signal leads INVS, INVC and
Exclusive OR if added to INVR
The polarity of the output signals of gates 124, 192 and 130 will be equal to the polarity of the input signal. logic 1 signal
When added to INVS, INVC and INVR leads,
The output signals of exclusive OR gates 124, 129 and 130 are inverted signals of the input signals.

AND gates 125, 131 and 132 are enabled by applying logic 1 signals to the ENS, ENC and ENR leads. A logic 0 signal applied to these leads disables these gates. When a logic 0 signal is applied to any one of the input leads ENS, ENC or ENR, the output of the AND gate becomes a logic 0 level,
The corresponding function of the memory circuit 121 is the corresponding OR
Disabled regardless of gate state. QFF generates the flip-flop output signal and QLL provides the latch output signal as described above with respect to FIG. Configurable switch 122 selects one of the binary signals of leads QFF and QLA, and output signal Q of switch 122 becomes an input signal to output selection logic circuit 140 and configurable combinational logic circuit 100.

FIG. 9 shows one embodiment of the memory circuit 121. Storage element 121 consists of two D latches LA1 and LA connected in series to form a flip-flop.
It has 2. Latch LA1 includes N-channel pass transistors P1 and P2 and NOR gates G1 and G2. The gates of pass transistors P1 and P2 are controlled by signals Ck and k. Similarly, latch LA2 connects N-channel pass transistors P3 and P4 and NOR gate G3.
and G4. The gates of transistors P3 and P4 are controlled by signals Ck and k. The D input lead is the data input lead for latch LA1. The S input lead functions as the set input lead for latch LA1 and the reset input lead for latch LA2. The R input lead functions as the reset input lead for latch LA1 and the set input lead for latch LA2.

The output signal LA of NOR gate G1 is the latch
Connected to LA2 data input lead. Output lead QLA is the NOR gate G of latch LA1.
The output lead QFF is connected to the output lead of
Connected to the output lead of NOR gate G3 of latch LA2.

Configurable memory circuit 120 (Figure 8)
The switch 122 functions as a transparent latch with a set and a reset by configuring the switch 122 to connect output leads Q and QLA. Read while clock signal Ck is low
The output signal of QLA follows the input signal. When clock signal Ck goes high, the output signal of QLA is held, cutting off pass transistor P1 and making pass transistor P2 conductive.

Memory circuit 120 can be configured to function as a D flip-flop circuit with set and reset. In this condition, switch 126 is configured to select the signal on lead F1, and gates 125, 131 and 132 read the logic 1 signal.
Enabled by adding to ENS, ENC and ENR. Finally, the configuration of the switch 122 reads the memory element 121.
It is defined to select the QFF output signal.
Storage element 120 can be configured as a D flip-flop circuit without set and reset by modifying the configuration described above by applying a logic 0 signal to leads ENS and ENR.

Configurable storage circuit 120 is configured to be an R-slatch by enabling AND gates 125 and 132 and disabling AND gate 131 such that a logic 0 input signal is generated on the Ck input lead of storage element 121. I can do it. A logic 0 signal on lead Ck is
Pass transistor P3 is cut off and pass transistor P4 is made conductive. Next, switch 1
22 is configured to select the output signal on the QFF.

Finally, storage circuit 120 can be configured to function as an edge detection circuit. For example, if storage element 120 is configured as a rising edge detection circuit, AND gate 125 is disabled by applying a logic 0 signal to input seed S, AND gate 131 is enabled and the clock signal is transmitted to input lead Ck. switch 126 connects input lead 126 such that a logic 1 signal is applied to input lead D.
is configured to select a. AND gate 1
32 is enabled. The logic 1 reset signal pushes the output signal on the QFF below the logic 0 signal.
If the clock signal is low, pass transistors P2 and P3 are cut off and pass transistor P1
conducts. As a result, NOR gate G1 inverts the logic 1 signal on lead D and produces a logic 0 signal on node LA. When the clock signal is pulled high, transistors P1 and P4 shut off, transistors P2 and P3 conduct, and the logic 0 signal on node LA is inverted by NOR gate 23, creating a logic 1 signal on output lead QFF. is generated, and as a result, a rising edge is detected. The reset input is then used to reset QFF to 0, and the edge detection circuit is ready to detect the next rising edge. When the clock signal is pressed down, transistors P2 and P3 are turned off, transistor P4 is turned on, and the signal on QFF remains in a logic zero state and does not change state until the next rising edge.

Similarly, storage circuit 120 can be configured to become a falling edge detection circuit by applying a logic 1 signal to the INVC lead of exclusive OR gate 129. Similarly, storage circuit 120 can also function as a shift register or a stage of a counter.

The output selection logic circuit 140 is the combinational logic circuit 1
It has configurable switches 141 and 142 so as to be configurable to select one signal from the output signal obtained from 00 and appearing on leads F1 and F2 and the output signal of storage element 120.

Configurable logic circuit 9 shown in FIG.
9 is not suitable for communicating with a microprocessor. For example, if it is desired to write data from a microprocessor to store data in storage element 121, storage element 121 is unavailable to receive other output signals from combinational logic element 100. Moreover, communicating between a microprocessor and a configurable logic element array consisting of a plurality of configurable logic elements, each corresponding to configurable logic element 99, requires an overall interconnection that reduces the diversity of the logic array. Requires structure.

FIG. 10 shows a configurable logic element 210 according to the present invention, which is made by modifying the configurable logic element 99 shown in FIG. 8 to be suitable for application in a microprocessor. Configurable logic element 210 includes all of the circuitry shown in FIG. 8 plus latch 205, programmable switches 201-204, 206, and
state buffer 208.

Information is stored in the latch 205 by applying a write signal to the lead WR _Y connected to the input lead G of the latch 205, and the signal to be stored is transmitted to the input lead D via the sending direction data lead DB _X. . Configurable switches 201-204 for appropriately configuring (programming) the Q output leads of latch 205 as desired.
It can be connected to any of the input leads A to D. These connections can be accomplished using pass transistors or other well-known switching elements as shown in FIG. For example, switch 202 may be configured to connect output lead Q to input lead C. Generally, switches 201-204 are constructed from control bits of programmable registers (not shown) connected to the configurable switches by leads (not shown).

Similarly, switch 206 also connects configurable switch 206 via a lead (not shown).
control bits of a program register (not shown) connected to 06. switch 2
06 may be configured to connect selected ones of leads 206a-206d to output lead 207. In this manner, switch 206 supplies either the signal stored in latch 205, the output signal of configurable combinational logic circuit 100, or the signal stored in storage circuit 121 to lead 207 as an output signal. The user determines which of these three signals is to be supplied by switch 206.

When a read signal is provided on lead _RDY , tri-state buffer 208 is enabled. When enabled, tristate buffer 208 provides the signal on its input lead 207 to bidirectional data lead _DBX . When not enabled, the output of tristate buffer 208 is in a high impedance state. The state of tri-state buffer 208 is controlled by the level of the signal on _RDY in well known manner. In this way, latch 206 is constructed and 3
By enabling state buffer 208, the user can configure configurable logic element 210
Check the status of selected important internal signals of, for example, the status of any output signal of the combinational logic circuit 100, the status of the output signal of the memory circuit 121, or the status of the signal stored in the latch 205. Can do (read).

FIG. 11 shows a configurable logic element that is the same as configurable logic element 210 of FIG.
A chip 300 is shown with an 8x8 configurable logic element array consisting of CLE(x,y) (x,y=0,...,7). (In an alternative embodiment not shown, some of the configurable logic elements in the array shown in FIG. (Identical to the configurable logic elements shown.) A microprocessor interface structure 180 generates read/write signals to operate registers R ₀ -R ₇ . Register R _Y has eight state-settable logic elements or configurable logic elements CLE (x, y) (x=0, . . . , 7).
Each configurable logic element is identical to configurable logic element 210, and each configurable logic element is connected to the lead 14 shown in FIG.
3,144 can be configured to provide different output signals. The output leads and overall interconnect structure of the configurable logic elements are omitted from illustration in FIG.

The configurable logic element array adapted to the microprocessor shown in FIG. Storage element 121 can remain available without monitoring internal signals or using any of the interconnect structures of configurable logic element array 300 (not shown in FIG. 11). It has high flexibility.
Also, in implementing the microprocessor interface logic circuit 180, it is not necessary to utilize any of the logic functions implemented by the configurable logic elements in the array.

Microprocessor interface logic circuit 180 has three types of input buses. That is, it has a bus 310a for receiving address signals, a bus 310b for receiving chip enable signals, and a bus 310c for receiving control signals. Microprocessor interface logic circuit 180
The output signal becomes a read/write signal on bus 301 whose dimensions depend on the number of registers used. In this case, bus 301 has eight leads.
It has a read and 8 write/reads.

Blocks ₁₉₀₀ to ₁₉₀₇ with bidirectional buffers for each data line _DB0 to _DB7 and microprocessor interface logic 180
is shown in more detail in FIG. In this embodiment, the address bus 310a provides a 3-bit address to the microprocessor interface logic 180 that is to be read or written in FIG. specific register
Generate a signal to select R _y . lead 3
10b provides a chip enable signal to microprocessor interface logic circuit 180. Control bus 310c has the read and write signals shown in FIG.
D, generates an input-output signal on lead I/ that determines the state of three-state buffers 109 ₀ -109 ₇ . For the first select signal generated on lead I/, the signal is
0 to data leads DB ₀ -DB ₇ shown in FIG. 11 via buffers 190A ₀ -A ₇ .
For the second selection signal of read I/, the data signal is transferred from bus DB ₀ to DB ₇ to buffer 190B ₀ to
The data is transferred to the microprocessor 310 via _190B7 .

13 and 14 are timing charts showing the read cycle and write cycle of the chip 300.

FIG. 15 shows a system using the configurable logic element array chip 300 for a microprocessor shown in FIG. The portion of the system shown in FIG.
0, a RAM/ROM memory 312, a decoder 305, a printer 315, and a configurable logic element array 300. In this example,
Configurable logic element array 300 is used to interface microprocessor 310 to printer 315. Configurable logic element arrays in such systems replace traditionally used small scale integrated circuits (SSI), medium scale integrated circuits (MSI), or large scale integrated circuits (LSI). The microprocessor uses ROM/RAM memory 312
Execute the program stored in the . The configurable logic element array 300 receives commands from the microprocessor 310 available on the data bus, generates appropriate printer control signals, and transfers the signals to an I/O pad similar to that shown in FIG. 4a. It is supplied to the lead 315a via an I/O pin (not shown in FIGS. 11 and 15). Configurable logic element array 300 receives data to be printed on a data bus from microprocessor 310, adapts the data format to the printer as needed, and provides the data to printer 314 via lead 315B. do.
Status signals from printer 314 are provided to leads 315c of configurable logic element array 300. The states of the three status signals are determined by the microprocessor 310 via the data bus when the microprocessor 310 reads the appropriate register in the configurable logic element array 300.
Transferred to 0.

Although the preferred embodiments of the present invention have been described above,
Those skilled in the art can implement the present invention with various modifications and changes without departing from the concept of the invention.

[Brief explanation of drawings]

FIG. 1 illustrates some of the various logic functions that may be implemented by configurable logic elements within a configurable logic array. FIG. 2 shows the internal logical structure of one possible embodiment of a configurable logic element such that a useful number of functions for two variables A, B can be realized. Figure 3A shows 16
A system that can specify any input state and realize 2 to the 16th power of functions.
Shows 16-bit RAM. FIG. 3B shows a selection structure for selecting any one of the 16 bits to be transmitted to an external terminal such that 2^16 functions can be realized. FIG. 3C shows one possible Karnaugh map for the structure of FIG. 3A.
FIG. 3D shows a logic gate when a binary 0 is placed at the intersection of the first and second rows and the first column in the Karnaugh map of FIG. 3C. 4th A
The diagram shows programmable interconnect lines formed between selected leads and selected input/output pads between logic elements and lead interconnect lines formed on an integrated circuit chip to achieve the desired logic function. 9 shows a plurality of configurable logic elements made up of nine logic elements. Figure 4B shows the fourth
This key represents the connection state of the intersecting leads in Figure B. FIG. 5 shows a portion of a novel combinational static and dynamic shift register circuit that can be used with configurable logic elements according to the present invention. Figures 6A to 6H are the 5th
FIG. 3 is a waveform chart for showing the operation of the structure shown in the figure. 7th
The figure shows configurable logic elements according to the invention. FIG. 8 shows one embodiment of the configurable logic element of FIG. FIG. 9 shows one embodiment of storage element 121 of FIG. FIG. 10 shows one embodiment of a configurable logic element suitable for application in a microprocessor according to the present invention.
FIG. 11 shows a chip using the array of configurable logic elements shown in FIG. 1st
FIG. 2 is a circuit diagram schematically illustrating a microprocessor interface logic circuit 180 for the array of configurable logic elements shown in FIG. FIG. 13 shows the circuit 30 shown in FIG.
2 is a timing chart showing the timing of a read cycle for 0; FIG. 14 is a timing chart showing the timing of write cycles for circuit 300 shown in FIG. FIG. 15 is a circuit diagram illustrating a system using the chip shown in FIG. 11 with a microprocessor and storage elements. 21, 22...Inverter, 25...AND gate, 26...NOR gate, 29...Transistor, 201-204, 206...Programmable switch, 205...Latch, 208...3-state buffer, 180...Micro Processor interface logic circuit, 210... configurable logic element, 300... configurable logic element array, 310... microprocessor, 3
15...Printer.

Claims (1)

[Scope of Claims] 1. A logic element whose configuration can be changed, comprising: means for receiving N first binary input signals; means for receiving M second binary feedback signals; and said M+N means for selecting K (where K≦N+M) signals from among the K binary signals; and a means for selecting K signals from among the K binary signals; configurable combinatorial logic means receiving a plurality of binary signals; and a selected one of the binary output signals of the configurable combinatorial logic means and a first a first configurable storage circuit for receiving a selected one of the M binary input signals and generating the M second binary feedback signals; A reconfiguration comprising means for receiving a binary output signal and said M second binary feedback signals of said first reconfigurable storage circuit, and means for selecting an output signal from the signals received by said means. means for reading the state of a selected one of the binary output signal and the M second binary feedback signals of the configurable combinational logic means; A logical element whose configuration can be changed, characterized by comprising: 2 a second storage circuit for storing a data signal and providing an output signal corresponding to the stored signal; and receiving an output signal of the second storage circuit and transmitting the output signal to one of the N first binary inputs configurable means for supplying said means for receiving a signal such that the output signal of said second storage circuit is any of said N first binary input signals. A logic element whose configuration can be changed according to claim 1. 3. The structure according to claim 2 is changeable, wherein the means for reading the state of the signal includes means for reading the state of the output signal of the second storage circuit. logical element. 4. The means for reading the state of a signal has a plurality of configurations and receives the binary output signal of the reconfigurable combinational logic means and the M binary feedback signals, and configurable switch means for receiving signals from said configurable storage circuit and, when enabled, providing signals representing different signals among said received signals; 2. A reconfigurable logic element as claimed in claim 1, further comprising a three-state buffer for generating an output signal representative of . 5. A reconfigurable logic element comprising: means for receiving N first binary input signals; means for receiving M second binary feedback signals; means for selecting K signals (wherein K≦N+M) from the selection means; and a plurality of configurations for generating the selected binary output signals;
configurable combinatorial logic means receiving a plurality of binary signals; and a selected one of the binary output signals of the configurable combinatorial logic means and a first a first configurable storage circuit for receiving a selected one of the M binary input signals and generating the M second binary feedback signals; A reconfiguration comprising means for receiving a binary output signal and said M second binary feedback signals of said first reconfigurable storage circuit, and means for selecting an output signal from the signals received by said means. a second reconfigurable storage circuit that stores a data signal and provides an output signal corresponding to the stored signal; N
and configurable means for supplying said means for receiving binary input signals. 6 means for receiving N first binary input signals, means for receiving M second binary feedback signals, and K signals from among the M+N binary signals (K≦N+M); reconfigurable combinatorial logic means having a plurality of configurations for generating a selected binary output signal and receiving said K binary signals from said selection means; and a selected one of the binary output signals of the configurable combinational logic means and the N first
a first configurable storage circuit for receiving a selected one of the M binary input signals and generating the M second binary feedback signals; A reconfiguration comprising means for receiving a binary output signal and said M second binary feedback signals of said first reconfigurable storage circuit, and means for selecting an output signal from the signals received by said means. a second reconfigurable storage circuit that stores a data signal and provides an output signal corresponding to the stored signal; a plurality of configurable logic sub-elements each having configurable means for providing to said means for receiving N binary input signals; and means for selectively communicating to a storage circuit. 7. said means for selectively communicating data signals receives address and control signals from a microprocessor, and a write signal for determining which of said second storage circuits is to store a data signal; 7. A reconfigurable logic element according to claim 6, characterized in that it has a microprocessor interface circuit for generating. 8. The reconfigurable logic element according to claim 7, wherein the reconfigurable logic sub-elements are arranged as a rectangular matrix. 9 means for receiving N first binary input signals, means for receiving M second binary feedback signals, and K signals (K≦N+M) from among the M+N binary signals; reconfigurable combinatorial logic means having a plurality of configurations for generating a selected binary output signal and receiving said K binary signals from said selection means; and a selected one of the binary output signals of the configurable combinational logic means and the N first
a first configurable storage circuit for receiving a selected one of the M binary input signals and generating the M second binary feedback signals; A reconfiguration comprising means for receiving a binary output signal and said M second binary feedback signals of said first reconfigurable storage circuit, and means for selecting an output signal from the signals received by said means. means for reading the state of a selected one of the binary output signal and the M second binary feedback signals of the reconfigurable combinational logic means; a configurable logic sub-element comprising: a configurable logic sub-element for selecting a particular one of said means for reading the state of a signal and for supplying the signal read by said particular reading means to a data bus; A logical element whose configuration can be changed, characterized in that it has a means. 10. A reconfigurable logic element according to claim 9, wherein said selection means includes a computer interface circuit. 11 A reconfigurable logic element comprising: means for receiving N first binary input signals; means for receiving M second binary feedback signals; means for selecting K signals (wherein K≦N+M) from the selection means; and a plurality of configurations for generating the selected binary output signals;
configurable combinatorial logic means receiving a plurality of binary signals; and a selected one of the binary output signals of the configurable combinatorial logic means and a first a first configurable storage circuit for receiving a selected one of the M binary input signals and generating the M second binary feedback signals; A reconfiguration comprising means for receiving a binary output signal and said M second binary feedback signals of said first reconfigurable storage circuit, and means for selecting an output signal from the signals received by said means. means for reading the state of a selected one of the binary output signal of the configurable combinational logic means and the M second binary feedback signals; , a second storage circuit for storing a data signal and providing an output signal corresponding to the stored signal; and receiving an output signal of the second storage circuit and transmitting the output signal to one of N first binary inputs. and configurable means for supplying the signal to the means for receiving a signal, such that the output signal of the second storage circuit is any of the N first binary input signals. A logical element that can be changed.