JPH0445682A - Compressed picture data reproducing system - Google Patents

Abstract

PURPOSE:To shorten waiting time when moving from a high-speed reproducing state to a standard-speed or slow reproducing state by holding a picture data under reproducing at high speed in a storing means until reproducing the next picture. CONSTITUTION:Each time reproducing and decoding the encoded data of a frame to which inter-frame encoding is executed, switching circuits 11 and 12 are changed over and the picture data of the next frame is generated from the picture data to be read from one of frame memories 9 and 10 and the reproduced and decoded inter-frame difference data, and written into the frame memories 9 and 10. When outputting the request of moving from the high-speed reproducing state to the standard-speed reproducing state, the encoded data is reproduced from the next frame of the display picture and decoded to prepare the picture data of the next frame. Therefore, since it is not necessary to reproduce and decode the encoded data having a large data amount, the waiting time from the request of moving to the standard-speed reproducing state to the execution of this reproducing is shortened, and standard-speed reproducing is quickly executed.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a method for reproducing moving images compressed and recorded on a recording medium, and in particular, the present invention relates to a method for reproducing moving images recorded on a recording medium by compressing data, and in particular, a pressure 111 method that enables standard speed playback, slow playback, and high speed playback according to user specifications. [1
Concerning one-image data reproduction method 2.

[Prior art] As a conventional method for reproducing O-pressure j1vI4 image data, for example, there is
0(198?)P, 1104-1111, a system described in a paper titled "Study of a recording-based moving image reproduction system using an interframe coding method" is known. This system uses CDs, which are large-capacity digital recording media.
- Long-term recording of moving image data in ROM is realized by data compression through encoding. The encoding method in this case is a hybrid encoding method that combines a frame-by-frame predictive encoding method and an orthogonal transform encoding method, with a rate of 69%.
Orthogonal transformation (hereinafter, D C'! (Disor*t+@C
owin@Transor-m)) and the nine-frame differential signal is quantized, variable-length coded, and recorded. Furthermore, adaptive intra-frame coding and motion-compensated frame-to-frame coding using motion vectors are basically performed. FIG. 8 is a schematic block diagram showing such image data O decoding mt. Here, for the sake of simplicity, motion compensation is not shown, and the interframe difference signal is simply expressed. I
Only the portion that is added to the 1111 image data of I to restore the original image data is shown. In the same figure, 1 is a variable length decoding circuit, 2 is an inverse quantization circuit, 5 is an inverse orthogonal transform circuit, 4 is an addition circuit, 5 is a switching circuit, 4 is a digital port frame memory, and 7 is for output. Frame memory, 8 is D
/A conversion theory. 15 shown in Figure 19 shows the 7v frame of frame number 1 that has been intra-frame encoded (hereinafter, the frame 14t1 is referred to as frame 1) - image data The following frame inspection coded frames 2 to 10 The operation of this decoder will be explained in the case where coded data consisting of frame differential data 2 to 10 corresponding to 1 is sequentially reproduced and decoded from a large capacity digital record. First, as shown in FIG.
, an inverse quantization circuit 2, and an inverse orthogonal variation 111 circuit S. Here, since this internal data is intra-frame encoded data, the switching circuit S selects the output data of the inverse orthogonal transform circuit s as is by the switching signal SW. Then, the frame 10 decoded conceited data output from the switching circuit S is written into the frame memory 6 and the output frame memory 7, as shown in FIG. Difference data 2'
When the encoded data of Therefore, in response to the switching signal SW, the switching circuit 5 selects the output data of the adding X circuit 4. The decoded ego data of the frame 1 that has already been written is read out from the frame memory 6 in synchronization with the output data of the inverse orthogonal transform circuit S, and this image data and the frames of frame 2 and frame 1 are read out from the frame memory 6 in synchronization with the output data of the inverse orthogonal transform circuit S. Inverse alternation that is a difference signal between! The adder circuit 4 adds the output data of the l11 circuit S to restore the decoded 01iii image data of frame 2. That is, as shown in diagram M9, the inter-frame difference data 2' and the image data of frame 1 are added, frame 2C) II image data is decoded, and written into the frame memory 6 and the output frame memory 7. . Then, by repeating the above, the new image data obtained from the adder circuit 4 is seen in the frame memory 6, and
These new images f-me are written in the output memory 7, read out at a standard television speed, and converted into an analog O video signal by the D/^ conversion m8 for display. The above operation is for standard speed playback, but next, the case of high speed playback will be explained. In this case, it is necessary to thin out the frames, that is, to decode them into multiple frames, but when using the frame inspection encoding method as described above, lI? 5! I
As shown in the figure, every other frame, such as frames 1 and 11°-1, is intra-frame encoded, and the other frames are inter-frame encoded, so if the frame to be decoded is arbitrary, then The original image data cannot be decoded. Therefore, as shown in Figure 10g, by thinning out and decoding 11 frames for high-speed playback and encoding them using intra-frame encoding, these frames can be decoded independently and played back at high speed. Realization slows down. As mentioned above, during high-speed playback, the image data tSa recorded in a large-capacity digital storage system is not sequentially read out and decoded, but must be decoded into multiple frames sp@. Large capacity digital record ii
G body, 4? In the case of KCD-10M, it is necessary for the head to reproduce image data while performing track jumps to move between recording tracks. Therefore, there is a waiting time from when an access request for a frame for image display is made until the requested image data is reproduced. In addition, the image data decoded for high-speed playback # is intra-frame encoded frame data63>, and since the data compression rate is lower than that of frame-related encoded frames and the amount of data is large, the intra-frame It takes a plurality of frame times t to reproduce and decode the encoded frame of image data. Therefore, for the sake of simplicity, as shown in Figure 11,
- The waiting time from when there is a frame access request to display an image until the image data of this frame starts to be played back is t57, and when this intra-frame encoded 9-frame OIi image data starts playing. Assuming that the waiting time tr until decoding is 5 hours, it takes 10 frame hours tl from requesting 17 times 5 image data access to displaying both images during high-speed playback. I will do it. Therefore, for example, if t is used for 8x high-speed playback, as shown in Figure 10, frame 0. frame 8
0. Every 80th frame must be intraframe encoded, such as frame 160, -1,
Frame 0-image data that has been intra-frame encoded for each 0 frame will be reproduced. That is, as shown in Figure 11, after frame Ot is played back and decoded, frame five 80t is played back and decoded, and then frame 140t is played back and decoded. Then, the decoded nine-dimensional image is sequentially displayed as a stationary image for a period of t a + t r. Here, the process of moving from the high speed playback state to the standard speed playback state in the prior art will be explained. While viewing the display with high-speed playback +
When the omt image is displayed, an instruction request for standard speed playback is made. Now, in Figure 11, tree five 8001! If a standard speed playback instruction request is made while # is displayed, the user is expecting the next standard speed image display from 7-ray 581. However, when the frame 5ooIi image is being displayed, the frame 14001iii1m data has already been reproduced and the decoding operation has started, and therefore the frame 160 is stored in the output frame memory 7 in the frame memory 6 in FIG. Decoded image data is being written. Therefore, when a user requests an instruction to shift to standard speed playback, frame 81 is encoded using the frame Goyaku encoding method, which has a high compression rate, and the encoded data corresponding to frame 81 is the same as that of frame 80. Since this is differential data,
The original image data cannot be decoded only with the encoded data of this frame, and the decoded data of the frame honor code 80 is required. Therefore, the frame must be reproduced from 5800 encoded data that have been intra-frame encoded. Therefore, as shown in $111 tE, if an instruction to shift to standard speed playback is received while the image of frame 80 is being displayed in high speed playback, the encoded data of frame 800 is played back and decoded again. The image is then written to the memory 6 or the output memory 7 again and displayed as an image. The time required for this is of course ta+tr, which is 0th order, and frame 8.
1 encoded data is reproduced. The encoded data of frame 81 is stored in frame 8o in the large-capacity Digimel recording system.
Since it is recorded adjacent to the encoded data of frame 81, there is no need for a track jump, and the access request of frame 81 is recorded adjacent to the encoded data of frame 81. The waiting time ta from when the encoded data is requested to when the encoded data is played back can be almost ignored, and since it is encoded using the frame-related encoding method, the compression rate is high and the amount of data is small. The time %@r required to reproduce and decode the encoded data of 81 is smaller than the time Sr required to reproduce and decode the data tube of a frame internally encoded in 7 layers. Therefore, here time t
- If rf is one frame time, it will take one frame time t- to reproduce and decode the encoded data of the interframe encoded frame. When the encoded data of frame 81 is reproduced, it is decoded by variable length decoding circuit 1, inverse quantization circuit 2, and inverse quantization circuit 5. The image data of frame 81 is decoded by being added to the decoded image data of frame 80, and sent to frame memory 6 and output frame memory 7 via switching circuit 5.
will be written to. Then, when the encoded data of frame 820 that has been interframe encoded is reproduced in the next frame period, the same percentage filling as described above is performed, and the decoded internal image of frame 810 that was written to the output frame memory 7 immediately before. The data is output and displayed as an image. From now on, this operation is repeated, and standard speed playback can be achieved. [Problems to be Solved by the Invention] As described above, when there is a Klllll speed up play transition instruction request during high speed playback, standard speed playback is performed.
As shown in Figure 11, this transition is delayed by a time of ta+t r + t@r (11 frame periods in Figure 11) from the time when the request for transition to standard speed playback is made. For this reason, it takes a long time to wait until standard speed playback is executed in response to a user's request for a transition from high speed playback to standard speed playback, making it difficult for the user to use the system. An object of the present invention is to provide a method for reproducing pressure image data that eliminates such problems, eliminates the waiting time when transitioning from a high-speed reproduction state to a standard speed or slow reproduction state, and is user-friendly. It's about doing. [Means for solving the problem] In order to achieve the above object, the present invention retains the current display image during high-speed playback in a storage means until the next image is displayed, and The data to be read from the large-capacity Digimel recording system after a request to shift to standard speed or slow playback will be displayed when the request for standard speed or slow playback is received. The result of the decoding of the encoded data of the inter-frame encoded frame, and the image data stored in the storage means, as the encoded data of the inter-frame encoded frame. The image data of the image that should be displayed for a long time is restored by processing. [Function] By retaining the image data of the currently displayed image that is being reproduced at high speed in the storage means until the next image is displayed,
From a high-speed playback state in which only intra-frame coded coded data is decoded and played back, all frame O data coded using intra-frame coding and inter-frame coding methods are played back and decoded at standard speed or slow playback. When transitioning to the state, 4j! <When decoding coded data of an interframe coded frame, the coded data can be added to the image data stored in the previous frame storage means, so the user must There is no need to play back and decode the encoded data of the frame that is intra-frame encoded corresponding to the display being played back at the W& point, and there is no need to play back and decode it. Therefore, the waiting time when changing from the high speed playback state to the standard speed or slow playback mode can be shortened. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing an embodiment of the compression + rg + side data reproduction method according to the present invention, in which 9.10 is a frame memory, 11.12 is a switching circuit, 15 is an inverting circuit, 1
4 is a switching signal generation circuit, and parts corresponding to those in FIG. 6 are given the same reference numerals. Here, as shown in Fig. 10, encoded image data is recorded on a large-capacity digital recording medium such as a CD-ROM, and as with the prior art described above, high-speed playback is performed at 8x speed. During high-speed playback, it is assumed that the head is stopped until there is an access request for the next nine intra-frame encoded frames.Also, as in the prior art described above, the head is assumed to be stopped. For simplicity, the waiting time from the next intra-frame coded frame O access request to the start of playback of this frame is ta t-5.
5 hours, the waiting time from the start of reproduction of this frame to decoding is f15 tr f 57 frames, and the time required to reproduce and decode a 7-ray human encoded frame is t·rt1 frame time. However, in reality, in the case of a CD-ROM that rotates at a constant linear speed, the waiting time %a differs depending on the distance between recording positions of intraframe-encoded frames. Next, the operation of this embodiment when there is a request to shift to standard speed playback in high speed playback # will be described with reference to FIG. 7 between the a side of the switching circuit 11 and the b side of the switching circuit 12
A frame memory 10 is connected between the switching circuit 110h side and the switching circuit 12 a side! 12
Subsequently, the output signal of the switching circuit S is supplied to the switching circuit 11 and the frame memory 7, and the output signal of the switching circuit 12 is supplied to the adding circuit 4. During high-speed playback at 8x speed, a switching signal whose level is inverted in synchronization with the start of access by a head (not shown) is output from the switching signal generation circuit 14, and the switching circuit 12 is switched and controlled by this switching signal. Further, this switching signal is inverted in level by the inverting circuit 1S and supplied to the switching circuit 11.
1 is switched and controlled. Therefore, assuming that the period switching circuits 11 and 12 for reproducing and decoding frame O which has been intra-frame encoded by t% are closed in a manner, frame O output from the inverse orthogonal transform circuit S is decoded. Talll1
The print data is supplied to the frame memory 7 via the switching circuit 5, and is also supplied to the frame memory 9 via the switching circuit 5.11t and written therein. This 111g11 data frame memory 7! When writing is completed, this image data is read out from the frame memory 7 and the image of the frame is displayed.At the same time, there is a request to access the next intra-frame encoded frame 80, and the head switches to the track jump control. The switching circuits 11 and 12 also switch to the ripping side. After this access request, it takes a waiting time tal to complete the access of the next 7 rays 580, and in the next waiting time tr, the image data of this frame 80 is decoded and written to the frame memory 7.10 in the same way as above. It will be done. When the 7-ray memory 7 is read out and internal display of this frame 80 starts, the head starts accessing the next intra-frame encoded frame 160, and the switching circuit 1
1°12 switches to the 1 side. Then, when the access to frame 160 is completed, playback and decoding are started, but when a request to shift to standard speed playback is made during the waiting time tr for playback and decoding, frame 14
The head stopped at the reproduction position 0 starts accessing the intra-frame encoded frame 800 and the inter-frame encoded frame 81 recorded next, and at the same time, the switching signal generation circuit 14 Frame-wise encoded frame 81 since the head initiated this access
This occurs during the time t a +tar until the signal is reproduced, decoded, and output from the inverse orthogonal transform circuit 5, and a switching signal is generated to close the switching circuits 11 and 12i'a. Further, the switching circuit 5 is switched from the inverse orthogonal transform circuit '5ga to the adding circuit 4 side in response to the switching signal SW. In such a state, the inverse orthogonal variation! When the decoded inter-frame difference data of frame 81 is output from the 14 circuit 3, the frame memory 10 outputs the frame 8 in synchronization with this.
The decoded image data of 0 is read out and added by the adding circuit 4 to restore the image data of the frame 81. This image data is written into the switching circuit 5 and the frame memory 7, and further passed through the switching circuit 11 and written into the frame memory 9KI. When these inputs to the frame memory 7.9 are completed, the level of the switching signal from the switching signal generation circuit 14 is reversed, and the switching circuit 11.12 switches from the am side to the b side KgJ, and so on. , next frame related encoded frame B2
The 0 encoded data is reproduced and decoded. Then, when the decoded fl: frame difference data of this 0 frame 82 is supplied from the inverse orthogonal transform circuit 5 to the adder circuit 4,
The image data of frame 81 written earlier in the frame memory 9 is read out to generate conceited data of frame 82, which is written in frame 7.10. Similarly, the switching circuits 11 and 12 are switched every time the encoded data of the frame-related encoded frame is reproduced and decoded. The image data of the next frame is mainly assigned from the frame review difference data and written to the frame memories 9 and 100, respectively. In this way, when in the high-speed playback state, when an image for which you want to start standard-speed playback is displayed and a request to shift to it is issued, encoded data is played back and decoded from the next frame of this displayed image, and Since the image data of this display image is used to create the next 7 lines of II data of this display image, when a transition to standard speed playback is requested, a large amount of data is intra-frame encoded and played back in 9 frames. , there is no need for decoding, which reduces the waiting time from when a request to shift to standard speed playback is made to when this playback is executed.
Standard speed playback will occur quickly. With the conventional technology shown in Figure 8, it is not possible to shift to standard speed playback. O time ta + Sr + t from request to execution
@r is 5+5+1-m11 frame time-117s mouth (
α57)−・0, but in this example, ta+
t@rsm5-)-116 frame time review-4/! 10(
cL2) s@o, and 5 frame time review (α57s・
0) Shortened. 1115r! A is a block diagram showing a specific example of the switching circuit shown in FIG.
19 is a mode control circuit. In the figure, the counter 16 is the reference clock I generation circuit 1.
It outputs a signal whose level is inverted every time the count value reaches a value set by the mode control circuit 19. The output signal of the counter 16 is supplied to the b side of the switching circuit 18, and is inverted in level by the inverting circuit 17 and supplied to the a side of the switching circuit 18. When a high-speed reproduction mode is input, the mode control circuit 19 resets the counter 1dt, and the counter 16 is set to a predetermined value t-stage. As a result, the counter 16 operates according to the set predetermined value in synchronization with the operation of the head (
tag-Sr) Outputs a signal whose level is inverted every time. At this time, tA, the mode control circuit 19 is switched to the selector switch 18.
When the counter 16 is closed to the b side, the output signal of the counter 16 is supplied as a switching signal to the first factor switching circuit 12 and the inverting circuit 1s via the switching circuit 18. When the transition to standard speed playback is requested at 69 and the mode control circuit 19 receives a mode input for standard speed playback as shown in FIG. Another 1It-counter 16
Set to . Due to this reset, the output signal of the counter 16 becomes 0L1 (low level), but this reset II
Since the previous level is 181, mode control circuit 1
9 is cut and stored on the switching circuit 1aia side, and the switching signal obtained from the switching circuit 18 is the same as the reset lIgIII °H@
shall be. In addition, after being reset, the output signal of the counter 16 is set by the mode control circuit 19.
ta-)-tar) Once the time has passed, the level will be reversed. As a result, the counter 16 is reset 11fK, and as explained earlier, the remaining intra-frame encoded 7-ray 580 decoded image data stored in the frame memory of FIG. It will be read after reset. When the output signal of the counter 16 is inverted from "H" to °L1 after a period of time (tagtr) has passed since the counter 16 was reset, the % mode control circuit 1! sets another value in the counter 14. The output signal of is t@
The level is inverted every r hours. At this time, selector switch 1
8 is closed to the ta side, and this 9th, switching circuit 1
The level of the switching signal output from 8 is inverted every time t@r, and the switching circuits 11 and 12 in FIG. 1 operate as described above. It should be noted that when a request for transition to standard speed playback is made during high speed playback during the 0L1 period of the output signal of the counter 16, the switching circuit 1B remains closed to blI at this time. Other operations are the same as above. The above explanation has been about the case of transition from the high speed reproduction state to the standard speed reproduction state, but next, the case of transition from the high speed reproduction state to the slow reproduction state will be explained with reference to Figure 4. However, here, it is assumed that the state shifts to a slow playback state of 1/2 speed. In the high-speed playback state, the intra-frame encoded data for every 80 frames is read out and displayed as described above, but here, if the complaint 800-image is displayed, an IK slow playback instruction request is issued. Assuming this, the encoded data of frame 81 after frame 800 is reproduced and decoded in time (ta+tsr), as in the case of standard speed reproduction. The encoded data of this frame 81 is as shown in Figure 1.
Variable length decoding circuit 1, inverse quantization circuit 2, inverse orthogonal transform circuit S
The signal is subsequently decoded and supplied to the adder circuit 4. In response to an instruction request for slow playback, the mode control circuit 19 shown in FIG. 5 resets the counter 14t, and
a+% [phase]r) Set a predetermined value to the counter 16 so as to output a signal whose level is inverted between WiI, and then switch from the switching signal generation circuit 14 to the switching circuit 18t-1. The output switching signals are as shown in Figure 4. Therefore, the inter-frame difference signal data of the frame 81 is added to the 7-ray 5800II image data read from the frame memory 10 in the adder circuit 4, and the 7-ray 5800II image data is 581 image data are obtained. This image data outputted from the adding circuit 4 is written into the frame memory 9 and the output frame memory 7 via the switching circuit 5. In the next frame period, since slow playback is performed at 1/2 speed, the encoded data is not played back, and the mode control circuit 1
9 sets another predetermined value to the counter 16 so that the counter 16 outputs a signal whose level is inverted in (2Xt@r) time, and also causes the switching circuit 181 to remain closed to tm@ Department. Therefore, the switching signal output from the switching circuit 18 is
@4 As shown in figure, the phase is 11 and the period is 2
The signal becomes t@r. 9. The 7-ray 581 image written immediately before in the output frame memory 7 is displayed. Furthermore, in the next frame period, the encoded data of the frame-related difference signal of frame 82 is reproduced and decoded in tar time. Furthermore, since the switching signal outputted from the switching signal generation circuit 14 is a signal with a period of 2
The decoded image data of frame 10.1 and the inter-frame difference number 1 of 7-ray 582 are added to restore the image data of frame 82, and the frame memory 10. 7 rays 5 memory 7 for output
will be written to. At this time, the image of the frame 81 written first from the output frame memory 7 is displayed. After that, repeat this process to achieve slow playback. In 15 above, when transitioning to slow playback, in the same way as when transitioning to standard speed playback, the 900p response to the displayed image being played back at the time of receiving the user's slow playback instruction request is explained. There is no need to play back and decode the encoded data of the intra-frame encoded frame, and the slow playback from the high-speed playback state is performed for the time tr required to reproduce and decode the encoded data of the nine intra-frame encoded frames. It is possible to provide a method for reproducing pressure image data that can shorten the waiting time when transitioning to a state and is very user-friendly for the user. FIG. 5 is a block diagram showing another embodiment of the pressure S image data reproduction method according to the present invention, in which 20 is an f-Alport frame memory, 21 is a frame memory, 22.25
is a switching circuit, 24 is a switching signal generation circuit, and I! The parts corresponding to the first prisoner are given the same reference numerals and redundant explanations will be omitted. In FIG. 5, in the case of high-speed playback at 8x speed, frame ① encoded data that is intra-frame encoded every 80 frames is reproduced in the same manner as in the previous embodiment. At this time, the switching signal generated from the switching signal generation circuit 24 is °L°, and the switching circuit 2
2μ is turned on and the switching circuit 25 is closed to all. (9) The switching circuit 5 selects the output of the inverse orthogonal transform circuit 5. At this time, the encoded data of the intra-frame encoded frame is decoded and output from the inverse orthogonal transform circuit 3, and written into the frame memory 7.20 via the switching circuit 5. In this way, the frame memory 7 is sequentially rewritten with frame data of every 80 frames and decoded 9 frames (thus, an image of every 80 frames is displayed. On the other hand, the frame memory 20 It is Todoroki Alhord's memory, and written image data is immediately read out.
Frame memo through switching circuit 22! 721. Therefore, the image data in the frame memory on which the image is displayed is also held in the frame memory 21. Therefore, as shown in FIG. 6, if there is a request for IIK standard speed playback while the image of frame 80 is being displayed, then the encoded data of the frame 800 next frame, that is, frame 81, will be displayed. access, playback,
Decryption is being performed. The time required from requesting access to the encoded data of frame 81 to decoding it is as follows: When the instruction request for standard speed playback is received, the head is at the recording position of the encoded data of frame 160, and when the encoded data of frame 810 is encoded. Since it is far from the data recording position, the waiting time ta from the access request for track jump to the start of data reproduction and the reproduction of the encoded data of frame 81, which is the encoded data encoded between frames. decoding time t
It becomes the sum with @r. The decoded data of frame 81 is outputted by the inverse orthogonal transform circuit S and supplied to the adder circuit 4. At this time, the switching code from the switching signal generation circuit 24 is as shown in FIG. After receiving the instruction request for playback, (ta+t@r) time @H・ changes, and the switching circuit 2
2 is off, and the switching circuit 2s is switched to the b side. As a result, the image data of 7 rays 580 is read out from the frame memory 21, supplied to the addition 3EII4 via the switching circuit 2Sf, and the frame 8 is outputted by the inverse orthogonal transform circuit 5.
The decoded image data of frame 81 is obtained by adding the frame difference signal data of frame 81 with the inter-frame difference signal data of frame 81 in addition circuit 4. The image data of the 7-ray 581 outputted from the adder circuit 4 is written into the output frame memory 7 such as the frame memory 20 via the switching circuit 5t. As a result, the message "I'm in love" in frame 81 is displayed, and the 7 ml data is held in the frame memory 20. After writing to these frame memories 7.20 is completed,
As shown in FIG. 6, the switching signal from the switching signal generating circuit 24 becomes @L1 again, the switching W circuit 22 is turned off, and the switching circuit 2S is closed to a911. From the reproduction of the next inter-frame encoded IF, 7-ray 581, one rmo frame of image data is stored from the frame memory 20 each time the decoded data of the frame differential signal is output from the inverse orthogonal transform circuit S. is read out and OI! The II image data and the decoded data are added by the adder circuit 4 to create image data for the next frame, which is stored in the frame memory 7.20. In this way, standard speed playback is performed. In this way, by providing a storage means that stores and holds the current display image 11 which is being reproduced at high speed until the next image t is displayed, it is possible to switch from high speed reproduction to standard speed reproduction. ! When transitioning to IK, as a frame to be reproduced and decoded, the encoded data of frame O of the display image being reproduced at the time of receiving the instruction request for standard speed reproduction is reproduced and decoded, and is stored in the storage means. By adding it to the image data that was displayed, it is possible to obtain the i1me image of that frame, and once again calculate the intra-frame encoding corresponding to the display being played back at the time of receiving the user's instruction request for standard speed playback. There is no need to reproduce or decode encoded data. Therefore, the waiting time when transitioning from high-speed playback mode to standard-speed playback mode can be shortened by the time it takes to play back and decode the coded data of the frame coded within %7 frames, and the compressed recording is convenient for users. The image data reproduction method t-m can be provided. FIG. 7 is a block diagram showing a specific example of the switching signal generation circuit 24 in FIG. In the same figure, the mode control circuit 27 resets the slip-flop circuit 24t to its output level "L" as an initial countermeasure in any playback mode. is supplied to the switching circuit 22.2s in the gs diagram. Therefore, in the high-speed playback state, the 7 lip-flop circuit 26
As shown in Fig. 6, the switching signal output from I
Therefore, the switching circuit 22 in Figure 5
is on and the switching circuit 23 is closed to side a, but when there is an instruction to shift to standard speed playback, the mode control circuit 27 synchronizes with this and sets the 7-rip 70-rub circuit 26, which will now be output. The switching signal is set to "Hl."As a result, in FIG. 5, the switching circuit 22 is turned off and the switching circuit 25 is turned off.
Switch to . Then, after (ta+t@r) hours,
The mode control circuit 27 resets the slip-flop circuit 26 and sets the switching signal to 1L''.As a result, the switching circuit 22 is turned on again and the switching circuit 25 is switched to the a side. In the examples, we have explained the case of transitioning from high-speed playback in the forward direction to standard-speed playback, or from high-speed playback to slow playback, but when moving from high-speed playback in the reverse direction to standard-speed playback, or from high-speed playback in the reverse direction to slow playback. It is clear that the present invention is also applicable to cases where a CD-ROM rotates at a constant linear speed.
In the case of ROM, the interval between recording positions of intraframe-encoded frames is not constant. Furthermore, the recording length of each frame is also different. Therefore, depending on these % & a tr
Although the time of at@r is different, it goes without saying that the operations of each of the above embodiments are performed accordingly. [Effects of the Invention] As explained above, according to the present invention, a storage means is provided to store and hold the currently displayed image being reproduced at high speed until the next 8m is displayed. When transitioning from the high speed playback state to the standard speed playback state, the next frame O encoded data of the display image at the time of reception of the instruction request for standard speed playback is played back and decoded as the data of the next frame to be played back and decoded. However, since the image data of the frame can be decoded by adding it to the image data stored in the storage means, it is possible to decode the image data of the frame by adding it to the image data stored in the storage means. There is no need to reproduce and decode the encoded data of the frame that is intra-frame encoded, and therefore the time required to reproduce and decode the encoded data of the nine intra-frame frames is reduced.
The waiting time from the high speed playback state to the standard speed playback state can be shortened, making it easy for the user to use the pressure m.
The method for reproducing image data can be provided.

[Brief explanation of drawings]

Figure 1 shows the pressure according to the present invention! Ili! A block diagram showing an embodiment of the i-image data reproduction method, FIG. 2 is a ninth timing diagram explaining an example of the operation of this embodiment, and FIG. 3 is a specific example of the switching signal generation circuit in FIG. 1. Figure 4 is a timing diagram for explaining other operations of the embodiment shown in Figure 1, and Figure 5 is a block diagram showing another embodiment of the image data reproducing method according to the present invention. Figure 6 is a tie diagram for explaining an example of the operation of this embodiment.
Figure 7 is a block diagram showing a specific example of the switching signal generation circuit in Figure 5, Figure 8 is a block diagram showing an example of a conventional compressed image data reproduction method, and Figure 9 explains its standard speed reproduction operation. The timing diagram for this, Figure 10, is pressure! ll
FIG. 11 is a schematic diagram showing 11 image data, and is a timing chart for explaining the transition operation from high-speed reproduction to standard-speed reproduction in the conventional example shown in FIG. 8. S-Inverse orthogonal variation! ! j1 circuit, 4... weighting circuit, 5...
・Switching circuit, 7-・Output frame memory, 9,1o・
...Frame/MoIJ, 11. j2... switching circuit,
13... Inversion circuit, 14... Switching signal generation circuit, 2
0.21--Frame memory, 22.25--Switching circuit, 24--Switching signal generation circuit. ” ■ Mouth (Meat°°λ＼MeppN30 jP15UfU JIA80 Tsuta90

Claims (1)

[Claims] 1. Image data compressed by intra-frame encoding in every plural frames and inter-frame encoding in each frame between the frames is recorded on a recording medium, and the image data is transferred from the recording medium to the recording medium. When reproducing data at high speed, only the image based on the image data of the intra-frame encoded frame is displayed, and the display of this image is continued until the display of the image based on the image data of the intra-frame encoded frame to be played next starts. In the compressed image data reproduction method, the decoded image data of the displayed image is held in the display period storage means during high-speed reproduction,
In response to a transition instruction from high-speed playback to standard-speed playback or slow playback, reproducing and decoding image data of an inter-frame encoded frame following an intra-frame encoded frame for the displayed image; A compressed image data reproducing method characterized in that the image data read from the storage means is subjected to arithmetic processing to generate image data for image display, and the image data is reproduced at standard speed or at slow speed.