JPH0442619A - D/a converter - Google Patents

Abstract

PURPOSE:To improve the differentiating linearity and to suppress the increase in a required area by constituting each current source transistor (TR) cell of plural TRs of the same size, and using only the required number of TRs among the plural TRs to attain high precision for the current source TR cells. CONSTITUTION:Current course TR cells T1 - T4 of plural sets are included in the D/A converter and a weighting circuit 10 is provided, in which the current outputted from an m-th (1<=m<=n) TR cell among the n-set of the current source TR cells T1 - T4 is a multiple of 2<m-1> with respect to the current outputted from a TR forming the least significant bit. Then each of the current source TR cells T1 - T4 consists of 2<n-1> sets of TRs t1 of the same size, and 2<m-1> of TRs are connected in series with the m-th TR cell. Thus, while the increase in the required area is suppressed, the differentiating linearity is improved.

Description

Detailed Description of the Invention [Summary] The present invention relates to a DA converter, particularly a weighting circuit used in a DA converter, and provides a DA converter that can improve differential linearity while suppressing an increase in required area. A DA converter that outputs an analog signal according to a current value corresponding to an n-bit digital signal, including n current source transistor cells, of which nil current source transistor cells a weighting circuit in which the current value output from the m-th (1≦m≦n) transistor cell is expressed as twice the current value output from the transistor cell forming the least significant bit; Each of the current source transistor cells is formed by two transistors of the same size, and the mth transistor cell has two transistors of the same size.
It consists of transistors connected in series.

[Industrial application field]

The present invention relates to a DA converter, and particularly to a weighting circuit used in a DA converter.

In recent years, high-speed DA converters used in televisions, VTRs, etc. are required to have a higher number of bits and higher precision.

In a DA converter, a weighting circuit is used, which includes a plurality of current source transistor cells with different current values. Then, when increasing the number of bits,
The error between the current source transistor cells increases, and differential linearity deteriorates.

Therefore, it is desired to reduce errors between current source transistor cells by increasing the accuracy of current source transistor cells, and as a result, improve differential linearity.

[Conventional technology]

FIG. 4 shows a conventional weighting circuit.

In FIG. 4, the weighting circuit is 4 bits;
current source transistor cells T1 to T4. Here, the ratio of sizes W1 to W4 of cell TI-T4 is 1:2:
4:8, and as a result, the ratio of current values from cell 'r-74 is 1:2:4:8.

Next, FIG. 5 shows a DA converter using the conventional weighting circuit as described above.

In FIG. 5, the DA converter is of the 8-bit type, and therefore the weighting circuit 10 includes eight current source transistor cells Tl-T8.

Here, the ratio of size Wl-W8 of cell T-T8 is 1
:2:4:8:16:32:64:128, and as a result, the ratio of cells TI-T8 is 1:2:4:8:16:128. In addition, the code|symbol 12 shows these, the code|symbol 14 shows a load, and shows a power supply voltage.

Current value from 32:64: Bias circuit code vd is (DSD), (D, D) indicates each input terminal of a digital signal (this is 8 bits) which is an input signal.

For example, the lth bit and the second bit of the digital signal are at rHJ level, and the other third to eighth bits are rHJ level.
When the level is LJ, the input terminal DSD2 is r
Since the input terminals D3 to D8 are at the rHJ level, the sum of the current values from the current source transistor cell TST is supplied to the load 14. In this way, an 8-bit input digital signal is converted to an analog signal.

[Problem that the invention seeks to solve]

In the weighting circuit as described above, when the bits are increased, the error between the current source transistor cells increases and the differential linearity deteriorates. Here, differential linearity refers to an error with respect to the average current of each bit.

Furthermore, there is a conventional DA converter using a segment circuit, as shown in FIG.

In FIG. 6, reference numeral 16 indicates a segment circuit;
In the case of the 8-bit type, the segment circuit 16 includes 255 (=21) current source transistors (DSD) with the same characteristics (outputting the same current value).
, (D SD) is transistor FE FE
FF FF Tassel I! ,,,
~I, input I corresponding to I
FE Indicates FF blade terminal. for example,
The second bit of the 8-bit input digital signal is rHJ.
If the other bits are at the rLJ level, the decoded value is r2J, so there are 2n-1 input terminals. As a result, transistor cells I, I
The sum of the current values from is supplied to the load 14. In this way, an 8-bit input digital signal is converted to an analog signal.

Since the segment circuit described above uses a plurality of current source transistor cells that output the same current value, the error between the transistor cells is small even when the bits are increased. Therefore, the differential linearity is improved,
High accuracy is achieved.

However, in segment circuits, as bits become higher, a large number of current source transistor cells are required.
For example, in the case of 8 bits, 255 (21) transistor cells are required. As a result, there is a problem that the area of the segment circuit increases.

As described above, when a weighting circuit is used in a DA converter, the differential linearity deteriorates as the bit rate increases, while when a segment circuit is used, the segment There is a problem that the area of the circuit increases.

An object of the present invention is to provide a DA converter that can improve differential linearity while suppressing an increase in required area.

[Means to solve the problem]

FIG. 1 shows a DA converter according to a first aspect of the invention. In FIG. 1, the weighting circuit is, for example, 4 bits and includes four current source transistor cells T1-T4. Each cell 4-1 T includes eight (=2) transistors t1 to ts of the same size. Then, the mth (1≦
The transistor cell T 1 (m≦4) uses only two transistors out of the eight transistors t 1 to t 2 . For example, the third transistor cell T is
Only 4 (=2) transistors 1-14 are used.

In addition, in FIG. 1, the unused transistor t1
That is, the transistor t of the transistor cell Tl
1-t Transistor 1- of sF transistor cell 2
1. ) Transistor of transistor cell T3 -18
may be used for other applications, for example for current source transistor cells in other weighting circuits.

Further, the invention according to claim 2 provides a digital signal generator that outputs an analog signal based on a current value corresponding to an n-bit digital signal.
In the A converter, the upper one of the n bits! The bits are constructed with segment circuits, the lower n-l bits are constructed with weighting circuits, and the sizes of the current source transistor cells of the segment circuits and weighting circuits are the same.

[Operation] In FIG. 1, according to the invention as claimed in claim 1, the current source transistor cells T1 to T4 each include one, 2n-1, four, and eight transistors t of the same size. , the ratio of current values from the transistor cells Tl-T4 is 1:2:4.8. And transistor t
Since "1 to ts" have the same size, the error between the transistor cells Tt "" 74 becomes small, and the differential linearity improves.

Furthermore, according to the second aspect of the invention, by using the weighting circuit or the weighting circuit and the segment circuit together, an increase in the required area is suppressed compared to the case where only the segment circuit is used.

〔Example〕

FIG. 2 shows a DA converter using a weighting circuit according to a first embodiment of the present invention.

In FIG. 2, the DA converter is of the 3-bit type, so the weighting circuit 10 includes 3II current source transistor cells T1 to T3.

Here, each cell T includes four transistors t1 to t4 of the same size. Then, the cell T uses only one transistor t1, and the other transistor t
"""t4 is not connected.

Further, the cell T includes 2n-1 transistors t1, t
The other transistors t3 and t4 are not connected. Further, the cell T3 uses all four transistors t1 to t4. As a result, cell T 1T
2. The ratio of current values from T3 is 1:2:4.

Then, since the transistors t '' t < are the same size, the transistor cell T ST .

The error between 13 and 13 is small, and the differential linearity is improved.

(D, D) indicate each input terminal of a 3-bit input digital signal. For example, when the first and second bits of the digital signal are at rHJ level and the third bit is at rLJ level, , input terminals D and D are rHJ
Since the input terminal D2 is at the rHJ level, the sum of the current values from the current source transistor cells T 1 and T 2 is supplied to the load 14. In this way, the 3-bit input digital signal is converted to an analog signal.

In addition, in order to improve the precision of the current mirror with the bias circuit 12, the transistor cell Tb in the bias circuit 12 is replaced with the transistor cells T 1 , T 2 , T
It may also be configured in the same way (using multiple transistors of the same size).

In addition, input terminals D , D SD , D , D2
．． The transistor cell T-79 connected to D is
Although shown alone in the embodiment, the transistor cell T
, T , T , and transistor cell T
ST, T to the transistor cell T1. T2,
It may be configured similarly to T3 (with a plurality of transistors of the same size).

Next, FIG. 3 shows a DA converter using a weighting circuit according to a second embodiment of the present invention.

In FIG. 3, the DA converter is a 6-bit type and includes a weighting circuit 10 and a segment circuit 16.

Here, the weighting circuit 10 is responsible for the lower two bits among the six bits, and the segment circuit 16 is responsible for the upper four bits among the six bits.

The weighting circuit 10 includes 2n-1 current source transistor cells T, T, , each cell T comprising four identically sized transistors t l''1 to t 4 .

The cell T 1 uses only one transistor tl and does not connect the other transistors t2 to t4.

Further, the cell T2 has 2n-1 transistors S
Only transistor 12 is used, and the other transistors t3 and t4 are not connected. With the above configuration, cell T1 is responsible for the 1st bit of the lower 2 bits, and cell T2 is responsible for the 2nd bit of the lower 2 bits.

Since the segment circuit 16 has 4 bits, 15 (=
21) current source transistor cells 11 having the same characteristics (outputting the same current value), ■ to ■, and ■. Each current source transistor cell I comprises four transistors t1-t of the same size and uses all four transistors t1-t4.

The transistors t1 to t4 of the current source transistor cell I in the segment circuit 16 are the transistors t1 to t4 of the current source transistor cell T in the weighting circuit 10.
Since they are the same size, the error between the upper 4 bits and the lower 2 bits is reduced, and differential linearity is improved.

Note that, similarly to the first embodiment, the transistor cell Tb in the bias circuit 12 is replaced by transistor cells T 1 , T 2 ,
It may be constructed in the same way as transistor cell (2) (with a plurality of transistors of the same size).

Furthermore, in the second embodiment, the segment circuit 16 is in charge of the upper 4 bits, and the weighting circuit 10 is in charge of the lower 2 bits, and the number of bits that the segment circuit 16 is in charge of is small (4 bits). The number of current source transistor cells (2) in the circuit 16 is small. therefore,
The area required for the segment circuit 16 does not increase significantly.

Also, to describe the second embodiment of FIG. 3 in a general form,
It will look like this:

In an n-bit DA converter, the n bit is the upper one!
bit, divided into lower n−l bits.

The lower n-l bits are processed using a weighting method, and the upper i bits are processed using a segment method. That is, in the weighting method for the lower n-l bits, n
- one current source is used, the first current source is
It has a current value of (1≦i≦n-1). Here, the lower n
- Is the i-th bit of l bits at “H” level?
Depending on whether it is at the LJ level, a current with a current value of 2 is output from the i-th current source. Then, the sum of current values from all current sources is output by the weighting method.

Top! In the bit segment method, 2+1-A
2'-1 identical current sources with a current value of ' are used. The upper l bits are decoded and the upper l bits are decoded. Current is output from the current source in the number indicated by the bit. Then, the sum of the output current values is output by the segment method.

As described above, the lower n-! Upper order by bit output and segment method! The sum with the bit output is the output of the DA converter.

Note that the current source in the weighting method and the current source in the segment method may be composed of two transistors of the same size.

In this case, the i-th current source in the weighting scheme is
2 (1
≦i≦n-1) transistors are used. Furthermore, each current source in the segment method uses two transistors of the same size.

〔Effect of the invention〕

As explained above, according to the invention as claimed in claim 1, each current source transistor cell is composed of a plurality of transistors of the same size, and a necessary number of transistors among the plurality of transistors are used. The precision of the source transistor cell can be improved. Therefore, errors between current source transistor cells are reduced, and differential linearity is improved.

Further, according to the invention as set forth in claim 2, since the weighting circuit and the segment circuit are used together, an increase in the required area is suppressed compared to the case where only the segment circuit is used.

It is a circuit diagram of Burke.

10... Weighting circuit 12... Bias circuit 14... Load 16... Segment circuits T1 to T4... Current source transistor cell 1 -18.
・Transistors 11 to ■15 of the same size...Current source transistor cells

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a weighting circuit according to the principle of the present invention, FIG. 2 is a circuit diagram of a DA converter using a weighting circuit according to the first embodiment of the present invention, and FIG. A circuit diagram of a DA converter using the weighting circuit according to the embodiment, FIG. 4 is a circuit diagram of a conventional weighting circuit, and FIG. 5 is a circuit diagram of a DA converter using a conventional weighting circuit.

Claims (1)

[Claims] 1. A DA converter that outputs an analog signal according to a current value corresponding to an n-bit digital signal, which includes n current source transistor cells (T_1 to T_n), and the n current sources Transistor cell (T_1 to T_n)
The m-th (1≦m≦n) transistor cell (T
_m) is 2^m^ with respect to the current value output from the transistor forming the least significant bit.
-^1 times the weighting circuit, and each of the current source transistor cells (T_1 to T_n) has 2^n^-^1 transistors of the same size (
t_1 to t_2n-1), and the m-th transistor cell (T_m) has 2^m^-^1 transistors (T_1 to t_2n-1) connected in series. A DA converter featuring: 2. In a DA converter that outputs an analog signal based on a current value corresponding to an n-bit digital signal, the upper l bits of the n bits are configured with a segment circuit, and the lower n-l bits are configured with a weighting circuit, A DA characterized in that the size of each current source transistor cell of the segment circuit and the weighting circuit is the same.
converter.