JPH04369919A - Automatic frequency control circuit - Google Patents

Abstract

PURPOSE:To make the conversion frequency stable even when no pilot signal is received in a highly stable AFC required for an automatic frequency control circuit(AFC), especially for the SCPC system or the like in a receiver for a radio satellite communication equipment. CONSTITUTION:An this control circuit provided with a frequency conversion means 10 mixing a local oscillation signal with an input signal to implement frequency conversion, a based pass filter means 12 extracting only a signal with a specific frequency from the output signal of the means 10, a reference oscillating means 14 outputting the signal of a reference frequency, a phase comparator means 16 comparing the phase and frequency of the output signal of the means 12 with those of an output signal of the means 12, and a voltage controlled oscillating means 18 outputting a signal whose frequency is controlled in response to the result of comparison by the phase comparator means 16 as a local oscillating signal, a frequency divider means 20 frequency-dividing the output signal of the voltage controlled oscillator means 18 at a prescribed frequency division number and outputs the result and the switching means 22 selecting either the output of the frequency divider means 20 or the output of a band pass filter means 12 and supplying the selective signal to the phase comparator means 16 are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit (AFC) in a receiving device for radio/satellite communication equipment. In particular, the present invention is applicable to SCPC (Single Channel
This invention relates to highly stable AFC required in the 1 Per Carrier system and the like. In the SCPC method, the bandwidth occupied by one channel is extremely narrow (several 10 KHz) relative to the carrier frequency (several 100 MHz or more), and the bandwidth tends to become narrower year by year in order to improve frequency utilization efficiency, so it cannot be used normally. In order to receive signals, it is strongly required that the reception frequency be highly stable.

[0002] However, the signals received from the satellite are
There is a certain limit to the stability of the reception frequency due to the stability of the local oscillator mounted on the satellite, the Doppler effect, and the stability of the receiver's high-frequency circuit. Therefore, by sending an unmodulated pilot signal to a specific position within the band used and automatically controlling the local frequency of the receiver so that this pilot signal is converted into a signal with an accurate frequency, stable AFC is employed to enable reception.

[0003] This pilot signal is sent out only by the master station that controls the entire communication network, so if this is interrupted for some reason, or if the system does not send out the pilot signal, or if a part of the communication network is A pilot signal cannot be obtained when performing a loopback test. Therefore, it is desired that stable reception is possible even in this case.

0004

2. Description of the Related Art FIG. 9 shows an example of a conventional AFC circuit. In the figure, 30 is a frequency converter (CONV), 32 is an AF
C pilot signal extraction narrowband filter (BF), 3
4 is a reference highly stable oscillator (OSC), 36 is a voltage controlled oscillator (VCO), 38 is a phase comparator, and 40 is an AFC.
Loop filter (LF) of the loop, 42 is AFC O
N/OFF selector switch (SW), 44 is AFC O
This is the bias voltage (VB) during FF.

[0005] In the conventional AFC, an AFC pilot signal is extracted by the BF32 at the output of the CONV30, and
The PD 38 compares the reference signal output from the OSC 34 with the pilot signal, and controls the VCO 36 so that these signals have the same phase and frequency. Here, LF40 is a loop filter that determines the response characteristics of the AFC loop. Also, SW42 is AFC OFF.
At times, the VCO control voltage is switched to a fixed bias VB.

In such a configuration, in the case of a system without a pilot signal, the AFC is used in an OFF state, so the frequency stability of the output signal of the CONV 30 is almost determined by the stability of the VCO 36. Therefore, V
A highly stable oscillator is required as the CO 36. However, the stability of a VCO is determined by the oscillation frequency, variable width, Q of the resonator, etc.
Hz or higher), and it is necessary to search within the allocated band to acquire the pilot signal, so it is very difficult to achieve high stability (if frequency stability of 10-6 or less is required, this is not possible). is virtually impossible). In addition, even in systems that use pilot signals, when performing internal loopback tests during equipment maintenance and inspection, etc., there is no pilot signal, so the test must be performed with AFC OFF, and even in such cases, VCO stability may be a problem. becomes. This is because the pilot signal is transmitted only by the reference station.

FIG. 10 shows an example of arrangement of received signals. As shown in the figure, channel slots are allocated at constant channel intervals from CH1 to CHn, and a pilot signal is placed in a part of the band from the reference station. Sent from. Here, the channel spacing is, for example, 45 KHz in FM-SCPC (22 KHz in a narrow band system).
5KHz), and these vary depending on the system. Received signal (fRF) at 1,190MHz
, set the output frequency (fIF) of CONV30 to 70MHz
Then, the local frequency (fL) of CONV30
is 1,120MHz, and assuming that the stability of OSC 34, which is the AFC reference signal, is 1 x 10-6 (a crystal oscillator is generally used), the stability of the 70MHz output signal is up to 70Hz by the AFC loop. It will be compressed. However, in the case of AFC OFF, fL
The stability of is determined by the stability of VCO 36, and is generally 1
Since it is approximately ×10-4, the 70 MHz output signal will fluctuate by 112 KHz. Therefore, in the case of the channel spacing as described above, it becomes impossible to receive the designated channel.

[0008]

[Problem to be Solved by the Invention] Therefore, even in systems that use pilot signals, it is necessary to use the system with AFC OFF when performing a return test to the local station during maintenance and inspection of equipment, or in systems that do not have pilot signals. In this case, a problem arises in that the frequency of the CONV output signal becomes unstable.

An object of the present invention is to stabilize the frequency of the CONV output signal even when AFC is OFF.

0010

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In the figure, the automatic frequency control circuit of the present invention includes a frequency conversion means 10 that performs frequency conversion by mixing a local oscillation signal with an input signal;
A bandpass filter means 12 that extracts only a signal of a specific frequency from an output signal of zero, a reference oscillation means 14 that outputs a signal of a reference frequency, and a phase between the output signal of the bandpass filter means 12 and the reference oscillation means 14. and an automatic frequency control circuit comprising a phase comparison means 16 for comparing frequencies, and a voltage controlled oscillation means 18 for outputting a signal whose frequency is controlled according to the comparison result of the phase comparison means 16 as the local oscillation signal. , a frequency dividing means 20 that divides the output signal of the voltage controlled oscillation means 18 by a predetermined frequency division number and outputs the resultant signal; and an output of the frequency dividing means 20 or the bandpass filter means 1.
The present invention is characterized by comprising a switching means 22 for switching and selecting one of the two outputs and supplying the selected output to the phase comparison means 16.

[0011]

[Operation] When there is no pilot signal in the received signal, if the switching means 22 is switched to select the output of the frequency dividing means 20, the voltage controlled oscillation means 18, the frequency dividing means 20, and the phase comparing means 16 A synchronized loop (PLL) is formed, and the frequency of the output signal of the voltage controlled oscillation means 18 is controlled to be the frequency of the reference oscillation means 14 multiplied by the frequency division ratio of the frequency division means 20. is stabilized to a stability of .

0012

Embodiment FIG. 2 is a block diagram showing a first embodiment of the present invention. Components that are the same as those in FIG. 9 are given the same reference numerals, and their explanations will be omitted. 50 is VCO
52 is a frequency divider (DIV) that divides a part of the output of BF32 into 1/N (N: integer), and 52 is a switch (SW) that switches between the extracted pilot signal of the output of BF32 and the output signal of DIV 50. be.

[0013] When AFC is turned on, by setting SW52 to the a side, an AFC loop similar to the conventional one is formed.
When FC is OFF, switch SW52 to b side and PL
By forming L, the output frequency of the VCO 36 is controlled so that the output frequency of the OSC 34 and the output frequency of the DIV 50 are the same, and by providing a highly stable output using the OSC 34 as a reference signal, This makes the output signal highly stable.

In this embodiment, in a system using a pilot signal, by setting SW52 to the a side, the AFC
By controlling the VCO 36 so that the extracted pilot signal output from the BF 32 is the same as the reference signal from the OSC 34, a loop can be formed.
The frequency of the output signal of ONV30 is the reference signal OSC
It is stabilized to the same stability as the frequency of 34.

On the other hand, when there is no pilot signal such as during a return test to the own station during maintenance and inspection, or when used in a system that does not have a pilot signal, the PLL
can be formed, and the output frequency of the VCO 36 is
Since OSC 34 is used as a reference signal and the output frequency of DIV 50 is controlled to be the same, AFC OFF
However, its stability can be made the same as OSC 34. Note that the output frequency of the VCO 36 is N times the reference signal (the input frequency of the PD 38).

For example, the input frequency fRF of CONV30
1,190MHz, output frequency fIF 70MHz
, the output frequency fL of the VCO 36 is 1,120 MHz, and the pilot signal is located at the center of the output frequency of the CONV 30, then fP = 70 MHz. AFC
When turned ON (SW52 is on the a side), the VCO 36 uses the error signal of the output of the PD38 to output f through the LF40.
Since it is controlled by the AFC loop so that r = fP, the reference signal fr (output of OSC 34) is
If it is 0MHz, even if fRF fluctuates, the output of VCO 36 will change around 1,120MHz, so C
The fIF of ONV30 output can be maintained at 70MHz. Here, the frequency stability of OSC 34 is 1×
If it is set to 10-7, fIF can also have the same stability.

When AFC is turned off (SW52 is on the b side), the output of the VCO36 is divided by 16 (
If N = 16), the output will be 70MHz, so the error signal of the output of PD38 will cause f to pass through LF40.
It is controlled so that r = fP. Therefore, VCO
Since the output frequency stability of 36 is phase-locked to the output of OSC 34, it can be made to have a stability of 1×10 −7 similarly to OSC 34, and when fL = 1,120 MHz, it becomes 112 Hz.

FIG. 3 is a block diagram representing a second embodiment of the invention. 54 is a control circuit (CONT) that switches and controls parameters of SW52 and LF40 when switching ON/OFF of AFC. This example shows the response characteristics of the AFC loop at AFCON and the PLL at AFCON.
Since the response characteristics of the LF 40 are different, the parameters of the LF 40 are changed at the time of ON/OFF switching to set the optimum parameters and improve the response characteristics.

FIG. 4 shows an example of parameter switching of the loop filter LF40 in the embodiment shown in FIG. 61 is a parameter changeover switch, 62 to 65 are resistors and capacitors that determine loop parameters,
66 is an amplifier. In the figure, change the resistance values of 62 and 63, synchronize with AFC ON/OFF, and turn SW6.
1, the response characteristics of the loop can be changed.

In this way, by changing the parameters of the LF 40 to account for the difference in the control loop caused by AFC ON/OFF, it is possible to always set the optimum response characteristic. FIG. 5 is a diagram showing a third embodiment of the present invention, in which the same parts as those described above are designated by the same reference numerals. In the figure, 70 is a detector (DE) that detects the presence or absence of a pilot signal.
T), 72 is a control circuit (CON
T).

In this embodiment, if the pilot signal is cut off for some reason, it is detected and the A
By turning off the FC loop, a relatively stable signal is obtained as the output signal of CONV30. Normally, if the pilot signal is disconnected, the AF
The C loop ends up being latched in one direction. (At this time, the pilot signal is generally searched within the allocated band in an attempt to capture the pilot signal.) With the above configuration,
By making the stability of the reference signal source OSC 34 stable to some extent, a stable signal can be obtained even when the pilot signal is interrupted. In addition, pilot signal loss is also detected at the reference station and automatically switched to another device.
It will be sent out again.

FIG. 6 is a block diagram representing a fourth embodiment of the present invention. 74 in the figure is A depending on the output state of PD38.
Alarm detection circuit (ALM) that detects whether the FC loop is normal or abnormal, 76 is S depending on the output state of ALM 74.
This is a control circuit (CONT) that controls W52. In this embodiment, even if the pilot signal is cut off for some reason, it is detected by detecting the state of PD38, and the AFC loop is automatically switched to PLL, so that it can be used as a relatively stable output signal of CONV30. It's trying to get a signal.

Normally, when the pilot signal is disconnected,
Since the state of PD38 is latched in one direction, this is detected by ALM 74 and CONT7
By switching SW52 to the b side with 6, the PLL
It constitutes. With this configuration, as described above, a highly stable output signal can be obtained using the OSC 34 as a reference signal source.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention. In the figure, 70 is a pilot signal presence/absence detector (DET) as in the embodiment of FIG. 80 and 82 are frequency dividers (DI
V), 84 is based on information from DET 12, DIV
Control circuit (CONT) that controls by changing the frequency division number of 86
It is. Here, DIV86 is somewhat different from DIV50 described above, and is a variable frequency divider whose frequency division number can be changed by external control.

[0025] When the pilot signal is cut off for some reason, it is detected and the AFC is turned off, and even if the pilot signal is sent out again, the frequency may have been changed or the received frequency may have fluctuated. , just A
Even if the FC is turned on, it may not be possible to capture it. In this embodiment, in order to deal with this problem, AFC is
Before setting to N, set AFC OFF, that is, PL.
The DET 70 searches within the allocated band until a pilot signal is detected while keeping the circuit configuration of L as it is. When the pilot signal is reacquired, the AF
C loop is turned on.

A search method for pilot signal acquisition will be described below. In the PLL state with SW52 set to the b side, the input signal of PD38 (the output of OSC34 is
If the frequency divided by M) is fr, and the division number of DIV 86 is N, the output frequency fL of the VCO 36 is fL
=N×fr. Therefore, by changing the frequency division number N of DIV 86, fL changes by a step width of fr. For example, if fr = 1KHz, as mentioned above, if fL = 1,120MHz, N will be 1,120,000, and if it increases by 1,
fL =1,120.001MHz. Therefore, CO
By controlling this frequency division number N from the NT84 and changing fL, it is possible to search within the allocated band where the pilot signal exists. Here, the 1/P frequency divider of DIV 82 is used to make the pilot signal frequency extracted when AFC is ON the same frequency as fr, which is frequency-divided by 1/M of OSC 34. Therefore, although not shown,
When AFC is ON, fr and the pilot signal can be made to have the same frequency by simultaneously bypassing DIV 80 of 1/M frequency division, so this is not necessarily necessary.

With the above configuration, even if the pilot signal is cut off for some reason, the pilot signal will be sent out again by automatically switching to PLL and searching for pilot signal capture. The signal can be captured and the AFC loop can be re-established. FIG. 8 is a diagram showing a sixth embodiment of the present invention. CONT90 in this embodiment is also CONT8 in FIG.
Similarly to 4, after AFC is turned off due to pilot signal loss, the pilot signal is searched by changing the division ratio of DIV 86 for reacquisition. Judgment DET 70
This is done based on the information from the signal from the ALM 74 and the loop state from the ALM 74.

[0028]

Effects of the Invention As explained above, according to the present invention, in a system using a pilot signal, stable AF
A C loop can be formed, and even if the pilot signal is cut off for some reason, it is possible to reacquire the pilot signal through a stable search.

Furthermore, a stable output signal can be obtained even without a pilot signal when carrying out a return test to the local station during maintenance and inspection. In addition, when used in a system that does not have a pilot signal, a highly stable output signal can be obtained even when AFC is OFF, and a highly stable output signal can be obtained regardless of AFC ON/OFF, which improves the performance of the receiving device. It greatly contributes to improvement.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram representing a first embodiment of the present invention.

FIG. 3 is a diagram representing a second embodiment of the invention.

FIG. 4 is a diagram showing a detailed configuration of the loop filter in FIG. 3;

FIG. 5 is a diagram representing a third embodiment of the present invention.

FIG. 6 is a diagram representing a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a sixth embodiment of the present invention.

FIG. 9 is a diagram showing the configuration of a conventional AFC.

FIG. 10 is a diagram showing an example of arrangement of received signals.

[Explanation of symbols]

30...Frequency converter 32...Narrowband filter 34...High stability oscillator 36...Voltage controlled oscillator 38...Phase comparator 40...Loop filter 50...Frequency divider 52...Switch

Claims (6)

[Claims] 1. Frequency conversion means (10) that performs frequency conversion by mixing a local oscillation signal with an input signal, and bandpass filter means that extracts only a signal of a specific frequency from the output signal of the frequency conversion means (10). (12), a reference oscillation means (14) that outputs a signal at a reference frequency, an output signal of the bandpass filter means (12), and the reference oscillation means (14).
phase comparison means (16) for comparing the phase and frequency with
and voltage controlled oscillation means (18) for outputting a signal whose frequency is controlled according to the comparison result of the phase comparison means (16) as the local oscillation signal. a frequency dividing means (20) for dividing the output signal of the means (18) by a predetermined frequency division number and outputting the resultant signal; and either the output of the frequency dividing means (20) or the output of the bandpass filter means (12). An automatic frequency control circuit characterized in that it comprises a switching means (22) which switches and selects one of the two and supplies the selected one to the phase comparing means (16). 2. A loop filter (40) that removes high frequency components of the output signal of the phase comparison means (16) and supplies the removed signal to the voltage controlled oscillation means (18);
2. The automatic frequency control circuit according to claim 1, further comprising control means (54) for switching the time constant of said loop filter (40) in synchronization with the switching of said loop filter (40). 3. Signal detection means (70) for detecting the presence or absence of a signal passing through the bandpass filter means (12); and when the signal detection means (70) does not detect a signal, the switching means automatically 3. The automatic frequency control circuit according to claim 1, further comprising control means (72) for causing the frequency dividing means (20) to select the output of the frequency dividing means (20). 4. Control means for automatically causing the switching means (22) to select the output of the frequency dividing means (20) when an out-of-synchronization in the phase comparison means (16) is detected.
74, 76). The automatic frequency control circuit according to claim 1 or 2, further comprising: 74, 76). 5. The frequency dividing means is a variable frequency divider (86) whose frequency division number can be varied according to an external signal, and the control means controls the switching means (22) to control the variable frequency divider (86). 86
) after selecting the output of the signal detecting means (70).
4. The automatic frequency control circuit according to claim 3, further comprising a controller (84) for sequentially applying different frequency division numbers within a predetermined range to the variable frequency divider (86) until the signal is detected. 6. The frequency dividing means is a variable frequency divider (86) whose frequency division number can be varied by an external signal, and the control means is configured to cause the switching means (22) to control the variable frequency divider (86). 86
) after selecting the output of the signal detecting means (70).
4. The automatic frequency control circuit according to claim 3, further comprising a controller (90) for sequentially applying different frequency division numbers within a predetermined range to the variable frequency divider (86) until the signal is detected and the control loop is stabilized.