JPH04364752A - Semiconductor substrate treatment system - Google Patents

Abstract

PURPOSE:To arbitrarily set and change the conveyance sequence of wafers to individual treatment devices regarding a semiconductor substrate treatment system, especially the semiconductor substrate treatment system wherein the conveyance mechanism of semiconductor substrates is controlled. CONSTITUTION:A semiconductor substrate treatment system is provided with the following: a plurality of treatment devices 12 to 17 which treat semiconductor substrates; a conveyance mechanism 18 which conveys the semiconductor substrates to the individual treatment devices 12 to 17; and a control device 19 which controls the treatment devices 12 to 17 and the conveyance mechanism 18. The system is featured in such a way that the control device 19 arbitrarily sets and changes the conveyance sequence of the semiconductor substrates to the individual treatment devices 11 to 17 and that the device freely combines the treatment sequence of the arranged treatment devices 12 to 17.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate processing system, and particularly to one used for controlling a semiconductor substrate transport mechanism.

0002

2. Description of the Related Art A conventional semiconductor substrate (hereinafter referred to as wafer) processing system will be described below with reference to FIG. FIG. 6 is a plan view showing a plurality of conventional wafer processing apparatuses.

In the wafer processing system shown in FIG. 6, a wafer storage device 61, wafer processing devices 62, 6
3, a buffer interrupter 64, a wafer processing device 65, a pass device 66, and wafer processing devices 67, 68.
and the wafer storage device 69 are arranged in numerical order.

[0004] Furthermore, between each processing device 61 to 69 (for example,
A transport mechanism (not shown) is provided between the wafer storage device 61 and the wafer processing device 62, between the wafer processing device 62 and the wafer processing device 63, etc.). The control unit 6b is connected to each of the processing devices 61 to 69 via a communication cable 6c, and operates each transport mechanism (not shown). Further, the operation panel 6d is connected to the control section 6b, and instructions for each process are inputted to the control section 6b from the operation panel 6d. Next, the operation of the conventional wafer processing apparatus shown in FIG. 6 will be explained. First, the operator selects the operation panel 6d.
Inputs an instruction to start semiconductor substrate processing.

[0005] Upon receiving this start input signal, the control unit 6b transmits each control signal to each of the processing devices 61 to 69 and a transport mechanism (not shown) disposed between each processing device via a communication cable 6c. . Upon receiving this control signal, each processing device 61
The wafers 69 to 69 perform each process, and after the process is completed, the wafer is transferred to the next processing device by a transfer mechanism.

[0006]

[Problems to be Solved by the Invention] In conventional wafer processing equipment, each processing equipment is arranged in a predetermined order, so depending on the processing content of the wafer, even unnecessary processing equipment may be placed on the wafer transport path 6a. Because of the
For this reason, there was a problem in that unnecessary heat treatment and the like were automatically performed during transportation.

[0007]Furthermore, depending on the wafer processing conditions, there may be cases where it is desired to change the processing order of the wafers, and in that case, there is a problem in that the wafer transport mechanism needs to be significantly changed.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor substrate processing system in which a plurality of wafer processing devices are installed, in which the transfer order of wafers can be arbitrarily set. do.

[0009]

[Means for Solving the Problems] A semiconductor substrate processing system of the present invention includes a plurality of processing apparatuses for processing semiconductor substrates;
A transport mechanism for transporting the semiconductor substrates to each of the processing apparatuses, and a control apparatus for controlling the processing apparatus and the transport mechanism, wherein the control apparatus arbitrarily controls the order in which the semiconductor substrates are transferred to each of the processing apparatuses. The feature is that it can be set and changed.

0010

[Operation] In the above configuration, the control device freely sets and changes the order of transport to each processing device. The control device transmits control signals to the transport mechanism and each processing device so as to control the transport mechanism and each processing device according to the set or changed transport order. The transport mechanism receives a control signal from the control device and transports the semiconductor substrate to each processing device. The processing device to which the semiconductor substrate has been transported processes this semiconductor substrate.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor substrate (hereinafter referred to as wafer) processing system according to an embodiment of the present invention. Note that FIG. 1 is a plan view showing a state in which a plurality of each processing device is arranged. FIG. 2 is a block diagram showing the electrical configuration of a wafer processing apparatus according to an embodiment of the present invention. first,
The configuration of the wafer processing system shown in FIG. 1 will be explained.

The wafer storage device 11 in FIG. 1 is located at the left end of the drawing and stores wafers. Adjacent to the wafer storage device 11, wafer processing devices 12 to 17 are arranged in numerical order.

The wafer storage device 11 and the wafer processing devices 12 to 17 are equipped with sensors 261 to 2 shown in FIG.
68 are arranged for each device. (For example, the wafer storage device 11 is equipped with a sensor 261.) The sensors 261 to 268 are connected to each device 11 to 17.
This is to detect the presence or absence of a wafer in the area.

A wafer transport device 18 is arranged at a position facing the wafer storage device 11 and the wafer processing devices 12 to 17. Note that the wafer transport device 18 is equipped with a moving mechanism (not shown) for making the wafer transport device 18 movable. An arrow 1a indicates the direction of movement of the wafer transport device 18. The arrow 1b indicates the wafer receiving direction of the wafer transport device 18.

The wafer storage device 11, wafer processing devices 12 to 17, and wafer transfer device 18 are connected to a control section 19 via a control section/wafer processing device communication cable 1c. The control unit 19 includes a wafer storage device 11, wafer processing devices 12 to 17, and a wafer transfer device 18.
control.

The control section 19 also includes a main CPU 21. The main CPU 21 communicates with an operation panel 1d and an HDD (hard disk drive) 22 via a bus 27.
It is connected to an FDD (floppy disk drive) 23, a memory 24, sensors 261 to 268, a wafer storage device 11, wafer processing devices 12 and 17, a transfer device 18, and sub CPUs 251 to 257. The control unit 19 also controls the main C as shown in FIG.
In addition to PU21, sub CPU251 to 257 and HDD2
2, an FDD 23, and a memory 24.

It should be noted that an operation panel 1d is connected to the control section 19. The operation panel 1d is used to register the processing contents of each processing device and the wafer transport processing order in the control section 19 by assigning an appropriate name. The operation of the wafer processing apparatus shown in FIGS. 1 and 2 will be described below with reference to FIGS. 3 and 4.

FIG. 3 is a flowchart showing a transfer process in a wafer transfer apparatus according to an embodiment of the present invention. FIG. 4 is a diagram showing a wafer processing order according to an embodiment of the present invention. Incidentally, in the memory 24 in the control unit 19, the processing contents of each processing device and the wafer transfer processing order are registered in advance with names through the operation panel 1d. First, the name registered in the memory 24 is specified from the operation panel 1d.

Once the name is specified, the operation panel 1d transmits an instruction to start wafer processing and the processing contents of each processing device to the main CPU 21 based on the specified name, as shown in FIG. Flow is started. In step S1, an instruction to start processing from the operation panel 1d is confirmed, and the flow advances to step S2.

In step S2, the processing contents of the necessary processing apparatus are stored in the memory 24 based on the wafer transfer processing order of the specified name registered in the control unit 19 and the wafer transfer processing order, and the processing contents are stored in the memory 24 as shown in FIG. Expand to a data table. After creating the data table, the flow goes to step S
Proceed to step 3.

In step S3, the processing apparatus that first receives the wafer is searched from the data table shown in FIG.
Determine the wafer transfer source and wafer transfer destination. For example, as shown in FIG. 4, if the processing order number 1 is the wafer processing device 11 and the processing order number 2 is the processing device 13, the wafer transfer source is the wafer storage device 11, and the wafer destination is the processing device 13. It is determined that the device is device 13. After determining the source and destination of the wafer, the flow advances to step S4.

In step S4, the destination processing device 13
The receiving status of the wafers is checked by the sensor 263 shown in FIG. If it is determined that the processing device 13 is ready to receive the wafer, the flow advances to step S5. On the other hand, if it is determined in step S4 that the destination processing apparatus 13 is unable to receive the wafer, the flow repeats step S4 again.

In step S5, the wafer storage device 11
An instruction is issued to the wafer transport device 18 to receive the wafer from the wafer and transport it to the processing device 13, and the flow advances to step S6.

Thereby, the wafer transfer device 18 receives the wafer from the wafer storage device 11, moves the wafer to a position facing the wafer processing device 13 while holding the wafer by a moving device (not shown), and sets the wafer in the wafer processing device 13. do.

In step S6, the sensor 263 shown in FIG. 2 provided in the processing apparatus 13 checks whether the processing apparatus 13 has received the wafer. Processing device 1
If it is determined that No. 3 has received the wafer, the flow proceeds to step S7. On the other hand, if it is determined that the processing device 13 has not received the wafer, the flow repeats step S6 again. In step S7, an instruction to start wafer processing is transferred to the sub CPU 251, and the flow advances to step S8. In step S8, the processing device 13 starts predetermined wafer processing, and the flow advances to step S9. In step S9, the processing of the predetermined wafer started in step S8 is finished, and the flow returns to step S4 again to perform the processing from step S4 onwards.

Thereafter, the processing status of each of the processing apparatuses 12 to 17 is checked in accordance with the wafer transfer source and transfer destination in the internal data table of the control unit 19, which is similarly searched, and transfer processing is performed. Note that after the wafer processing is completed, the transport device transports the wafer to the wafer storage device 11 again. The wafer storage device 11 stores the wafer, and the wafer processing device completes a series of wafer processing.

With the above configuration, the processing order of each processing apparatus can be arbitrarily combined, so that even a wafer processing apparatus that has once been designated for processing can be designated again, that is, it can be designated again in the wafer transport processing order.

In the above embodiment, the transfer device 18 can only move in one direction as indicated by the arrow 1a (wafer transfer device movement direction), but as shown in FIG.
In wafer processing systems where
It is possible to move in both left and right directions, and the same transport processing method as the embodiment shown in FIG. 1 is possible. The wafer processing system shown in FIG. 5 will be described below. FIG. 5 shows a wafer processing system in which a wafer transport device 59 is at the center of each processing device.

Reference numeral 51 in FIG. 5 is a wafer storage device, and numerals 52 to 58 are wafer processing devices. code 5
9 is a conveying device. The wafer storage device 51 and the wafer processing devices 52 to 58 are arranged in a circular shape so as to surround the transfer device 59.

The arrow 5a indicates the direction of movement of the wafer transport device, and indicates that the wafer transport device 59 can rotate clockwise and counterclockwise with respect to the wafer storage device 51.

The wafer storage device 51, the wafer processing devices 52 to 58, and the wafer transfer device 59 include a control section 5.
0 is connected. Further, an operation panel 5d is connected to the control section 50.

Note that the wafer processing system shown in FIG.
It operates in the same way as the wafer processing apparatus shown in FIG. Therefore, a detailed explanation of the operation of the wafer processing system shown in FIG. 5 will be omitted here.

[0034]

[Effects of the Invention] With the above configuration, the wafer transfer order can be arbitrarily set and changed, so that processing can be performed using only the necessary processing equipment. Therefore, there is no need to transport the wafer to a device that does not perform processing, eliminating unnecessary processing of the wafer and time loss, and shortening the wafer processing time. Furthermore, since it is possible to perform processing again on the equipment that has previously performed the processing or the equipment that has passed the wafer, special processing conditions can be set.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor substrate processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a semiconductor substrate processing system according to an embodiment of the present invention.

FIG. 3 is a flowchart of semiconductor substrate processing according to an embodiment of the present invention.

FIG. 4 is a diagram showing a processing order of a semiconductor substrate according to an embodiment of the present invention.

FIG. 5 is a diagram showing a semiconductor substrate processing system according to another embodiment of the present invention.

FIG. 6 is a diagram showing a conventional semiconductor substrate processing system.

[Explanation of symbols]

11, 51... Wafer storage device, 12-17, 52-5
8... Wafer processing device, 18, 59... Wafer transfer device, 19, 50... Control unit, 1a... Wafer transfer device movement direction, 1b... Wafer receiving direction of wafer transfer device, 1
c, 5c...control unit/wafer processing equipment communication cable, 1
d, 5d...Operation panel, 21...Main CPU, 22...H
DD (hard disk drive), 23...FDD (floppy disk drive), 24...memory, 251-2
57...Sub CPU, 261-268...Sensor.

Claims (4)

[Claims] 1. A plurality of processing means for processing semiconductor substrates, a transport means for transporting the semiconductor substrate to each of the processing means, and a control means for controlling the processing means and the transport means, A semiconductor substrate processing system characterized in that means arbitrarily sets the order in which the semiconductor substrates are transported to each of the processing means. 2. The semiconductor substrate processing system according to claim 1, wherein the control means sets the transport order of the semiconductor substrates so that the same processing means performs the processing at least twice. 3. The semiconductor substrate processing system according to claim 1, wherein the transport means moves in a straight line to process the semiconductor substrate. 4. The semiconductor substrate processing system according to claim 1, wherein the conveying means rotates clockwise and counterclockwise to convey the semiconductor substrate.