JPH04359461A - Lead frame for resin-sealed semiconductor device - Google Patents

Lead frame for resin-sealed semiconductor device

Info

Publication number
JPH04359461A
JPH04359461A JP13452691A JP13452691A JPH04359461A JP H04359461 A JPH04359461 A JP H04359461A JP 13452691 A JP13452691 A JP 13452691A JP 13452691 A JP13452691 A JP 13452691A JP H04359461 A JPH04359461 A JP H04359461A
Authority
JP
Japan
Prior art keywords
lead
lead frame
resin
adhesive
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13452691A
Other languages
Japanese (ja)
Other versions
JP2970060B2 (en
Inventor
Masahiko Ichise
理彦 市瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13452691A priority Critical patent/JP2970060B2/en
Publication of JPH04359461A publication Critical patent/JPH04359461A/en
Application granted granted Critical
Publication of JP2970060B2 publication Critical patent/JP2970060B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate a slip of an inner lead in a lead frame for an LOC at the time of connecting, and to obviate a deviation of a connecting position. CONSTITUTION:A recess 5 or a through hole is provided on a lower surface of an inner lead 1 in a lead frame for an LOC, and a slip of a semiconductor chip 3 at the time of connecting is eliminated. Adhesive of an adhesive layer of a tape 2 is introduced into the recess 5 or the hole 6 so that the lead 1 is scarcely slipped. Further, the adhesive surface of the lead to the adhesive is increased to improve its adhesive strength, and the lead 1 is further scarcely slipped.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、樹脂封止型半導体装置
用リードフレームに関し、特にＬＯＣ（Ｌｅａｄ　　Ｏ
ｎ　　Ｃｈｉｐ）用リードフレームに関する。[Field of Industrial Application] The present invention relates to a lead frame for a resin-sealed semiconductor device, and particularly to a lead frame for a resin-sealed semiconductor device.
n Chip) lead frame.

【０００２】0002

【従来の技術】従来のＬＯＣ用リードフレームは、図４
に示す様に内部リード１Ｃの下に両面に接着層を有する
テープ２が接着されている。半導体素子３は、テープ２
の下面に貼り付けられるような形で固着されて搭載され
る。次に、Ａｕワイヤ４によって内部リード１Ｃと半導
体素子３とが電気的に接続される。[Prior Art] A conventional lead frame for LOC is shown in FIG.
As shown in the figure, a tape 2 having adhesive layers on both sides is adhered below the internal lead 1C. The semiconductor element 3 is attached to the tape 2
It is attached and installed in such a way that it can be pasted on the underside of the . Next, the internal lead 1C and the semiconductor element 3 are electrically connected by the Au wire 4.

【０００３】この様にＬＯＣ用リードフレームは、内部
リード１Ｃが半導体素子３の上部に引き回せるため、半
導体素子の周辺に内部リード１ａを引き回す領域を必要
としない。従ってＬＯＣの樹脂封止型半導体装置は、半
導体素子搭載部を有し、その上部に半導体素子３を搭載
し、その周辺に内部リードを引き回す樹脂封止型半導体
素子に比べてより大きな半導体素子が搭載できる。[0003] In this way, the LOC lead frame does not require an area around the semiconductor element to route the internal leads 1a because the internal leads 1C can be routed above the semiconductor element 3. Therefore, the resin-sealed semiconductor device of LOC has a semiconductor element mounting part, the semiconductor element 3 is mounted on the upper part, and the semiconductor element is larger than the resin-sealed semiconductor device which has internal leads routed around it. Can be installed.

【０００４】0004

【発明が解決しようとする課題】この従来のＬＯＣ用リ
ードフレームでは、内部リード１Ｃの下面が平面である
ために、滑りやすくなっており、そのためボンディング
時において内部リード１Ｃが動いてしまい、内部リード
１ＣとＡｕリード４との接合が不十分になってしまう問
題点がある。[Problems to be Solved by the Invention] In this conventional LOC lead frame, the lower surface of the internal lead 1C is flat, making it slippery. Therefore, the internal lead 1C moves during bonding, causing the internal lead to slip. There is a problem that the bonding between 1C and the Au lead 4 becomes insufficient.

【０００５】本発明の目的は、このような問題を解決し
、内部リードのずれをなくし、Ａｕリードとその接合を
良好にできる樹脂封止型半導体装置用リードフレームを
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a resin-sealed semiconductor device that can solve these problems, eliminate misalignment of internal leads, and improve the bonding between Au leads and the leads.

【０００６】[0006]

【課題を解決するための手段】本発明の構成は、内部リ
ードの下部に半導体素子を固着して搭載してなる樹脂封
止型半導体装置用リードフレームにおいて、前記内部リ
ードはその下面に凹部又はスルーホールを備えたことを
特徴とする。[Means for Solving the Problems] The present invention provides a lead frame for a resin-sealed semiconductor device in which a semiconductor element is fixedly mounted on the lower part of an internal lead, in which the internal lead has a recess or It is characterized by having a through hole.

【０００７】[0007]

【実施例】図１は本発明の第一の実施例のＬＯＣ用リー
ドフレームの断面図である。図のように、内部リード１
はその下面がエッチングにより球面状に凹部５を設けら
れている。この凹部５にテープ２の上面の接着層が入り
こんで、内部リード１は滑りにくくなっている。さらに
、平面の場合より接着層と内部リード１の接着面が増加
するため、内部リード１とテープ２との接着力も向上す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a lead frame for LOC according to a first embodiment of the present invention. As shown, internal lead 1
has a spherical recess 5 formed on its lower surface by etching. The adhesive layer on the upper surface of the tape 2 enters the recess 5, making it difficult for the internal lead 1 to slip. Furthermore, since the adhesive surface between the adhesive layer and the internal lead 1 is increased compared to the case of a flat surface, the adhesive strength between the internal lead 1 and the tape 2 is also improved.

【０００８】図２は本発明の第二の実施例のＬＯＣ用リ
ードフレームの断面図である。この実施例では、凹部５
ａがプレスによりＶノッチの形で内部リード１ａの下面
に設けられている。FIG. 2 is a sectional view of a lead frame for LOC according to a second embodiment of the present invention. In this embodiment, the recess 5
A is provided in the form of a V-notch on the lower surface of the internal lead 1a by pressing.

【０００９】図３は本発明の第三の実施例のＬＯＣ用リ
ードフレームの断面図である。前記２例の場合、半導体
素子３をテープ２に貼り付ける際に凹部５，５ａに空気
が侵入してしまい、テープ２の接着層の接着剤が十分に
凹部に入り込まないという不具合が発生する可能性があ
る。そのため、本実施例では、凹部５，５ａの代りにス
ルーホール６を設けることにより、内部リード１ｂの下
面の空気が抜ける様にして確実にテープ２の接着層の接
着剤がスルーホール６に入り込むようにしている。FIG. 3 is a sectional view of a lead frame for LOC according to a third embodiment of the present invention. In the above two cases, when attaching the semiconductor element 3 to the tape 2, air may enter the recesses 5, 5a, and a problem may occur in which the adhesive of the adhesive layer of the tape 2 does not fully enter the recesses. There is sex. Therefore, in this embodiment, by providing a through hole 6 instead of the recesses 5 and 5a, the air on the lower surface of the internal lead 1b is released, and the adhesive of the adhesive layer of the tape 2 is ensured to enter the through hole 6. That's what I do.

【００１０】0010

【発明の効果】以上説明したように本発明は、テープの
接着層の接着剤がリードフレームの凹部やスルーホール
に入りこむ様にして、内部リードを滑りにくくし、さら
にテープとの接着面が増加したのでテープと内部リード
の接着力が向上し、平面の内部リードの場合に比べてさ
らに滑りにくくなっている。このような効果から従来は
２〜３％発生していた内部リードの滑りによるボンディ
ング不良が無くなったという効果が得られている。[Effects of the Invention] As explained above, the present invention allows the adhesive in the adhesive layer of the tape to enter the recesses and through holes of the lead frame, making the internal leads less likely to slip, and further increasing the adhesive surface with the tape. This improves the adhesion between the tape and the internal leads, making them even more difficult to slip compared to flat internal leads. These effects have resulted in the elimination of bonding defects due to internal lead slippage, which conventionally occurred at 2 to 3%.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の第一の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 1 is a sectional view of a lead frame for LOC according to a first embodiment of the present invention.

【図２】本発明の第二の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 2 is a sectional view of a LOC lead frame according to a second embodiment of the present invention.

【図３】本発明の第三の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 3 is a sectional view of a lead frame for LOC according to a third embodiment of the present invention.

【図４】従来例のＬＯＣ用リードフレームの断面図。FIG. 4 is a sectional view of a conventional LOC lead frame.

【符号の説明】[Explanation of symbols]

１　　　　内部リード ２　　　　テープ ３　　　　半導体素子 ４　　　　Ａｕワイヤ ５，５ａ　　　　凹部 ６　　　　スルーホール 1 Internal lead 2 Tape 3 Semiconductor device 4 Au wire 5, 5a Recessed part 6 Through hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　内部リードの下部に半導体素子を固着
して搭載してなる樹脂封止型半導体装置用リードフレー
ムにおいて、前記内部リードはその下面に凹部又はスル
ーホールを備えたことを特徴とする樹脂封止型半導体装
置用リードフレーム。1. A lead frame for a resin-sealed semiconductor device in which a semiconductor element is fixedly mounted on the lower part of an internal lead, characterized in that the internal lead is provided with a recess or a through hole on its lower surface. Lead frame for resin-sealed semiconductor devices.
JP13452691A 1991-06-06 1991-06-06 Lead frame for resin-sealed semiconductor device Expired - Fee Related JP2970060B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13452691A JP2970060B2 (en) 1991-06-06 1991-06-06 Lead frame for resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13452691A JP2970060B2 (en) 1991-06-06 1991-06-06 Lead frame for resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH04359461A true JPH04359461A (en) 1992-12-11
JP2970060B2 JP2970060B2 (en) 1999-11-02

Family

ID=15130384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13452691A Expired - Fee Related JP2970060B2 (en) 1991-06-06 1991-06-06 Lead frame for resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2970060B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0712159A3 (en) * 1994-11-08 1997-03-26 Oki Electric Ind Co Ltd Structure of resin molded type semiconductor
US6531784B1 (en) * 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0712159A3 (en) * 1994-11-08 1997-03-26 Oki Electric Ind Co Ltd Structure of resin molded type semiconductor
US6002181A (en) * 1994-11-08 1999-12-14 Oki Electric Industry Co., Ltd. Structure of resin molded type semiconductor device with embedded thermal dissipator
US6531784B1 (en) * 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Also Published As

Publication number Publication date
JP2970060B2 (en) 1999-11-02

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