JPH04358224A - Square foot calculating device - Google Patents

Abstract

PURPOSE:To provide the square soot calculating device without deteriorating performance while reducing the hardware scale of a multiplier. CONSTITUTION:The approximate inverse of a square root is indexed from a table information storing means 12 with the high order of a normalized operand outputted from a normalizing means 8 as an address, a partial square root is obtained by multiplying the inverse to the output of a remainder holding means 13, which defines the 0th remainder as an address, by a multiplying means 14, the partial square roots at respective repetitions are merged by a digit matching means 21 and an adding means 22, and the remainder at the next step of the repeated calculation is calculated by subtracting the product of the merged square root and the partial square root from the remainder by a multiplicand generating means 19, inverting means 20 and (R=SXT+T) arithmetic means 23.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a square root calculation device for a data processing device.

0002

2. Description of the Related Art A real number represented by double exponential division handled in the present invention is composed of four parts: an S part, an L part, an E part, and an M part. The S part represents the positive and negative sign bits, the L part represents the bit length of the E part, and the E part is combined with the L part to represent the exponent part. (Hereinafter, the S, L, and E parts will be collectively referred to as the double exponent part.) The M part, which is the remaining bits after removing the double exponent part from all the bits, represents the mantissa part. The above LE part can take any bit length from 2 to the total bit length (however, a multiple of 2), and in this double exponential division representation real number, IEE
It is possible to handle numbers with large or small absolute values that cannot be handled even with E standard double-precision floating point numbers. Regarding the correspondence between this double exponential division representation real numbers and real numbers,
Information Processing Society of Japan Journal Vol. 22 No. 6 (1
981) P521 526.

[0003] Conventionally, in many cases, square root calculation devices execute square root calculation using the Newton-Raphson method. To find the square root of a numerical value A, first find 1/√A, then multiply it by A to find √A. In the Newton-Raphson method, 1/√A is determined by convergence calculation, but the closer the initial value of the reciprocal is to the true value, the smaller the number of iterations required for convergence, and with a high-speed square root calculation device, it is about 3 to 4 times. What can be obtained by the convergence calculation of
This is shown in Publication No. 4, etc.

0004

However, in the above embodiment of the square root arithmetic unit based on the Newton-Raphson method, the mantissa part of the floating-point input operand is input as the multiplicand and multiplier, and the double exponent When calculating the square root of a divided representation real number, 31 bits x 3 corresponding to the maximum bit length of the mantissa with the leading bit added.
Requires a 1-bit multiplier. If the multiplication instruction and the square root operation instruction are not executed simultaneously, and the multiplier for executing the multiplication instruction is also used for executing the square root operation instruction, no problem arises. However, when there is no dependence on the data used between the multiplication instruction and the square root operation instruction, it is difficult to provide a 31-bit x 31-bit multiplier for the square root operation in order to execute the two instructions at the same time. This results in a huge increase in the amount of material, which poses a problem.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a square root calculation device that uses a multiplier whose bit length of the multiplier is smaller than the maximum bit length of the mantissa of a real number represented by double exponential division.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the square root calculation device of the present invention includes table information storage means for storing approximate reciprocals of square roots for input operands;
A remainder holding means when calculating a square root by repeating a certain number of bits from the highest order, and multiplying the remainder output from the remainder holding means and the approximate reciprocal of the square root output from the table information storage means as a multiplicand and a multiplier, respectively. a merging square root holding means for merging the square roots of each iteration using the upper part of the product outputted by the multiplication means as a partial square root; a remainder (R) output from the remainder holding means; Data (S) obtained by combining the output merged square root and the square root output from the multiplication means by the multiplicand generation means, and the partial square root (T) output from the multiplication means.
) and calculates (R-SxT).

[0007]

[Operation] Before explaining that the above configuration can perform a square root operation, the square root operation method used in the present invention will be explained. The square root of A is divided into groups of a certain number of bits starting from the higher order, and expressed as shown in (Equation 1).

[0008]

[Math 1]

On the other hand, if we square the sides of Equation 1 and transform the right-hand side, we obtain (Equation 2).

0010

[Math 2]

From (Equation 2), the square root can be found using the following procedure. (1) Multiply A (referred to as R0) by the reciprocal of a1, and set the fixed number of high-order bits of the result to a1.

(2) After calculating R1=R0-a1xa1, shift R1 to the left by the fixed number of bits in (1).

[0013] Below, (3) and (4) are repeated as many times as necessary. (3) Multiply Ri by the reciprocal of a1, and set the certain number of high-order bits of the result to ai+1. However, compared to a1 in (1), ai+1 is taken from the upper bit.

(4) Ri+1=Ri-{(a1+...
+ai)x2+ai+1}xai+1 After calculating, Ri+1 is shifted to the left by a certain number of bits in (1).

[0015] The table information storage means stores an approximate reciprocal of a1, which is indexed using the upper bits of A as an address, and is stored as the 0th remainder in the remainder storage means, R0 (=A) and a1. The product with the approximate reciprocal is calculated by the multiplication means, and a1 is obtained as the upper bit of the product. Next, the multiplicand generation means outputs a1 in the first iterative calculation, and R0, a1, and a1 are input to the (R-SxT) calculation means to obtain R1. Next, a1 is stored in the merge square root holding means, and after R1 is left-shifted by a certain number of bits, it is stored in the remainder holding means. Thereafter, the following process is repeated with i>1 until the bit length of the merged square root becomes equal to or greater than the bit length of the square root to be determined.

The product of Ri stored as the i-th remainder in the remainder holding means and the approximate reciprocal of a1 is calculated by the multiplication means, and ai+1 is obtained as the upper bit of the product. Next, the multiplicand generation means shifts (a1+...+ai) to the left by 1 bit, then merges it with ai+1 and outputs it as a multiplicand, Ri, {(a1+...+ai)x2+
ai+1}, ai+1 are input to the (R-SxT) calculation means to obtain Ri+1. Next, ai+1 is stored in the merging square root holding means, and after Ri+1 is left-shifted by a certain number of bits, it is stored in the remainder holding means.

In (Equation 1) and (Equation 2), it is initially assumed that there is no bit overlap between the partial square roots, but even if there is bit overlap between the partial square roots, the square root can be found using the above procedure. If possible, it is not necessary to set non-overlapping between partial square roots as a necessary condition. In the procedure shown above, the items that occupy a high proportion of the execution time of the square root operation are the index of the table information storage means, the multiplication time of the remainder and the approximate reciprocal of a1, and the multiplicand {(a1+...+ai)x2+a
i+1} and (R-SxT) calculation time. Among these, the multiplicand {(a1+...+ai)x2+a
i+1}, if there is no bit overlap between the partial square roots, simply shift a1, . Also, if there is 1 bit overlap between partial square roots, (a1+...+
ai), before storing ai in the merging square root holding means, in parallel with the calculation of (R-SxT), (a1+...
・+ai) does not affect the execution time of the square root operation. On the other hand, in the generation of the multiplicand (a1
+...+ai) to the left by 1 bit, then ai+
Since it is merged with 1, there is no need for addition even if ai and ai+1 have 1 bit overlap. If there is an overlap of 2 or more bits between partial square roots, the multiplicand (a1+...+ai)
Since addition is required to generate , the execution time of the square root operation increases. Therefore, the present invention targets cases where there is no bit overlap between partial square roots and cases where there is 1 bit overlap between partial square roots.

[0018]

Embodiment The approximate reciprocal of the square root is indexed using the 13 bits (x represents 0 or 1) of (Equation 3) as an address.

[0019]

[Math 3]

[0020] The numerical values stored in the table information storage means are:
Subtract 2-12 from the above address value to obtain a slightly larger reciprocal of the square root, and then find the reciprocal of this square root. The actual table stores the values of the reciprocal of the square root from 2-2 to 2-16, and the sign bit, which is always 0, and the 2-1 bit, which is always 1, are not stored directly in the table, but in the example, they are stored one by one. Since it would be troublesome to add an explanation, we will explain that 01 is included in the table as the first two bits. When performing multiplication, the multiplier is divided into groups of 3 bits with 1 bit overlap, and multiples of the multiplicand are generated according to Booth's algorithm shown in Table 1. , until two partial carries and a partial sum are obtained, and these two are added by a carry propagation adder to obtain the final product. In the multiplication of the approximate reciprocal of the remainder and the square root, 1 is added to the beginning of the value read from the table, and the inversion of the 1 bit adjacent to the right of the bit used as the address is added to the end. In multiplication, by using the bit added to the right as the least significant bit of the multiplier, the effect is increased by 2-16 times instead of 2-17 times. 0
For 1.00000000000, the values 2-2 to 2-16 stored in the table are all 1, and even if the bits less than the bits used in the address of the input operand are zero, the above 2-16 Due to the multiplication effect, a multiplication with a multiplier of 1.0000000000000000 is performed inside the multiplier.

[0021]

[Table 1]

In the calculation of (R-SxT), for the multiplier configuration described above, R is input as a kind of multiple to the tree-like carry-save adder group, and also the calculation of {R+Sx(-T)} By taking the 1's complement of the input of the multiplier and adding 1 as the least significant bit, the above 2-1 can be calculated.
The same effect as having an effect of 2 to 16 times instead of 7 times allows the multiplier to become a two's complement number with substantially (R-SxT) calculation means. It is well known to those skilled in the art that by appropriately extending the sign bit upwards, multiplication can be performed even on negative numbers in two's complement representation. In the following, the (R-SxT) calculation means is divided into the multiplier inversion means and the (R+SxT) calculation means, and adding 1 to the partial square root immediately before the input of the (R+SxT) calculation means is a square root calculation. Since it has a great influence on time, {R+
Sx(T+1)+(T+1)}, the effect of adding 1 to the partial square root is given to the multiplier by adding 0 to the least significant bit using the inversion means, and the effect of adding 1 to the partial square root is given to the multiplicand, This is handled by inputting it as a kind of multiple to a group of tree-like carry-save adders, and a calculation means of (R+SxT+T) is used.

[0023] In the following examples, specific numerical examples will be cited, but in order to save space, the numerical values are 16 unless otherwise specified.
It is displayed in decimal.

FIG. 1 shows a block diagram of a double-exponential division expression real number square root calculation device according to an embodiment of the present invention. The double exponential division representation real number square root calculation device of this embodiment inputs a 32-bit double exponential division representation real number in two's complement representation, outputs a 32-bit square root in two's complement representation, and outputs partial square root data. The bit length is 12 and there is 1 bit overlap between the partial square roots.

In FIG. 1, 1 is an input register, 2 is an exception detection means, 3 is a double exponent length determining means, 4 is a double exponent part separating means, 5 is a double exponent part processing means, and 6 is a leading bit addition. 7 is a normalization shift number calculation means, 8 is a normalization means, 9 is a digit adjustment shift number calculation means, 10 is a shifter, 11 is a multiplexer, 12 is a table information storage means, 13 is a remainder holding means, 14 is a multiplication 15 is a merging square root holding means, 16 is a multiplexer, 17 is a constant subtraction means, 18 is a multiplexer, 19 is a multiplicand generation means, 20 is an inversion means, 21 is a digit adjustment means, 22 is an addition means, 23 is (R+SxT+T) 24 is a digit adjustment means, and 25 is an exponent/mantissa merging means.

The operation of the double-exponential division expression real number square root calculation device shown in FIG. 1 will be described below using specific numerical examples. FIG. 2 shows the process in which an operand is processed by each means after it is input. First, 79B4C316 is input as an operand and set in input register 1. If the first bit of the input operand is 1, the exception detection means 2 detects it as a data exception, and notifies the external instruction execution control unit of the double-exponential division expression real number square root arithmetic unit that an exception has occurred. . In this numerical example (
(We omit this assumption below) The exception is not detected. In the double exponent length determining means 3, the first second of the input operand is
The length N of the series of 0 or 1 starting from the bit is determined and the double exponent length 2N+1 is output. In this embodiment, 9 is output. The double exponent part separating means 4 separates the first 9 bits into a double exponent part and the rest into a mantissa part and outputs them. In the double index part processing means 5, if the run of the L part in the double index part of the output of the double index part separation means 4 is composed of 1 and its length is 3 or more, the run of the L part is reduces the number of bits by 1, and the E part is a constant 1
After the number of bits is decreased by 1 by subtracting and deleting the least significant bit, a constant 1 is added. If the run of the L part in the double index part consists of 0 and its length is 2 or more,
The number of bits is reduced by 1 in the L part run, and the bit number is reduced by 1 in the E part by deleting the least significant bit. If the LE part is a binary number and it is 1101, it will be 1100, and the LE part will be 2.
If the number is 01, 1100, or 10 in decimal notation, it is expressed as 10. In either case, a double exponent part is embedded so that the most significant sign bit is at position 231, and the other bits are set to 0 and output as 32-bit data. Leading bit addition means 6 adds leading bit 1 to the mantissa. Normalized shift number calculation means 7
In this example, the number of shifts for bit normalization is calculated. For double index length 2N+1, when 231-2N is 1, 2N+11 is output, and when 231-2N is 0, 2N+12 is output. In this embodiment, 19 is output.

The normalizing means 8 receives an instruction for the number of shifts of 19 from the normalized shift number calculating means 7, and converts the input data into 1
Shift to the left by 9 bits and output 5A618B00000. The table information storage means 12 contains two of the normalization means 8.
13 bits from 43 to 231 are input, and 0D772 is output. Further, as the least significant bit of this output, the inverted bit of 230 of the normalizing means 8 is added, but in this embodiment, 1 is added, and the multiplier 14
The actual multiplier is 0D773. The multiplexer 11 uses a normalization means 8 that adds 4 bits of zero to the beginning.
This output is set in the remainder holding means 13. At this time, the merge square root holding means 15 is reset to zero. Multiplying means 14: 05A618B0000
Multiplication of 0 and 0D773 is performed, resulting in 04C108598
The product of 5,000,000 is found. multiplexer 16
Then, 13 bits from 260 to 248 of the multiplication means 14 are selected as the 1st partial square root of the 1 sign bit and the 12 data bits. The inverting means 20 inputs the partial square root, inverts the bits, adds 1 to the least significant bit, and outputs the result. However, only when the partial square root is negative in the third iteration, the inverting means 20 adds 0 to the least significant bit and outputs it. This is done to correct the fact that the partial square roots are calculated to be larger in the negative direction.

Furthermore, in the first iteration, the multiplicand generating means 19 embeds the output of the multiplexer 16 in 234 to 222 and outputs the other bits as zero. (
R+SxT+T) In the calculating means 23, the output of the remainder holding means 13 is R, the output of the multiplicand generating means 19 is S, and the inverting means 2
Input the output of 0 as T, and in the third iteration, execute (R+SxT+T) only if the partial square root is negative, otherwise execute the operation (R+SxT). (R+S
+T of xT+T) is input to the arborescent carry-save adder group with digit alignment such that the bit corresponding to the least significant bit of the partial square root is in the 20's place. (R+SxT+T)
The output FFFFB8700000 of the calculation means 23 is shifted left by 11 bits by the shifter 10, selected by the multiplexer 11, and set in the remainder holding means 13. On the other hand, constant subtraction means 17 subtracts 1 from the LSB of the output of multiplexer 16. The multiplexer 18 selects the output of the constant subtraction means 17 when the output of the multiplexer 16 is positive and (R+SxT+T) the output of the calculation means 23 is negative, and otherwise selects the output of the multiplexer 16. In the first iteration, the above conditions are judged and the output of the constant subtraction means 17 is selected.

The digit alignment means 21 performs digit alignment for merging the partial square roots in each iteration. Specifically, when the partial square root is negative, the first two bits of the 13 bits output from the multiplexer 18 are suppressed to zero, and
If the partial square root is positive, the 13 bits output from the multiplexer 18 are shifted so that the bit weights are balanced with those of the upper merged square root, and then output. For the first partial square root, the input data is sorted from 234 to 222 and output. The adding means 22 inputs the output of the merging square root holding means 15 and the output of the digit matching means 21, performs addition, and sets the result in the merging square root holding means 15.

Next, the second iterative calculation begins. The output of the table information storage means 12 is the same for the second and subsequent times as it was for the first time. The first remainder R1 set in the remainder holding means 13
Multiplying means 1 by 0D773 to FDC380000000
Multiplied by 4, the product FE1E2F528000000
0 is output. 1F0F from 261 to 249 is code 1
bit, selected by multiplexer 16 as the second partial square root of the 12 bits of data. The inverting means 20 inverts 1F0F to become 00F0, adds 1 as the least significant bit and outputs it, and the (R+SxT+T) arithmetic means 23 essentially performs an arithmetic operation on 00F1 as a multiplier. On the other hand, the multiplicand generating means 19 shifts the output of the merging square root holding means 15 to the left by 1 bit, and embeds 12 bits excluding the first bit of the 13 bits output from the multiplexer 16 from 222 to 211, and 0
Outputs 260787800. (R+SxT+T) The calculation means 23 inputs the output of the remainder holding means 13 as R, the output of the multiplicand generation means 19 as S, and the output of the inversion means 20 as T, and executes the calculation of (R+SxT). (R+Sx
T+T) Output of calculation means 23 00005168F800
is shifted to the left by 11 bits by the shifter 10, selected by the multiplexer 11, and set in the remainder holding means 13. Multiplexer 18 is multiplexer 1
6 is selected and output, and the digit matching means 21 selects and outputs 13.
Out of the bit input, suppress the first two bits to zero and set it to 1.
1 bit is aligned from 221 to 211. Addition means 2
2, the output of the merging square root holding means 15 and the output of the digit matching means 21 are input and added, and 13038780 is obtained.
Outputs 00. The merge square root holding means 15 sets the output of the addition means 22.

Next, the third iterative calculation begins. The output of the table information storage means 12 is the same as the first time. 028B4 of the second remainder R2 set in the remainder holding means 13
7C00000 is multiplied by 0D773 by the multiplication means 14, and the product 02241BB37B400000 is output. 0114 of 261 to 249 is selected by the multiplexer 16 as the third partial square root of the 1 code bit and 12 data bits. The inverting means 20 inverts 0114 to become 1EEB, adds 1 as the least significant bit and outputs it, and the (R+SxT+T) arithmetic means 23 essentially performs an operation using 1EEC as a multiplier. On the other hand, in the multiplicand generation means 19, the merged square root holding means 15
1 bit to the left, and remove the first bit of the 13 bits output from the multiplexer
Embed bits from 211 to 20, 026070F
114 is output. (R+SxT+T) The calculation means 23 inputs the output of the remainder holding means 13 as R, the output of the multiplicand generation means 19 as S, and the output of the inversion means 20 as T.
+SxT) is executed. (R+SxT+T) The output of the calculation means 23 is 00000EDDFABC. The multiplexer 18 selects and outputs the output of the multiplexer 16, and the digit alignment means 21 aligns the 13-bit input from 212 to 20. The adding means 22 inputs the output of the merging square root holding means 15 and the output of the digit alignment means 21, performs addition, and outputs 1303879120. Note that only when the partial square root is negative and the remainder is positive in the third iteration, the adding means 22 adds an initial carry to 20. In the digit adjustment shift number calculation means 9, the double exponent part processing means 5
A shift number 11 is output by adding a constant 4 to the bit number 7 of the double exponent part of the output. The digit adjustment means 24 receives an instruction of the shift number 11 from the digit adjustment shift number calculation means 9, replaces 236, which is the leading bit of the output of the addition means 18, with 0 and shifts it to the right by 11 bits. In the exponent/mantissa merging means 25, the output 74 of the double exponent part processing means 5
000000 and output 006070F2 of digit adjustment means 24
and outputs the final result 746070F2.

[0032]

As described above, the present invention provides a remainder holding means, a table information storage means for storing an approximate reciprocal of a square root, a multiplication means for calculating a partial square root, and a merging square root and a partial square root arranged from the upper order by iterative calculation from the remainder. Find the product of (R-S
xT) By providing the arithmetic means, the square root operation can be performed using a multiplier whose bit length of the multiplier is smaller than the maximum bit length of the mantissa part of the square exponential division representation real number. In this example, in order to simplify the explanation, a single-precision square-exponential partition representation real number is used, so the effect of the present invention is not sufficiently achieved. In this case, the Newton-Raphson method is 63
Whereas a bit by 63 bit multiplier is required, a 63 bit by 13 bit and a 63 bit by 17 bit multiplier are sufficient for the method according to the invention. As a result, it is possible to provide a data processing device that can simultaneously execute multiplication instructions and square root operation instructions without causing a large increase in the amount of hardware. In terms of performance, a square root arithmetic unit that allows bit duplication between partial square roots is Newtonian.
It is comparable to a square root calculation device using the Rapson method. Also, when using guard bits, round bits, and sticky bits to round the square root of the result, LS
After B, each bit is treated as a guard bit and a round bit, and then the remaining bits are logically summed with each bit of the remainder, resulting in a sticky bit, so it is necessary to perform a check in comparison with the Newton-Raphson method, etc. The second effect of the present invention is that there is no.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a double exponential partition representation real number square root calculation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing specific numerical examples of outputs of each component means in the same embodiment.

[Explanation of symbols]

1 Input register 2 Exception detection means 3 Double index length determination means 4 Double exponential separation means 5 Double exponent part processing means 6 Leading bit addition means 7 Normalization shift number calculation means 8 Normalization means 9 Digit adjustment shift number calculation means 10 Shifter 11, 16, 18 multiplexer 12 Table information storage means 13 Surplus holding means 14 Multiplication means 15 Merged square root holding means 17 Constant subtraction means 19 Multiplicand generation means 20 Reversing means 21 Digit alignment means 22 Addition means 23 (R+SxT+T) calculation means 24 Digit adjustment means 25 Exponent/mantissa merging means

Claims (1)

[Claims] 1. A square root arithmetic device for calculating the square root of a real number input operand representing a double exponent division representation, comprising: double exponent length determining means for determining the number of bits of a double exponent part; and said double exponent length determining means. A normalized shift number calculating means for calculating a normalized shift number based on the number of bits of the double exponent part to be output; and a double exponent part and a mantissa part based on the number of bits of the double exponent part output by the double exponent length determining means. double exponent part separation means for separating the double exponent part; double exponent part processing means for processing the double exponent part outputted by the double exponent part separation means according to the bit configuration of the double exponent part; and the double exponent part processing means. Digit adjustment shift number calculation means for calculating the number of digit adjustment shifts of the mantissa part based on the number of bits of the double exponent part output by the means; and a leading bit for adding leading bits to the mantissa output from the double exponent part separation means. adding means; normalizing means for left-shifting the output of the leading bit adding means according to the normalized shift number output from the normalized shift number calculating means; and square root approximation using the upper bits of the output of the normalizing means as an address. table information storage means for indexing reciprocal numbers; remainder holding means for repeatedly obtaining square roots by a certain number of bits starting from the highest order; a remainder outputted from said remainder holding means; and a remainder outputted from said table information storage means. a multiplier for performing multiplication by inputting approximate reciprocals of square roots as multiplicands and multipliers, respectively; merging square root holding means for merging the square roots of each iteration with the higher order of the product output from the multiplication means as a partial square root; an inverting means for bit by bit inverting the partial square root outputted by the means; and a multiplicand generating means for shifting the output of the merging square root holding means to the left by one bit and generating a multiplicand from the partial square root outputted from the multiplying means; a remainder (R) outputted by the remainder holding means;
By inputting the multiplicand (S) outputted by the multiplicand generating means and the multiplier (T) outputted by the inverting means, (R+S
xT) or (R+SxT+T) (R+
SxT+T) calculation means, a shift means for shifting the output of the (R+SxT+T) calculation means to the left by a number obtained by subtracting the overlapping bit length between adjacent partial square roots from the bit length of the partial square root, and an input of the remainder holding means. a multiplexer that selects the output of the normalization means and the output of the shift means as L of the partial square root output of the multiplication means;
a constant subtraction means that subtracts 1 from SB; a multiplexer that selects the partial square root output from the multiplication means and the output of the constant subtraction means and outputs it as a corrected partial square root; and a merged square root output from the merged square root holding means. for,
digit alignment means for performing digit alignment for merging corrected partial square roots output by the multiplexer; addition means for adding the merged square root and the output of the digit alignment means to output an updated merged square root; digit adjustment means for deleting the leading bit of the mantissa output by the means and shifting it to the right according to the digit adjustment shift number output from the digit adjustment shift number calculation means; and a double exponent part output from the double exponent part processing means. and a mantissa output from the digit adjustment means, and exponent/mantissa merging means for outputting a final result.