JPH04357721A - Space diversity in-phase synthesizing system - Google Patents

Abstract

PURPOSE:To prevent the generation of a free-run state and a large sized circuit scale by controlling an endless phase shifter with respect to an antenna whose incoming signal level is maximum at all times. CONSTITUTION:Endless phase shifters 34-36 adjusting the phase of a reception signal from plural antennas 31-33 at every antenna are provided respectively corresponding to all the antennas 31-33, and all reception signals in phase are simultaneously synthesized by controlling an endless phase shifter corresponding to other antenna with respect to an antenna whose incoming signal level is always maximum. Furthermore, the system is provided with an endless phase shifter control section 46 to control the endless phase shifters 34-36 and a microcomputer 47 is provided with the control section 46 and receives incoming signal level information and phase detection information from the antennas 31-33 as input information to generate a control signal controlling the endless phase shifters 34-36 and gives an output to each of the endless phase shifters 34-36.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space diversity in-phase combining system, and more specifically, to a space diversity in-phase combining system used in a space diversity (SD) in-phase combining circuit which is a receiving system of a digital multiplex radio transmitter/receiver. .

[0002] In recent years, various compensation techniques have been introduced to improve the quality of wireless lines, and for space diversity, there has been a shift from two-sided antennas to three-sided antennas, and the precision and high reliability of synthesis technology has improved. ization is required.

[0003] Furthermore, modulated waves are being multiplied, and multiple waves such as 1 multi, 3 multi, 6 multi, and 12 multi waves are transmitted all at once, with the aim of improving resistance to fading.

[0004] This requires an individual synthesis method corresponding to each multi, and the circuit scale tends to increase and the control becomes complicated. Therefore, commonization and simplification of circuits are required.

[0005]

2. Description of the Related Art FIG. 6 is a diagram showing a conventional three-sided antenna SD (space diversity) in-phase synthesis circuit.

[0006] In the figure, 1 is the main antenna (MAIN);
2 is the first sub-antenna (SUB1), 3 is the second sub-antenna (SUB2), 4 to 9 are hybrid circuits, 1
0 to 13 are phase detection/AGC circuits (PH DET
AGC), 14 and 15 are mixers (MIX), 16 is the first
an infinite phase shifter (EPS1), 17 is a second infinite phase shifter,
18 and 19 are infinite phase shifter control units (EPS CONT)
shows.

In this example, the antennas include a main antenna (MAIN) 1 and a first sub antenna (SUB1).
) 2 and a second sub-antenna (SIB2) 3.

The received signal of the main antenna 1 and the received signal of the first sub-antenna 2 are transmitted through a hybrid circuit (H) 6.
This combined output is combined with the second sub-antenna 3.
The hybrid circuit (H) 9 performs in-phase synthesis of the received signals of the three antennas to obtain an in-phase combined output of the received signals of the three antennas.

In the process of such in-phase synthesis, phase detection and
The AGC circuits 10 to 13 each perform phase detection from the signals demultiplexed by the hybrid circuits 4 to 8, and input the detection signals to mixers 14 and 15 at a constant level.

Mixers 14 and 15 detect the phase difference and send detection signals to infinite phase shifter control sections 18 and 19. The infinite phase shifter control units 18 and 19 control the first infinite phase shifter 16 and the second infinite phase shifter 17 using the phase difference detection signal.

[0011] Through this control, the hybrid circuits 6, 9
The above-mentioned in-phase synthesis is performed so that the phases of each signal input to the input signal are in the same phase.

0012

[Problems to be Solved by the Invention] The conventional devices as described above have the following problems.

(1) Due to the level cut of the main antenna,
A free run state occurs. In other words, if the received signal level of the antenna drops below a predetermined reference value due to fading or equipment failure, the infinite phase shifter will no longer be able to adjust the phase, resulting in a free run state and normal operation. It becomes impossible to obtain an in-phase composite output.

(2) The circuit scale increases. (3) The number of components used in the circuit increases, making it difficult to obtain a good NF value (noise figure).

SUMMARY OF THE INVENTION It is an object of the present invention to solve these conventional problems, to prevent the occurrence of a free-run state and an increase in circuit scale, and to ensure a good NF value.

[0016]

[Means for Solving the Problem] FIG. 1 is a diagram showing the principle of the present invention, in which 31 is a first antenna (ANT1), 32
is the second antenna (ANT2), 33 is the third antenna (ANT3), 34 is the first infinite phase shifter (EPS1),
35 is a second infinite phase shifter (EPS2), 36 is a third infinite phase shifter (EPS3), 37 to 39 are hybrid circuits for splitting (H), and 40 is a hybrid circuit for in-phase synthesis (H).
), 41 to 43 are phase detection/AGC circuits (PH DE
TAGC), 44 is an incoming signal level monitor circuit, 45 is a phase difference detection circuit, 46 is an infinite phase shifter control circuit, 47 is a microcomputer, and 48 is a data latch section.

[0017] In order to solve the above problems, the present invention is constructed as follows. (1) In a space diversity in-phase combining method in which received signals from a plurality of antennas 31 to 34 are in-phase combined, infinite phase shifters 34 to 36, which adjust the phase of received signals from the antennas for each antenna, are antenna 31
- 34, and by always using the antenna with the highest incoming signal level as a reference and controlling the infinite phase shifters corresponding to the other antennas, the phases of the received signals from each antenna are set in the same phase. All the received signals are combined at the same time.

(2) An infinite phase shifter control unit 46 is provided for controlling the infinite phase shifters 34 to 36, and a microcomputer 47 is provided in the infinite phase shifter control unit 46.
The microcomputer 47 generates control signals for controlling the infinite phase shifters 34 to 36 using the incoming signal level information and phase detection information from each of the antennas as input information, and generates control signals for controlling the infinite phase shifters 34 to 36. output to devices 34 to 36.

[0019]

[Operation] The operation of the present invention based on the above configuration will be explained with reference to FIG. First infinite phase shifter (EPS1) 34
, the second infinite phase shifter (EPS2) 35, and the third infinite phase shifter (EPS3) 36 are connected to the first antenna (AN), respectively.
T1) 31, second antenna (ANT2) 32, and third antenna (ANT3) 33, and phase adjustment is performed so that the received signals from each antenna are in phase.

In this case, the infinite phase shifter control section 46 controls the infinite phase shifters corresponding to the other antennas while keeping the infinite phase shifter corresponding to the antenna with the highest incoming signal level fixed, thereby adjusting the phase. I do.

First, the incoming signal level monitor circuit 44 monitors the incoming signal level of each antenna, and inputs the information to the infinite phase shifter control section 46. Further, the phase difference detection circuit 45 detects the phase difference between each antenna, and inputs the phase detection information to the infinite phase shifter control section 46.

In the infinite phase shifter control section 46, the microcomputer 47 uses the input information to generate control information for controlling the infinite phase shifter, and after latching it into the data latch section 48, Control information is sent to each infinite phase shifter 34-36.

Using this control information, each infinite phase shifter adjusts the phase of the received signal from each antenna for each antenna, so that the phases of all the received signals are in the same phase.

The in-phase received signals from each antenna are simultaneously combined by the in-phase combining hybrid circuit 40 to obtain an output signal (IF OUT).

[0025] With this arrangement, the configuration of the main signal system from each antenna to obtaining the in-phase combined output (IF OUT) is the same for all antennas, so that the same NF value is obtained. In addition, a good NF value can be ensured in terms of circuit configuration.

Furthermore, since the infinite phase shifters of the other antennas are controlled using the antenna with the highest incoming signal level as a reference, a free run state will not occur unless the level of all antennas is interrupted.

Furthermore, even if the number of carriers increases due to the introduction of a microcomputer into the infinite phase shifter control section, by using the microcomputer in a time-sharing manner, the infinite phase shifter control section can control all carriers at once. It becomes possible.

Furthermore, by employing each of the above configurations, even if the number of antennas increases, it is possible to prevent the circuit scale from increasing.

[0029]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

(Description of the first embodiment) FIGS. 2 to 5 are diagrams showing the first embodiment of the present invention, in which FIG. 2 shows a three-sided antenna SD in-phase synthesis circuit, and FIG. 3 shows an incoming call level monitor circuit. 4 is a block diagram of the phase detection circuit, and FIG. 5 is a processing flowchart of the EPS control section.

In the figure, the same reference numerals as in FIG. 1 indicate the same parts. Further, 49 is a D/A (digital/analog) converter, 50 is a ROM, 51 to 53 are phase control registers, 5
5 is a comparison section, 56 is a signal conversion section, A, B, and C are comparators, INV1 to INV3 are inverters, AND1, A
ND2 is an AND gate, OR1, OR2 are an OR gate,
57 is a phase detection section, 58 is a comparison section, Mix1 to Mix3
is a mixer, and WC1 to WC3 are window comparators.

[0032] In this embodiment, a three-sided antenna is used to
(Space diversity) This is an example of performing in-phase synthesis.
The circuit is shown in FIG.

The three-sided antenna SD in-phase synthesis circuit shown in FIG.
infinite phase shifter (EPS1) 34, second antenna (AN
a second infinite phase shifter (EPS2) 35 connected to T2);
, a third infinite phase shifter (EPS3) 36 connected to the third antenna (ANT3), and a branching hybrid circuit 37
~39, in-phase synthesis hybrid circuit 40, phase detection/
AGC circuit (PH DET AGC) 41 to 43,
Incoming call level monitor circuit 44, phase difference detection circuit 45, infinite phase shifter control section (hereinafter simply referred to as "EPS control section") 46
will be established.

The EPS control section 46 is provided with a microcomputer 47, a data latch section 48, and a D/A (digital/analog) converter 49, and the microcomputer 47 includes a ROM 50 and phase control registers 51 to 53. The EPS (infinite phase shifter) is controlled by the microcomputer's program processing.

Further, the ROM 50 stores in advance a control information table in which control information for EPS control is registered. The phase control registers 51 to 53 are registers for storing current phase value data corresponding to the first, second, and third antennas, respectively.

For example, the phase control register 51 includes the first
The current value data of the phase of the second antenna (ANT1) 31 is stored in the phase control register 52.
In addition to storing the current value data of the phase of NT2)32,
The phase control register 53 includes a third antenna (ANT3).
)33 phase current value data is stored.

Note that the current phase value data is stored in advance as predetermined data, and then, based on the phase detection information of each antenna, the data is corrected (±1) using the method described later, and the current value of the phase is obtained. Data.

The current value data of the phase stored in each of the phase control registers 51 to 53 described above is directly transferred to the RO.
This address is used as the address of M50, and the control information table is accessed using this address to read out the control information.

The data latch section 48 latches the control information read from the ROM 50, and this control information is converted into an analog signal by the D/A converter 49 and sent to the first, second, and third signals. It is sent as a control signal to infinite phase shifters 34-36.

Note that the data latch section 48 is capable of latching control information separately for each of the infinite phase shifters 34 to 36 corresponding to each antenna. Then, in the D/A converter 49, each of the control information is separately D/A converted and outputted (separately outputted for each infinite phase shifter).

The first infinite phase shifter (EPS1) 34 receives the received signal from the first antenna (ANT1) 31 and performs phase adjustment using the control signal described above. Further, the second infinite phase shifter (EPS2) 35 is connected to the second antenna (ANT2).
) 32 received signals are input, and the phase is adjusted using the control signal described above.

Furthermore, a third infinite phase shifter (EPS3) 36
inputs the received signal of the third antenna (ANT3) 33 and performs phase adjustment using the control signal described above. In this way, each received signal of the three-sided antenna is phase-adjusted by a separate infinite phase shifter, and the output signal is input to the in-phase synthesis hybrid circuit 40, and the in-phase synthesized intermediate frequency output (IF OUT ).

Further, between each of the infinite phase shifters 34 to 36 and the in-phase synthesis hybrid circuit 40, demultiplexing hybrid circuits (H) 37 to 39 are provided corresponding to each antenna. , the output of this circuit is phase detection and
The signal is input to AGC circuits (PH DETAGC) 41 to 43, where phase detection processing and AGC (automatic gain control) are performed.

The phase data detected by the phase detection process is sent to a phase difference detection circuit 45, where a phase difference detection process between each antenna is performed. Further, the signal after the AGC processing is sent to an incoming signal level monitor circuit 44, where the incoming signal level of each antenna is monitored.

The incoming call level information output from the incoming call level monitor circuit 44 and the phase difference detection information output from the phase difference detection circuit 45 are sent to the EPS control unit 46, where each infinite phase shifter 34 to 36 is created, and the phases are controlled so that the phases of the received signals from the three antennas are in the same phase.

Next, the incoming call level monitor circuit 44 will be explained in detail with reference to FIG.

The incoming call level monitor circuit 44 includes a comparison section 55 consisting of comparators A, B, and C that compare levels between the respective antennas, and a signal conversion section 56.

Input signals from each phase detection/AGC circuit 41 to 43 (these are input to "ANT1, AGCV", "ANT2")
, AGCV" and "ANT3, AGCV") are compared by the comparing section 55. That is, the incoming signal level of each antenna is compared by comparators A, B, and C,
Detect which antenna has the highest incoming signal level. This incoming call level comparison process is as shown in Table 1 below.

[0049]

[Table 1]

[0050] That is, in comparator A, "ANT
1, AGCV” and “ANT2, AGCV”,
If "ANT1, AGCV" is high, the output of comparator A is set to high level "H", and "ANT2, AGCV"
is high, the output of comparator A is set to low level “L”.
”.

Similar comparison processing is also performed for comparators B and C, and the outputs of each comparator shown in Table 1 are produced.

The output signal of the comparator 55 is converted to a signal converter 56.
The signal is input into the 2-bit digital signal, and is converted into a 2-bit digital signal and output. The signal converter 56 includes an inverter INV.
1 to INV3, AND gates AND1, AND2, and OR gates OR1, OR2 are provided, and the signal conversion processing shown in Table 2 below is performed by the logic processing of these parts.

[0053]

[Table 2]

In Table 2, "L" is a low level, "
"H" is a high level, "X" is an undetermined value, "LEV・MON"
1" and "LEV・MON2" are output signals (2 bits) of the signal converter 56.

For example, when the outputs of comparators A, B, and C are "L", "L", and "X", the output signals are "H" and "X".
H", and the reference antenna (the antenna with the highest incoming call level) is the second antenna (ANT2).

Similarly, when the outputs of comparators A, B, and C are "L", "H", and "X", the output signal is "H".
, "L", and the reference antenna becomes the third antenna (ANT3). Also, comparators A, B, C
When the output is “H”, “L”, or “X”, the output signal is “L”.
”, “H”.

In this way, the incoming call level is monitored and the 2-bit digital output signal (“LEV, MON
1”, “LEV, MON2”) are sent to the EPS control unit 46.

The phase difference detection circuit 45 is configured as shown in FIG. 4, for example. As shown in the figure, the phase difference detection circuit 45 of this embodiment includes a phase detection section 57 and a comparison section 58.

The phase detection section 57 includes three mixers Mix1
, Mix2, and Mix3, and the comparing section 58 is composed of three window comparators WC1, WC2, and WC3.

The phase detection section 57 detects the phase difference between the respective antennas, and the comparison section 58 creates phase detection information from the output signal of the phase detection section 57, and the EPS control section 4
Output to 6.

In the mixer Mix1, the first antenna 31
The mixer Mix2 compares the phase of the received signal by the first antenna 31 and the phase of the received signal by the second antenna 32.
3 is compared with the phase of the received signal.

Further, mixer Mix3 compares the phase of the signal received by the second antenna 32 and the phase of the signal received by the third antenna 33.

Each of these mixers Mix1, Mix2, Mi
The output signals of x3 are each sent to a window comparator W
It is sent to C1, WC2, and WC3, where comparison processing is performed.

Each window comparator WC1 to WC3
In each case, an output signal is output depending on whether the level of the input signal is within a certain range or outside the range.

The phase detection information that is this output signal is a 2-bit output signal for each window comparator WC1 to WC3. For example, if the comparison value is within a certain range (in phase), low level "L" and "L" are output, and when it is outside that range, one of them is high level "H" and the other is low level "L". L”.

This phase detection information is output to the EPS control section 46 and processed by the microcomputer 47.

Based on the processing flowchart of FIG. 5 below,
The processing of the EPS control unit will be explained. Note that each process number in FIG. 5 is shown in parentheses.

First, the incoming call level information from the incoming call level monitor circuit 44 and the phase detection information from the phase difference detection circuit 45 are input to the EPS control section 46 (S1).

Next, the microcomputer 47 determines a reference antenna using the input incoming call level information (S2). This reference antenna is the antenna with the highest incoming signal level.

For example, if the reference antenna is the first antenna 3
1, the data in the phase control register 51 (the register corresponding to the first antenna) is left as is, and the data in the phase control register 52 (the register corresponding to the second antenna) and the phase control register 53 (the register corresponding to the second antenna) are The data in the register corresponding to antenna No. 3 is increased by ±1 based on the phase detection information (S3).

If the reference antenna is determined to be the second antenna, the data in the phase control register 52 is left as is, and the data in the phase control registers 51 and 53 are increased by ±1 based on the phase detection information (S4). .

Furthermore, if the third antenna is determined as the reference antenna, the data in the phase control register 53 is left as is, and the data in the phase control registers 51 and 52 are increased by ±1 based on the phase detection information (S5). .

After modifying the data in the phase control register as described above, the control information table in the ROM 50 is accessed using the data in each phase control register 51 to 53 as an address, and the control information for EPS control is accessed. Read out (S6).

The read control information is sent by the microcomputer 47 to the data latch section 48 and latched therein (S7). The latched control information is converted into an analog signal by the D/A converter 49 and output to the first, second, and third infinite phase shifters 34 to 36 (S8).

By repeating each of the above processes and sequentially sending control information to the infinite phase shifters 34 to 36, the phases of the signals received by each antenna are adjusted to be in the same phase.

(Other Embodiments) Although the embodiments have been described below, the present invention can also be practiced as follows. (1) The antenna may have two or three sides, or may have more than two sides.

(2) The data latch section 48 may be provided within the microcomputer 47. (3) The ROM 50 may be provided outside the microcomputer 47.

[0078]

[Effects of the Invention] As explained above, the present invention has the following effects. (1) Since the infinite phase shifter is always controlled using the antenna with the highest incoming signal level as a reference, a free run state will not occur unless the levels of all antennas are cut off.

(2) In-phase combined output (IF
The configuration of the main signal system until obtaining OUT) is the same system for all antennas, so the NF value is the same. Furthermore, the NF value (noise figure) is good due to the circuit configuration.

(3) Compared to the conventional example, the circuit scale is smaller. (4) Since a microcomputer is used for the infinite phase shifter control unit, when the number of carriers increases, if the microcomputer is used in time division, the number of peripheral interfaces will increase, but the infinite phase shifter control unit Gather in one place. Therefore, it is possible to prevent the circuit scale from increasing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a three-sided antenna SD in-phase combining circuit in an embodiment of the present invention.

FIG. 3 is a configuration diagram of an incoming call level monitor circuit.

FIG. 4 is a configuration diagram of a phase difference detection circuit.

FIG. 5 is a processing flowchart of an EPS control unit.

FIG. 6 shows a conventional three-sided antenna SD in-phase synthesis circuit.

[Explanation of symbols]

31 First antenna (ANT1) 32 Second antenna (ANT2) 33 Third antenna (ANT3) 34 First infinite phase shifter (EPS1) 35 Second infinite phase shifter (EPS2) 36 Third antenna Infinite phase shifter (E
PS3) 37-39 Hybrid circuit for splitting 40
In-phase synthesis hybrid circuits 41 to 43 Phase detection/AGC circuit (PH DET
AGC) 44 Incoming call level monitor circuit 45 Phase difference detection circuit 46 Infinite phase shifter control section (EPS control section) 47 Microcomputer 48 Data latch section

Claims (2)

[Claims] 1. In a space diversity in-phase combining method that combines received signals from a plurality of antennas (31 to 34) in phase, infinite phase shifters (34 to 34) adjust the phase of received signals from the antennas for each antenna. 36),
Each antenna (31 to 34) is provided correspondingly, and the antenna with the highest incoming call level is always used as a reference.
A space diversity in-phase combining method that is characterized by controlling infinite phase shifters corresponding to other antennas to bring the received signals from each antenna into the same phase, and simultaneously combining all the in-phase received signals. . 2. An infinite phase shifter control section (46) for controlling the infinite phase shifters (34 to 36), and a microcomputer installed in the infinite phase shifter control section (46). (47) is provided, and the microcomputer (47) is provided.
), each of the infinite phase shifters (3
2. The space diversity in-phase combining system according to claim 1, wherein a control signal for controlling the phase shifters (4 to 36) is generated and output to each of the infinite phase shifters (34 to 36).