JPH04356884A - Digital video signal processor - Google Patents

Abstract

PURPOSE:To facilitate error correction in a video signal and error adjustment by preparing a field memory and a sub memory at a vertical part and storing data for error correction in the sub memory. CONSTITUTION:A judgement signal CRCTV and a vertical error flag SFLG are supplied to an error correction circuit 40 of a vertical part 28. A field memory 34 and a sub memory 35 are provided, and the data for error correction are stored in the memory 35. When a signal is '0' and a flag is '1', the correction of a sub block is disabled and a sub block is made erroneous. Therefore, for the sub block to appear in a data sequence DTF from the memory 34, the error is corrected by data contained in a line spatially lower than the field by one line. When the signal and the flag are '1', the sub block enables the correction and the error is corrected. Thus, the error correction and adjustment in the video signal can be easily executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing apparatus applied to correct errors in received (or reproduced) digital video signals.

0002

2. Description of the Related Art For example, when digital video signals are recorded and reproduced using a rotating head type VTR, random errors due to head noise, tape noise, or amplifier noise, or burst errors due to dropouts occur. Even if the code structure of a digital video signal is capable of error correction, errors may sometimes exceed the correction ability. In such cases where correction is impossible, error correction is required to make the error less noticeable on the screen.

One of the error correction methods that has already been proposed is to use the strong correlation in the vertical direction of television images to replace the data with data from one line before (interpolation) when the error cannot be corrected. ) There are things. Further, as another error correction method, there is a method in which an average value of two data located before and after the uncorrectable data is formed and the data is replaced with this average value.

All of these error correction methods obtain signals for interpolation from data within the same field. By the way, since television images are drawn using interlaced scanning, adjacent lines within the same field are spatially shifted by a distance of two lines. On the other hand, adjacent lines in the previous field are spatially separated by only one line, and can be said to have a stronger correlation.

[0005]

OBJECTS OF THE INVENTION An object of the present invention is to provide a digital video signal processing device that can make errors in an image less noticeable by interpolating uncorrectable data with data spatially one line below the previous field. Our goal is to provide the following. Another object of the present invention is to realize an apparatus that does not particularly require a one-line delay circuit or an average value forming circuit to obtain data for interpolation. Further, according to the present invention, the field memory can be used effectively by combining the field memory required for obtaining the data of the previous field and the field memory for error correction.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing an embodiment of the present invention, a method will be described in which data of a previous field spatially located one line below is used to interpolate one uncorrectable line.

When NTSC color video signals are digitized, the following points are guaranteed.

[0008] Since one 1° frame has 525 lines, the first (third) field...262 lines, the second (fourth) field...
) Field: 263 lines. In the first field, the phase of the vertical synchronization pulse and the horizontal synchronization pulse match, and in the second field, the phase of the two is shifted.
field. 2° 1 horizontal section (hereinafter abbreviated as 1H)
The number of sample pixels varies depending on the sampling frequency (fS). In other words, since the color subcarrier frequency (fSC) is 455/2 times the horizontal frequency (fh), (fS = 3
Table 1 below shows the case of fSC) and the case of (fS = 4fSC).

[0009]

[Table 1]

Assume that the number of samples of a line in which the horizontal synchronization pulse and the color subcarrier are in phase is 682, and the number of samples in a line in which the phase is shifted is 683. In odd-numbered frames, the line starts from a line where these two phases are out of alignment, and in an even-numbered frame, it starts from a line where these two lines match. As can be seen from Table 1, in the case of (fS = 3fSC), the number of sample pixels of adjacent lines temporally 1H apart within the same field is different, but the line of the previous field located spatially 1H below. If the information is an interpolation line, the number of sample picture elements for the error line and the interpolation line will be the same. Furthermore, as will be clear from the description below, the phases of the color subcarriers of each sample picture element in both lines are also equal.

Unlike the actual number of lines and the number of sample picture elements shown in Table 1, FIGS. 1 and 2 show each number as a smaller number in order to clarify the number of picture elements and the phase relationship. . FIG. 1 relates to the case (fS = 3fSC), and FIG. 2 relates to the case (fS = 4fSC). In the NTSC color television system, the phase of the color subcarrier is reversed between one line and the next line within one field, and the phase of the color subcarrier is also reversed between frames. Furthermore, since the sampling points are at a predetermined phase with respect to the color subcarrier, the difference in phase (phase difference π) of the color subcarrier at the sampling point of the line is shown by a black circle and a white circle. Furthermore, the lines of the first field are shown as solid lines, and the lines of the second field are shown as dashed lines.

First, in the case (fS = 3fSC), the odd frame, for example the first frame, is as shown in A of FIG. In the first field of the first frame, l
(1-0), l(1-1)...l(1-7) are drawn in sequence, and in the second field, l(1
-8), l(1-9)...l(1-16) are drawn sequentially, and there are a total of 17 lines in one frame. In the first line l(1-0), for example, the number of sample picture elements is 5, and in the next line l(1-1
), the sample period is 1/1 for line l(1-0).
There are 4 sample picture elements at positions with a shift of 2,
Furthermore, in the next line l(1-2), there are five sample picture elements as in line l(1-0). This relationship is repeated hereafter.

[0013] Following the second field of the first frame, an even frame, for example, the first field of the second frame,
As shown in B of Figure 1, l(2-0), l(2-1)...
Eight lines of l(2-7) are drawn in sequence, and in the second field, l(2-8), l(2-9)...
Nine lines of l(2-16) are drawn sequentially, and there are a total of 17 lines in one frame. Since the number of lines is odd, the phase relationship between the number of sample picture elements and the color subcarrier is opposite to that of the first frame. In other words, between lines at the same position in the first and second frames, if the number of sample pixels on one line is 5, the number of sample pixels on the other line is 4, and the phases of the color subcarriers differ by π from each other. . Then, a certain line and a line in the previous field located 1H spatially below it are the same in terms of the number of sample picture elements and the phase of the color subcarrier. For example, if l(1-10) of the second field of the first frame is an error line, line l(1-2) of the previous field spatially located below 1H of l(1-10) becomes the interpolation line. Both have five sample picture elements and a phase difference with the color subcarrier of zero. In other cases as well, as is clear from FIG. 1, the number of sample picture elements and the phase difference between the color subcarriers of the error line and the interpolation line are equal. l(1-10
) to l(2-16) as error lines, Table 2 shows the corresponding interpolation lines. However, for the sake of simplicity, the lines of the field before the first field of the first frame are also indicated by the line numbers of the second frame, and l is omitted and only each number is indicated.

[0014]

[Table 2]

In addition, in the case of (fS = 4fSC), the correspondence between the error line and the interpolation line is as follows from A in FIG. 2 (indicating the first frame) and B in FIG. 2 (indicating the second frame). As is clear, if l(1-10) is an error line, then l(1-2) is an interpolation line. In the case of (fS = 4fSC), the number of sample picture elements for all lines is equal to 5. l(1-0) to l(2
-16) as the error line, the corresponding interpolation lines are exactly the same as those shown in Table 2, and the phase relationships of the color subcarriers of both the error line and the interpolation line are equal.

As is clear from the above description, the error section of the digitized color video signal can be filled with the same number of sample picture elements and information on the phase relationship as the original. However, the sampling frequency (fS) is (fS
There is an advantage that correction can be performed in either case (fS = 3fSC) or (fS = 4fSC).

[0017] The above-mentioned interpolation method can be realized using a RAM (random access memory) having a capacity equal to or more than one field. For example, as shown in each of A to I in FIG. 3, a RAM having physical line addresses from 1 to 9 is used. However, from B onwards in FIG. 3, illustration of the physical line addresses from addresses 1 to 9 of the RAM is omitted for the sake of simplicity.

First, in the first field of the first frame, data of each line of this field is sequentially written into addresses 1 to 8 of the RAM. A in FIG. 3 shows the state in which writing of the first field data is completed using logical data line addresses. Next, the data of the 8th line [1-8] of the second field is written to 0 of the first field of the same frame, as shown in FIG. 3B.
The data of the th line [1-0] is stored at the address (first promise regarding writing). Furthermore, prior to this writing, data is read from the same location. That is, the first half of one memory cycle of the RAM is a read cycle, and the second half is a write cycle. The data of each line of this second field is sequentially written to the RAM, and the last line of the first frame [1-1
6] is written to address 9 as shown in FIG. 3C. As mentioned above, in principle, reading is performed to the same address as writing, but when the last line of data in a frame is written, the data at the address next to the writing address is read. be done.

As shown in FIG. 3D when writing of the data of the first frame is completed, the data of the 0th line [2-0] of the first field of the next frame is the same as that of the second field of the previous frame. The eighth line [1-8] of the address is shifted one place later than the stored address and written (second promise regarding writing). Under the above-mentioned promises regarding writing and reading, the operations proceed as shown in E and F of FIG. 3, and writing of data of all lines of the second frame is completed in the state of F of FIG. 3.

[0020] Again, the 0th line [3-
0] is written in accordance with the second promise, as shown in G in Figure 3, and the data in the 8th line [3-8] is written in accordance with the first promise, as shown in H in Figure 3. Therefore, the data is written, and writing of data of all lines of the third frame is completed as shown in FIG. Here, A in Figure 3, D in Figure 3,
As can be understood by comparing the three figures in G in the same figure, or the three figures in B, E, and H in Figure 3, the data in the first line of each field advances by one address each time one frame passes. It becomes something. In other words, the RAM operates in a circular manner. If such an operation is performed, R
The capacity of AM may be one field or more.

Data such as reproduced output from the VTR is supplied to the RAM via an error correction circuit. If the data is incorrect and the error is uncorrectable, a flag signal indicating this is generated from the error correction circuit. One line of data including data generated by this flag signal is prohibited from being written to the RAM. When the RAM is operated as described above, the line of the previous field spatially 1H below can be read out as interpolated data only by this write prohibition.

For example, if a flag signal is generated because the data on line [2-1] is erroneous and cannot be corrected, in the next memory cycle shown in D in FIG. ] data is prohibited from being written to RAM. Therefore, the data for this address is
This is the data of line [1-10] written previously. As shown in FIG. 3E, in the next memory cycle in which data on line [2-0] is read, line [2-0] is
Instead of the data on line [1], the data on line [1-10] will be read out. That is, with respect to each incorrect and uncorrectable line l(2-1), the line l(1-10) of the previous field spatially 1H below becomes an interpolation line, which is consistent with the above explanation.

Note that if the number of lines is the same between fields, it is only necessary to shift the writing of the data of the first line for each frame.

An embodiment in which the present invention is applied to a digital VTR will be described below. FIG. 4 shows the configuration of a recording system of a digital VTR, and FIG. 5 shows the configuration of its reproduction system. Digital video signals are recorded as diagonal tracks on magnetic tape by a rotating head. Since the transmission bit rate of digital video signals is high, two rotary heads arranged close to each other are provided, and one field's worth of digital video signals is distributed to two channels, each of which has two parallel channels.
recorded as a track. The audio signal is also converted to a PCM signal and recorded by a rotating head as one track parallel to the video track.

An NTSC color video signal to be recorded is supplied to an input terminal indicated by 1, and is then supplied to an input processor 2. The input processor 2 is provided with a clamp circuit, a synchronization and burst separation circuit, etc., and the color video signal of the effective video area is supplied to the A/D conversion circuit 3.
The separated synchronization signal and burst signal are supplied to a master clock generator 4 having a PLL configuration. A clock pulse of (3fSC) is generated from the master clock generator 4. This clock pulse and synchronization signal are supplied to the control signal generator 5. The control signal generator 5 generates control signals such as various timing pulses, identification signals for each line, field, frame, and track, and sampling pulses.

The A/D conversion circuit 3 includes a sample hold circuit and an A/D converter that converts the sample output into an 8-bit code, and a parallel 8-bit output is supplied to the interface 6. Here, the length of 1H of the color video signal is 63.5 [μs], of which the blanking period is 11.1 [μs], so the effective video area is 52.4 [μs]. Become. Also,

00
27]

[Math 1]

Therefore, the number of samples in the 1H interval is 682.5. Furthermore, the number of effective video samples is (52.
4 [μs]/Ts = 562.7 samples) (However, Ts
represents the sampling period, 0.0931217 [μ
s]. ). Considering that it will be divided into 2 channels, it will be 576 samples, and 288 samples per channel.
Assign samples. As shown in Figure 6, the 2H section (1
365 samples) as a unit, and the horizontal synchronization pulse H
The number of samples of a line in which the phases of D and the color recovery carrier are in agreement is 682, and the number of samples in a line in which the phases of the two are out of alignment is 683.

[0029] Furthermore, the number of lines in one field is 262.
．． 5H, of which the vertical synchronization period and equalization pulse period are 10.5H. Since test signals such as VIT and VIR are inserted into the vertical retrace interval, these are also considered valid video signals. As a result, the number of effective video lines in one field period is set to 252.

As described above, the digitized color video signal (effective video area) is distributed to two channels at the interface 6. Among the 576 samples of one line, data corresponding to odd-numbered samples is set to one channel, and data corresponding to even-numbered samples is set to the other channel. The processing for data in these two channels is the same. Further, the external digital video signal Din is supplied to the interface 6 and converted into two channels. The data of one channel is outputted to the output terminal 11A as a recording signal through the time axis compression circuit 7, the error control encoder 8, the recording processor 9, and the recording amplifier 10 in sequence. The data of the other channel is also processed using the same configuration, and the recording signal of the other channel is sent to the output terminal 1.
It is taken out to 1B. Two rotary heads provided close to each other are connected to the output terminals 11A and 11B via a rotary transformer. When the two rotating heads are an A head and a B head, a recording signal appearing at the output terminal 11A is recorded as an A track by the A head, and a recording signal appearing at the output terminal 11B is recorded as a B track by the B head.

FIG. 7 shows one sub-block of the code array of the recording signal taken out to each of the output terminals 11A and 11B. 1 subblock is 3 samples (24 bits)
block synchronization signal (SYNC), 2 samples (16
bit) identification (ID) and address (AD) signals, 9
6 samples (768 bits) of data, 4 samples (32 bits) of CRC (Cyclic Redundant)
ancyCheck) codes arranged in sequence, totaling 105
It is configured for samples (840 bits). Since one line of data is 288 samples per channel, this is divided into three to form one sub-block of data. The block synchronization signal is used for data processing of one sub-block, and by detecting the block synchronization signal, identification and address signals, data, CRC codes, etc. are extracted. The identification and address signals indicate the channel (track), frame, field, and line to which the data of the subblock belongs, and also indicate the address of the subblock. The CRC code is for detecting data errors.

FIG. 8 shows the code structure for one field regarding one channel. In the same figure, SBi(i
= 1 to 858) represents 1 subblock, and 3
One block is composed of sub-blocks. As mentioned above, the effective video area for one field is 25
Since it is 2H, there are 252 blocks of data in one field. The data in a certain field is arranged in a (21×12) matrix format starting from the first one, sequentially arranged in the first row, second row, third row, and so on. Parity data is formed for this video information data in both the horizontal and vertical directions. The horizontal parity data of the 13th block column in FIG. 8 is arranged, and the vertical parity data is arranged in the 22nd row at the bottom. The 13th column of this 22nd row is the horizontal parity data for the vertical parity data. Horizontal parity data is formed in three ways by 12 subblocks extracted from each of the 12 blocks constituting one row. Taking the first line as an example,

[0033]

[Math 2]

Parity data [SB37] is formed by the addition of (mod. 2). [SBi] means only the data in sub-block SBi. In this case, one sample belonging to each of the 12 subblocks is computed in 8-bit parallel fashion. similarly

[0035]

[Math 3]

[0036]

[Math 4]

Parity data [SB38] and [SB39] are formed by [SB38] and [SB39]. Horizontal parity data is similarly formed for each of the other 2nd to 22nd rows. In this way, one parity data is not simply formed from the data of 36 sub-blocks included in one row, but from the data of a total of 12 sub-blocks located at an interval of two sub-blocks. The purpose of forming one piece of parity data is to improve error correction ability.

[0038] The parity data in the vertical direction is 2 in each column from the 1st block column to the 12th block column.
It is formed from data of one sub-block. Taking the first column as an example,

[0039]

[Math 5]

parity data [SB820]
is formed. In this case, one sample belonging to each of the 21 sub-blocks is computed in 8-bit parallel fashion.

[0041] Therefore, like the video data, these parity data also have 96 samples and have a code arrangement as shown in FIG. The digital signal for one field in the above (22×13) matrix arrangement is shown in the first row.
When transmitting as one series in the order of 2nd row, 3rd row, etc., 22nd row, 13 blocks corresponds to the length of 12H, so to transmit one field's worth of digital signals, (
A period of 12×22=264H) is required.

By the way, the VTR in this example uses an auxiliary head to record or reproduce part of the vertical blanking period in one field, and when only the video head is used without using this auxiliary head, approximately 2
Only an area of 50H can be recorded. Furthermore, the number H
Considering the margin, an area of 246H in one track is set as a recordable area. In other words, as mentioned above, the time axis is compressed from 264H to 246H (compression ratio Rt is 41/44
). Further, a preamble signal and a postamble signal of the transmission bit frequency are inserted at the beginning and end of the recording signal for one field having a length of 246H.

The time axis compression circuit 7 in FIG. 4 compresses the video data with the above-mentioned compression rate, and also inserts a block synchronization signal, an identification and address signal, and a CRC code into every 96 samples of video data. A data missing period is formed in which a block of parity data is inserted. Horizontal and vertical parity data and a CRC code for each sub-block are generated by an error control encoder 8. block synchronization signal,
Identification and address signals are added in the recording processor 9. The address signal is the sub-block number (
i). The recording processor 9 also includes 1
A block coding encoder that converts the number of sample bits from 8 bits to 10 bits and a converter that serializes the 10 bit parallel code are provided. Block coding consists of 10 bits (210)
The DC level is close to zero among the street codes (28)
This code is made to have a one-to-one correspondence with the original 8-bit code, and therefore the DC level of the recording signal is made to be as low as possible. In other words, a signal form in which "0" and "1" appear alternately as much as possible. It is converted into . Block coding is used for the purpose of facilitating synchronization extraction on the playback side and preventing deterioration of the transmitted waveform. For the same purpose, instead of block coding, scrambling using M sequences, coding that takes into account the probability of occurrence of quantization levels, etc. may be used. The transmission bit rate per channel in the case of 8 bits is

[0044]

[Math 6]

, and the recording bit rate after converting to 10 bits is

[0046]

[Math 7]

[0047]

[0048] Each of the A head and B head corresponds to the A
The two-channel playback signal obtained by scanning the track and B track is the playback signal input terminal 12A, 12B.
and is supplied to the waveform shaping circuit 14 via the reproducing amplifier 13. The waveform shaping circuit 14 includes a reproduction equalizer that enhances the high-frequency components of the reproduction signal, and also converts the reproduction signal into a pulse signal, extracts a reproduction bit clock synchronized with the preamble signal, and sends it to the next stage reproduction processor 15. This reproduced bit clock is supplied along with the data. In the reproduction processor 15, the data series is serial-parallel converted, a block synchronization signal is extracted, the data is separated from other block synchronization signals, etc., and further block decoding (10→8 bit conversion) is performed. This data is supplied to the time base collector 16,
Data is obtained from which time axis fluctuations have been removed. The time base collector 16 is equipped with, for example, four memories, in which reproduced data is sequentially written using a clock pulse synchronized with the reproduced data, and data is sequentially read from the memory where writing has been completed using a reference clock pulse. If reading is about to overtake writing, reading is performed again from the memory from which the data was currently read.

Data regarding each channel of time base collector 16 is supplied via interchanger 17 to error correction decoder 18 . Two rotary heads are used for normal playback operation in which the recording track of the magnetic tape matches the scanning locus of the rotary head, or during slow or still playback when the position of the rotary head is controlled so that the two match. A reproduced signal is extracted only from the track to be reproduced and supplied to each of the input terminals 12A and 12B. However, during high-speed playback operations in which the running speed of the magnetic tape is several tens of times faster than the normal speed, the rotary head must scan across multiple recording tracks, and the input terminal 1
2A and 12B are supplied with a reproduction signal in which signals from both the A track and the B track are mixed. In such a case, channel identification is performed in the interchanger 17 using a track identification signal, and the channels are divided into the original channels.

An error correction decoder 18 is connected to the interchanger 17. Error correction decoder 18
This includes a CRC checker, horizontal parity and vertical parity error detection and correction circuits, field memory, and the like. During the aforementioned high-speed playback operation,
Field memory is used to serialize the data of each channel that is played back intermittently without error detection or correction. The data from the error correction decoder 18 is returned to the original transmission rate by the time base expansion circuit 19 and is supplied to the interface 20. The reproduced data of the two channels is returned to one channel by the interface 20, and is supplied to the D/A conversion circuit 21, where it is converted into an analog video signal. A digital video output Dout is taken out from the interface 20. Since the recording system and the playback system are each provided with a digital video input terminal and a digital video output terminal, editing and dubbing can be performed in the form of digital signals.

The output of the D/A conversion circuit 21 is supplied to the output processor 22, and a reproduced color video signal can be obtained at the output terminal 23. Also, the external reference signal is input to input terminal 2.
4 is supplied to a master clock generator 25, and the clock pulses and reference synchronization signals generated therefrom are supplied to a control signal generator 26. The control signal generator 26 generates control signals such as various timing pulses, identification signals for each line, field, and frame, and sampling pulses in synchronization with an external reference signal. Processing from the input terminals 12A, 12B of the reproduction system to the writing side of the time base collector 16 uses the clock pulse extracted from the reproduction data as the time base, and processing from the reading side of the time base collector 16 to the output terminal 23 is as follows. The clock pulse from the master clock generator 25 is used as the time base.

Error correction decoder 18 to which the present invention is applied
Prior to the explanation, the encoding code operation in the error control encoder 8 will be explained with reference to FIG. WDST shown in A of FIG. 9 is a timing pulse indicating the start of a data section in one field, and DWi shown in B of FIG.
is an 8-bit parallel data series supplied from the time axis compression circuit 7. There are a total of 756 subblocks as valid data in one field, and a time slot in which a CRC code is inserted after each subblock,
The data series DWi has time slots into which horizontal parity data for each of 36 subblocks is inserted. The length of one horizontal row period for 39 blocks, which is the sum of 36 subblocks and the time slot into which horizontal parity data is inserted, is 12RtH{12×(4
1/44)×H}. C in FIG. 9 shows a high level (“1
”) timing pulses HPT, VPT, CRCT
It shows.

The data series DWi is supplied to the vertical parity generation circuit, and the data series [SB820] to [S
36 vertical parity data of B855] are added to the delayed data series DWi by the timing pulse VPT. Next, the data series DWi including vertical parity data is supplied to the horizontal parity generation circuit to form three horizontal parity data for one horizontal row of data series, and the timing pulse HPT converts this horizontal parity data into the data series DWi. will be added. and CR within the period defined by the timing pulse CRCT.
A C code is added, and a data series DWo as shown in D in FIG. 9 is obtained. Note that at the beginning of each sub-block of the data series DWi from the time axis compression circuit and the data series DWo from the error control encoder 8, a time slot is provided to which a block synchronization signal and an identification and address signal are added. This is as stated above. In this way, 262H (or 263H) of one field period
Of these, 246H is the data period, and 16H (or 1
After the data blank (7H), the data of the next field begins.

The arrangement of the data series DRi reproduced from the magnetic tape and given to the error correction decoder 18 is also shown in D in FIG.
It will be similar to. FIG. 10 shows an example of an error correction decoder to which the present invention is applied. The error correction decoder is mainly composed of a horizontal section 27 that performs error detection and correction using a CRC code and horizontal parity data, and a vertical section 28 that performs error correction using a CRC code and vertical parity data, as shown surrounded by a broken line. There is.

The waveform shaping circuit 1 is reproduced from the magnetic tape.
4. Playback processor 15 and time base collector 16
The 8-bit parallel data series DRi is first supplied to the horizontal section 27. 11A shows a timing pulse RDST that defines the first timing of one field's worth of data, and FIG. 11B shows a data series DRi. This data series DRi starts from the first horizontal row period TH0 of the field and starts from the 22nd horizontal row period TH0.
21 are included in one field. Error detection is performed for each subblock by the CRC checker 29 in the horizontal section 27, and when it is detected as containing an error, it is set to "1".
, and the error signal ER becomes “0” when this is not the case.
R is generated from the CRC checker 29. It is checked whether all bits of the corresponding sub-block are erroneous, and if even one bit is erroneous, the period of the sub-block following this sub-block is held at "1". C in FIG. 11 shows an example of the error signal ERR. This error signal ERR is supplied to the horizontal determination circuit 30. The horizontal determination circuit 30 delays the error signal ERR by a period corresponding to 38 blocks and sets the error flag ER as shown in D in FIG.
In addition to forming the FLG, it is also necessary to check whether error correction is possible for each subblock (“1” =
Judgment signal CRCT indicating correctable (“0” = uncorrectable)
Generates H.

In this determination, if there are two or more errors in the subblock group for which horizontal parity is determined every two subblocks, it is determined that the error cannot be corrected, and if there is one or less, it is determined that the error is correctable.

The data series DRi is also supplied to the horizontal parity checker 31, from which a horizontal syndrome series SDH is generated. The horizontal syndrome is calculated in one horizontal row period (12RtH) and held so that it is used for error correction in the next one horizontal row period. In other words, the horizontal parity checker 31 includes two parts that alternately calculate the horizontal syndrome and hold the horizontal syndrome after calculating it. In F of FIG. 11, the horizontal syndrome for the horizontal period THi data is expressed as SD
It is expressed as Hi. This horizontal syndrome SDH
i indicates that the same content is repeated at a cycle of three block periods.

Furthermore, the data series DRi is delayed by one horizontal period by the buffer memory 32 and is supplied to the horizontal error correction circuit 33. In the error correction circuit 33, correction is performed using the horizontal seed rom SDHi for (CRCTH="1"), that is, correctable sub-blocks among the sub-blocks containing errors (ERFLG="1"). The error flag ERELG regarding the sub-block that has undergone this correction is set to "0". The signal processed in this way is the error block signal ER shown in G in FIG.
For example, [SB2] [SB75] [SB780] [
Each of SB819 ] and [SB858 ] includes an error that cannot be corrected depending on the horizontal parity.

A field memory 34 in which the data series from the error correction circuit 33 of the horizontal section 27 constitutes the vertical section 28
and is input data to the submemory 35 and is also supplied to the vertical parity checker 36. In addition, the horizontal part 2
The error block signal ERBLK generated in step 7 is supplied to a vertical determination circuit 37, a field memory control circuit 38, and a sub-memory control circuit 39. In this case, a total of 66 sub-blocks consisting of horizontal parity data will not be used after error correction in the row direction, so in order to save the capacity of the field memory 34 and sub-memory 35, these memories are cannot be saved. This also applies to subblocks consisting of 36 pieces of vertical parity data. Therefore, field memory 3
4 has a capacity of 756 subblocks, and PCM data is sequentially written using the address signal of each subblock.

PCM for this field memory 34
Data is written by shifting the first sub-block in each frame by three sub-block addresses corresponding to one line. It is written to the same address as the subblock included in the line located below the line. In this case, the sub-block that could not be corrected in the horizontal section 27 by the memory control circuit 38 (the sub-block for which the error block signal ERBLK is "1")
Writing to the field memory 34 is prohibited. Since there is a possibility that this write-inhibited sub-block can be corrected by vertical parity, the memory control circuit 39 monitors the error block signal ERBLK,
This writes a subblock of “1” to the submemory 35. If only this were done, the sub-memory 35 would overflow when errors occur frequently, and on the other hand, if the overflow was prevented, the capacity of the sub-memory 35 would become significantly large.

Therefore, the detection signal CRCTBL generated from the vertical determination circuit 37 is supplied to the memory control circuit 39. Similarly to the horizontal determination circuit 30, the vertical determination circuit 37 is capable of error correction using vertical parity for every subblock (="1"), that is, when there is one or less error block in one vertical column. , generates a determination signal CRCTV (I in FIG. 11) indicating whether it is impossible (="0"), that is, when there are two or more error blocks in one vertical column. In this case, during the period in which the data of the i-th field is being supplied from the horizontal section 27 to the vertical section 28, the determination signal CRCTVi-1 regarding the previous (i-1)th field appears. At the same time, it is detected whether or not the sub-block in which the error block signal ERBLK of the current i-th field is "1" can be corrected by vertical parity. In other words, in Figure 8, 3
Of the 22 sub-blocks included in each of the 6 columns, 2 sub-blocks have an error block signal ERBLK of "1".
If the detection signal CR
CTBL is changed from "1" to "0". Therefore ERB
Only error subblocks in which both LK and CRCTBL are "1" are stored in the submemory 35. At the same time, the address of the subblock written in the submemory 35 is stored as a vertical error flag SFLG. When the i-th field is written as described above, the sub-block and error flag SFLG are stored in order to correct the error in the previous (i-1)-th field by the error correction circuit 40. Because it is necessary to read out
Sub-memory 35 and memory control circuit 39 include two parts, each writing and reading a certain field.

[0062] Here, the required capacity of the sub-memory 35 will be considered. As described above, one subblock in each channel includes 96 samples in 8-bit parallel fashion, so the total number of bits of one field of PCM data is 580,608 bits. Digital V
If the error rate (probability of bit error) of the TR recording/reproducing system is taken as a parameter and errors are distributed for each bit without duplication in the same block, then 1 of 1 field
The number of error subblocks per channel is as follows.

[0063]

[Table 3]

Assuming that the error rate of the actual recording/reproducing system is about 10-5, it can be said that if there is a capacity of 6 subblocks, it will be enough on average. However, as mentioned above, writing to the submemory 35 is controlled by monitoring the detection signal CRCTBL, so when there is an error in two or more subblocks in each vertical column, only the first error subblock that appears is written. Therefore, overflow of the submemory 35 can be avoided in most cases.

The data of the previous field is read from the field memory 34 or submemory 35 and supplied to the error correction circuit 40. In this case, for the sub-block in which the vertical error flag SFLG is stored, data from the sub-memory 35 takes precedence, and for other
Data from field memory 34 is used, data from submemory 35 and vertical syndrome series SD
The error is corrected by V (H in FIG. 11).

To explain each part of the above-mentioned error correction decoder in more detail, first, the horizontal determination part 30 which is supplied with the color signal ERR from the CRC checker 29 and generates the error flag ERFLG and the determination signal CRCTH will be described in FIGS. 12 and 13. Explain with reference to.

FIG. 12 shows the configuration of one of the two parts that operate alternately every horizontal row period.
The error signal ERR is sent to 38 by the shift register 41.
The error flag ERFLG is formed by being delayed by a period corresponding to a block.

[0068] Also, to determine whether or not error correction using horizontal parity is possible, one horizontal row uses one error correction block code using 12 data sub-blocks every three blocks and one horizontal parity sub-block. This is done by treating one horizontal row equivalently as three independent rows, and detecting how many subblocks contain errors among these three independent rows. It will be done. If there are two or more subblocks containing errors, correction becomes impossible. A D-type flip-flop 42, a counter 43, and a decoder 44 generate gate pulses Y2, Y corresponding to each subblock within one block from a timing pulse HBLKS having a subblock period synchronized with the data series DRi.
1, Y0 (underlined indicates an inverted signal; the same applies hereinafter). A in FIG. 13 shows a timing pulse RDST indicating the beginning of the data section of the data series DRi of each field, and this is the "1" section and D
The D-type flip-flop 42 is cleared, and the timing pulse HBL synchronized by this D-type flip-flop 42 is
KA (B in FIG. 13) is supplied as a load pulse to the counter 43. From this point on, the counter 43 counts the timing pulse HBLKS and repeats loading by its own output, and the output of the counter 43 is sent to the decoder 44.
The three-phase gate pulses Y2, Y1, and Y0 shown in FIG. 13C are generated. Gate pulse Y2 has a period of “0” corresponding to the first sub-block of each block, gate pulse Y1 has a period of “0” corresponding to the next sub-block, and gate pulse Y0 has a period of “0” corresponding to the third sub-block of each block. The period corresponding to the th sub-block is “0”.

The data series DRi shown in FIG. 13D is the first and second horizontal row period TH0 of a certain field.
, TH1 and the beginning part of the third horizontal period TH2. The timing pulse HPC shown in F in FIG. 13 becomes "0" at the end of one horizontal row of this data.
Pulse HPCEN, which is the inversion of EN, and shift register 4
A timing pulse HBLKG (E in FIG. 13) delayed by 5 (using sample clock RCK as a shift pulse) and inverted by an inverter 46 is supplied to an AND gate 47, and the output of this AND gate 47 is supplied to an inverter 4.
D-type flip-flops 49a, 49b, 50a, 50b, 51a every horizontal row period by
, 51b are cleared. Further, the output of the AND gate 47 is used as a clock pulse for the flip-flops 52, 53, 54 provided for the output side of each pair of flip-flops, and at the end of each horizontal period, the flip-flops 49b, 50b, The output of 51b is transferred to flip-flops 52, 53, 54, and immediately after that, the output of flip-flops 49a, 49b, 50a, 50b, 51a,
51b is cleared.

Error signal ER from CRC checker 29
An example of ERR obtained by inverting R by the inverter 55 is shown in G in FIG. This error signal ERR is the NOR gate 5
6, 57, 58, and gate signals Y2, Y1
, Y0. The output pulse EC1 of the NOR gate 56 is used as a clock pulse for the flip-flops 49a and 49b, and the output pulse EC2 of the NOR gate 57 is
is used as the clock pulse for the flip-flops 50a and 50b, and the output pulse EC3 of the NOR gate 58 is used as the clock pulse for the flip-flops 51a and 51b. A level of "1" (+Vcc) is always applied to the inputs of the flip-flops 49a, 50a, and 51a. As shown in G in FIG. 13, [SB1] [SB4] [
The error signal ERR when each sub-block of SB41] [SB42] [SB78] is incorrect is the gate pulse Y.
2, Y1, and Y0 into three equivalent horizontal error pulses EC1, EC2, and EC3 (H in FIG. 13). In this horizontal parallel period TH0,
Since only two error pulses EC1 from the NOR gate 56 are generated, at the end of the period TH0, the output of the flip-flop 49b becomes "1", and the outputs of the other flip-flops 50b and 51b are "0". The output of is stored in the next stage flip-flops 52, 53, and 54. Therefore, the signals held in flip-flops 52, 53, and 54, respectively, are CRCTH1 and CRCTH.
2, CRCTH3, these are I in Fig. 13.
In the next horizontal period TH1, CR
Only CTH1 becomes "1". The outputs of these flip-flops 52, 53, 54 are the NOR gates 59, 60, 61
are supplied with gate pulses Y2, Y1, Y0 (C in FIG. 13), respectively, and are further supplied to the NOR gates 59, 60, 61.
The output of the judgment signal CRCTH (
It is taken out as J) in FIG.

In this way, it is possible to obtain a determination signal CRCTH which becomes "1" for sub-blocks that can be corrected by horizontal parity and becomes "0" for sub-blocks that cannot be corrected.

FIG. 14 shows the configuration of an example of the horizontal parity checker 31. Similar to the horizontal determination circuit 30, the operation of calculating the horizontal syndrome and the operation of holding the horizontal syndrome are performed alternately every horizontal period, and in the same period, the two component parts that perform the above two operations, respectively. A horizontal parity checker 31 is provided. Each part includes adder circuits 64A and 64B (comprised of exclusive OR gates) that add the 8-bit parallel data series DRi and the fed-back 8-bit parallel data series DRi according to the (mod. 2) arithmetic method. , this addition circuit 6
8-bit parallel input RAM65A, 65B with outputs of 4A, 64B as data input, and RAM65A, 65B
A latch circuit 66 to which output data retrieved from the
A and 66B, respectively, and the contents of the latch circuits 66A and 66B are taken out alternately every horizontal row period by a multiplexer 67 to form a horizontal syndrome series SDH.

The RAMs 65A and 65B have a capacity to store data for three sub-blocks (288 samples), and the addresses (0 to 287) can be read by the clock pulse RCK with the sampling period shown in A of FIG. It changes sequentially. As shown in FIG. 15B, data series D
Clear pulse P that becomes “0” for every 3 sub-blocks of Ri
RAM65A, 65B is cleared by SACL. As described above, one sub-block of the data series DRi includes 96 samples of data, a synchronization signal for the previous 5 samples, an address signal, an identification signal, and a CRC code for the subsequent 4 samples. There is. During this data missing period between each sub-block, the supply of the sample clock RCK to the address counter is stopped to prevent the address from incrementing, and the RAM 65A, 65
B is made to repeatedly perform the read operation. Figure 1
5C indicates a change in the address ADR of the RAMs 65A and 65B. In the first horizontal period TH0 of a certain field, the read control signal WE shown in FIG. 15D is first supplied to the RAM 65A, so that the RAM 65A operates in the mode shown in FIG. 15E. In E of FIG. 15, the W (shaded) section is a write cycle, and the R section is a read cycle. This one horizontal period TH0
In this case, the other memory 65B is prevented from being written to by the control signal WE in the "1" state as shown in F in FIG. Furthermore, during this period TH0, the output of the latch circuit 66B is selected by the multiplexer 67, but since this is the first horizontal period of the field, no effective syndrome is obtained. Furthermore, the sample clock RCK is supplied as a latch pulse to the latch circuits 66A and 66B, and the RAM
Read data from 65A and 65B is sequentially captured by this latch pulse. However, the latch circuit 66A,
66B have timing pulses HPEHNA and HP, respectively.
CENB is supplied as a clear pulse (see F in FIG. 13). This timing pulse HPCENA, HPCE
NB is "0" alternately during the first three sub-block periods of each horizontal period THi of the field, and during this "0" period, the latch circuits 66A,
66B is cleared and its 8-bit output DRi
' are all "0". Therefore, the first three sub-blocks of each horizontal row period are written into the RAMs 65A and 65B without being changed even through the adder circuits 64A and 64B.

Here, the first three of the horizontal period TH0
A total of 288 samples of data included in sub-blocks SB1, SB2, SB3 are stored in the RAM 65A as they are.
is written to addresses (0 to 287). Sub block SB
During the data missing period between SB3 and SB4, address 0 remains and no write operation is performed. The next three subblocks SB4, SB5, and SB6 are the data series D
In the section where Ri is sequentially supplied, the address of the RAM 65A similarly changes to addresses (0 to 287). In this case, as is clear from the mode shown in E of FIG. 15, the read cycle for each address precedes the write cycle, and one sample of 8-bit parallel data that was read earlier is taken into the latch circuit 66A. It is fed back as input DRi' to adder circuit 64A. For example, at addresses (0 to 95) of RAM 65A, subblock S
Data of 96 samples of B1 are stored, and in the section where data is read out one sample at a time from each address, each sample of sub-block SB4 is supplied as the input data series DRi. That is, in the adder circuit 64A, the corresponding samples of sub-blocks SB1 and SB4 are added in 8 bits in parallel, and the addition result is R
It is written again to addresses (0 to 95) of AM65A.

By repeating this operation, all sub-blocks SB1 to SB constituting one horizontal row
39 has been supplied, the first
The syndrome SDH0 for the th horizontal row is stored. In other words, addresses (0 to 95) of the RAM 65A contain subblocks SB1, SB4, SB7, SB34, etc.
, SB37 are stored, and the addresses (96-191) contain sub-blocks SB2, SB5, SB8, . . . SB35, S
The result of adding the corresponding samples of B38 is stored, and the addresses (192 to 287) contain subblocks SB3, BS6, SB9, . . . SB36, SB.
The result of adding together the 39 corresponding samples is stored. If all samples of this syndrome SDH0 are "0", it means that the data regarding the first horizontal row is correct, and conversely, the 8
If even one of the bits contains “1”,
Indicates that it contains an error. When only one subblock among the 13 subblocks constituting each of the three error correction block codes mentioned above is incorrect, this erroneous subblock and the erroneous subblock of syndrome SDH0 are matched. It can be corrected by adding (mod.2) to the part where

In the next horizontal period TH1, RAM6
Since the write control signal WE for 5A remains at "1" as shown in FIG. 15D, RAM 65A repeatedly performs only the read operation as shown in FIG. 15E. Along with this, the multiplexer 67
The state will be such that the output of 6A is selected. The syndrome SDH0 read from the RAM 65A is sent to the latch circuit 66.
A is synchronized with the sample clock RCK and taken out as an output via the multiplexer 67 as shown in H in FIG. In this case, the address ADR changes repeatedly through the addresses (0 to 287) in the same manner as described above, as shown in C in FIG. becomes.

On the other hand, in the next horizontal period TH1, FIG.
A write control signal WE shown at F in FIG. 15 is applied to the RAM 65B, and the RAM 65B operates in a mode in which read cycles and write cycles are alternately repeated as shown at G in FIG. Therefore, the syndrome SDH1 for the second horizontal row consisting of sub-blocks SB40 to SB78 is calculated. Although not shown in FIG. 15, the next horizontal period T
Syndrome SDH1 from RAM65B in H2
is read out, and the latch circuit 66B and multiplexer 6
7. By repeating such operations, all syndromes SDH0 to SDH21 relating to each of the 22 horizontal rows of one field are formed.

FIG. 16 shows an example of the configuration of the buffer memory 32 and the horizontal error correction circuit 33. The buffer memory 32 detects error blocks by the CRC checker 29, and while the horizontal parity checker 31 forms the horizontal syndrome sequence SDH, the buffer memory 32 stores the input data sequence DR.
This is to put i on standby.

In the illustrated example, since the cycle time of the RAM is slower than the transmission speed of the input data series DRi,
Samples (32 bits) are processed in parallel. The objects that are delayed in the buffer memory 32 are:
These are the data in each subblock (96 samples) and the previous address and identification signal (2 samples). The total of these is 98 samples, which is not a multiple of 4 samples, so the 2 samples of the CRC code part are also included as a dummy and processed as 100 samples. The first two samples of the input data series DRi are latched by one latch circuit 68A on the input side, and the next two samples are latched by the other latch circuit 68B, so that four samples are converted in parallel. Two samples of latch circuit 68A are written to RAM 69A, and two samples of latch circuit 68B are written to RAM 69B. If one subblock has 100 samples, one horizontal row has 3900 samples.
Samples will be included. RAM69A, 69B
The total capacity is such that data for at least one horizontal row can be stored. Two samples of data are input in parallel to each of the RAMs 69A and 69B, and the address thereof is sequentially changed to addresses (0 to 974) every four samples. For example, when the first and second samples of a certain sub-block are latched into the latch circuit 68A, two samples in the previous horizontal row are read from address 0 of the RAM 69A and latched into one of the latch circuits 70A on the output side. Then, when the next third and fourth samples are latched by the latch circuit 68B, the first and second samples are written to address 0 of the RAM 69A. the other RA
M69B is adapted to perform a read operation during the write cycle of RAM 69A, and conversely to perform a write operation during the read operation. In other words, RAM69A is delayed by two samples of the input data series DRi.
RAM 69B performs the same operation.

The four samples read out alternately from the RAMs 69A and 69B and latched in the latch circuits 70A and 70B are taken out one sample at a time in order to constitute the error correction circuit 33 (mod. 2) addition circuit 71 supplied to The horizontal syndrome series SDH generated by the horizontal parity checker 31 is supplied as the other input of the adder circuit 71. In this case, a delay circuit (shift register) 7 for phase matching between the data series and the syndrome series
2 and a gate circuit 73, the syndrome series is supplied to an adder circuit 71. A timing pulse HBLKE is supplied to the delay circuit 72 as a clear pulse. Timing pulse HBLKE is timing pulse H
It is similar to BLKS (see B in FIG. 13), and prohibits invalid data of the syndrome that occurs during the data missing period between each subblock, converts the syndrome series so that it is all "0" during this period, The identification and address signals included in the data series from the buffer memory are kept unchanged even after passing through the adder circuit 71.

The gate circuit 73 is for adding the corresponding syndrome only to subblocks containing correctable errors. As described above, the gate circuit 73 is controlled based on the determination signal CRCTH generated by the horizontal determination circuit 30 and the error flag ERFLG. The four combinations of "1" and "0" of both signals mean the following states, respectively.

(CRCTH="0", ERFLG="0"
”): Although included in an uncorrectable horizontal row, the sub-block is not in error. Therefore, the gate circuit 73 is off.

(CRCTH="0", ERFLG="1
”): It is included in an uncorrectable horizontal row, and its sub-block is incorrect. Therefore, the gate circuit 73 is off.

(CRCTH="1", ERFLG="0
”): Although included in the correctable horizontal row, the sub-block is not in error. Therefore, the gate circuit 73 is off.

(CRCTH="1", ERFLG="1"
”): Included in a correctable horizontal row, the sub-block is in error. At this time, the gate circuit 73 is turned on, and the error is corrected in the adder circuit 71.

Note that the output of the gate circuit 73 is all "0" when it is off, and when the gate circuit 73 is off,
The data does not change through the addition circuit 71.

Judgment signal CRCTH and error flag ER
FLG is supplied to the AND gate 74, and its output is “1”.
”, the gate circuit 73 is turned on. Also, the judgment signal CRC inverted by the inverter 75
TH and error flag ERFLG are AND gate 76
The error block signal ERBLK is added to the output of the AND gate 76 and becomes "1" for sub-blocks that are erroneous but cannot be corrected due to the horizontal parity.

According to the above horizontal portion 27, A to A in FIG.
It can be easily understood that the error correction operation described above is performed as shown in FIG. Subsequently, each part constituting the vertical part 28 will be explained in detail. First, the vertical parity checker 36 includes a RAM 6 in the horizontal parity checker 31 shown in FIG.
5A and 65B, it can be realized in the same way as a horizontal parity checker. The first to third data excluding horizontal parity data in the code structure of FIG.
Corresponding samples of 22 sub-blocks included in each column up to the 6th column are added in 8-bit parallel (mod, 2
), a vertical syndrome SDVi of (96×36=3456 samples) is formed. For this,
At the timing when a sub-block included in a certain column is supplied to the vertical parity checker 36, this input sub-block and the read data from one horizontal row before are calculated (
mod, 2 addition), and the result of this operation is written at the same location. For example, at the timing when sub-block SB79 is supplied,

[0089]

[Math. 8]

is calculated with input data as read data,

[0091]

[Math. 9]

The calculation result of [0092] is written at the same location. Such read and write operations regarding the same address are performed sequentially for each address for one horizontal row (36 subblocks), and this is performed for each of the 22 horizontal rows. After this is completed, the vertical syndromes from the first column to the 36th column are formed and stored in the RAM of the vertical parity checker. As in the case of the horizontal parity checker 31, the vertical syndrome formed in one field period is held for the next one field period, and two parts are provided in which the forming operation and the holding operation are performed in reverse. ,
The vertical syndromes held alternately are selected and a vertical syndrome series SDV as shown in H in FIG. 11 is created.
is formed.

As shown in FIG. 11, the vertical syndrome series SVD generated from the vertical parity checker 36 is delayed by one field period of the input data series DRi (B in FIG. 11) supplied to the horizontal section 27. made to be synchronized. The data series supplied from the horizontal section 27 to the vertical section 28 is delayed by one horizontal period with respect to the input data series DRi, and is further delayed by passing through the field memory 34 (or sub-memory 35), so that errors may occur. The data series DRi and the syndrome series SDV are supplied to the correction circuit 40 in synchronization.

One configuration of the vertical determination circuit 37 is shown in FIG. The vertical determination circuit 37 individually counts the number of error subblocks in the column direction with respect to the data supplied to the vertical section 28, and if two or more error subblocks are included, it is determined to be uncorrectable and becomes "0". “1” if correctable
The detection signal CRCTV is generated as the final result, and the determination signal CRCTV as the final result is generated in the next field period. One method for realizing such a function is to provide 36 counters to which the error block signals ERBLK for each of the 1st to 36th columns are separately supplied, and use these counters to calculate the error block signal ERBLK for each column. It is possible to determine the number of pieces. However, using as many as 36 counters is wasteful. In the example shown in FIG. 17, 77, 78, 7
The above function is realized by using a shift register indicated by 9.

Before explaining the vertical determination circuit 37, various timing signals and control signals used for processing in the vertical section 28 will be explained with reference to FIG.

RDST shown in A of FIG. 18 is a timing pulse with a field period synchronized with the start of data of each field in the data series DRi and DRo, and thereby defines a certain field TVi, the next field TVi+1, etc. Ru. The field switching pulse SVSL shown in FIG. 18B is the timing pulse RD
This is a pulse in which "0" and "1" are inverted every field in synchronization with ST. VPCEN (C in Figure 18) is 1
It is a timing pulse that has a period of the horizontal parallel period TH and is "0" in the period corresponding to the horizontal parity data. VBREN (D in Figure 18) is the field memory 34
This is a timing pulse that indicates a period for reading data from the vertical syndrome SDV and also indicates a period for correcting a correctable error block using the vertical syndrome SDV. VBENT(
In E) of FIG. 18, the data series is from the horizontal part 27 to the vertical part 2.
VBWEN (F in Figure 18)
) shows the timing pulse extended to include the period until vertical parity data is present. The data series DATA/SEQ from the horizontal section 27 includes horizontal parity data expressed as a hatched area for each horizontal row of data TH1 to TH22, as shown in G in FIG. Contains vertical parity data as horizontal rows of . One sub-block of data reproduced from a magnetic tape includes 105 samples as described above, but as mentioned above, the buffer memory 32 processes one sub-block as 100 samples (two of which are dummy samples). Therefore, the data period of one field is shortened from 246H to approximately 234H. and field memory 34
, the first 10 included in this one subblock
Only 96 samples of data are written to the address corresponding to the bit address signal. However, since horizontal and vertical parity data are not corrected in the vertical section 28, these parity data are stored in the field memory 34.
Do not write to. Writing data to the submemory 35 is also similar to that described above.

PBCLA (H in FIG. 18) is a latch clear pulse applied to one of the two latch circuits of the vertical parity checker 36, and the pulse that is shifted by one field period is applied to the other latch circuit. This is the applied latch pulse PBCLB (I in FIG. 18). In the illustrated example, one side is P in the field period TVi.
It is shown that a syndrome formation operation is performed during the "H" period of BCLA, and a holding operation is performed for this syndrome SDVi for a correction operation in the next field period TVi+1, while the syndrome SDVi that was previously formed in the field period TVi is -1 is held and a new PBCLB is held in the next field period TVi+1.
It is shown that the syndrome is calculated during the period when is "H". Therefore, the vertical syndrome series SDV used in the correction calculation operation is as shown in J of FIG. Furthermore, the corrected data series DRo obtained from the error correction circuit 40 of the vertical section 28 is as shown in K in FIG. This data series DRo is synchronized with the timing pulse RDST, and one subblock has 96 samples.
It includes data missing periods corresponding to other synchronization signals, addresses, and identification signals, and data missing periods corresponding to parity data. This data series DRo is supplied to the time axis expansion circuit 19 (see FIG. 4), and is further passed through the interface 20 and the D/A converter 21, so that it is possible to confirm that a video signal exists in periods other than the horizontal blanking period and the vertical blanking period. The output processor 22 adds a synchronizing signal and an equalization pulse, and outputs the signal to the output terminal 23 as a reproduced video signal.

To explain an example of the vertical determination circuit 37 shown in FIG. 17, the shift register 77 selects one of the output terminals Q1 to Q36 when there is at least one erroneous subblock in each vertical column in each field. The output terminal corresponding to that column is set to "1". Since the horizontal parity data is not subject to error correction as described above, there are a total of 36 vertical columns that are subject to determination. In addition, the shift registers 78 and 79 have 1
Used alternately for each field. That is, when shift register 78 is counting the number of error blocks in each vertical column in a certain field, shift register 79 counts the number of error blocks in each vertical column.
This is generated as a determination result as to whether or not the previous counting result can be corrected.

Error block signal ERBLK is supplied to shift register 77 via OR gate 80. The OR gate 80 has a 36th output terminal Q36.
The signal that appears in is fed back and supplied. A timing pulse VBWEN is supplied to the clear terminal of this shift register 77, and the timing pulse VBWEN is set in a clear state during a period of "0". Furthermore, the shift pulse CK1 (=VBWEN・VPCEN・
FBLKS) is formed and supplied to shift register 77. FIG. 19 shows the first three horizontal periods TH0, TH1 and T of a certain field (SVSL="0").
H2, VBWEN (E in Figure 19), VP
Shift pulse CK1 (I in Figure 19) from timing signals of CEN (C in Figure 19) and FBLKS (F in Figure 19)
is formed, and the error block signal ERBLK starting from the horizontal period TH1 is taken into the shift register 77 via the OR gate 80. Error block signal ERB
As mentioned above, LK is "1" for subblocks that cannot be corrected due to horizontal parity, and "0" for subblocks that are not erroneous. Therefore, for the first horizontal row, for example, for subblock SB2 (E
RBLK="1"), at the end of the horizontal period TH1, among the output terminals Q1 to Q36 of the shift register 77, only Q35 is "1". The error block signal ERBLK is also generated for each sub-block of horizontal parity data. However, since generation of the shift pulse CK1 is prohibited, it is not taken into the shift register 77. The above operation is repeated up to the horizontal row consisting of the 22nd vertical parity data, and if there is one or more error subblocks from the 1st column to the 36th column, that subblock of the shift register 77 The output terminal corresponding to is set to "1". The numbers assigned to the error block signal ERBLK in D in FIG. 19 and the data from the horizontal portion in L in FIG. 19 indicate subblock numbers, and the numbers assigned to other waveforms indicate time slots. It represents.

Output terminal Q3 of such shift register 77
The output appearing at 7 and the error block signal ERBLK are supplied to an AND gate 87. By taking out the output from the output terminal Q37 with a one-bit delay, the timing with the error block signal ERBLK can be aligned. As mentioned above, regarding sub-block SB2 (ERBLK="
1”), the error block signal ERBLK regarding the sub-block SB41 is supplied to the AND gate 87 at the timing when the output terminal Q37 of the shift register 77 becomes “1”, so this also becomes “1”. ”, the output of the AND gate 87 becomes “1”. In other words, the error block signal for each column detected and held by the shift register 77 and the error block signal regarding the sub-block after one horizontal row Synchronizing ERBLK with respect to a column and supplying it to the AND gate 87 is nothing but detecting whether there are two or more sub-blocks with (ERBLK="1") in the same column. Two or more sub-blocks Error subblock exists and AND gate 8
A column in which the output of 7 is "1" means that vertical parity data cannot be corrected.

The output of AND gate 87 is
8A, 88B, each output is OR gate 89
It is supplied to shift registers 78 and 79 via A and 89B. The output appearing at each output terminal Q36 of the shift registers 78, 79 is fed back to the input via OR gates 89A, 89B. Due to this feedback loop, if the detection result supplied via the AND gate 88A or 88B becomes "1" even once,
The detection results for this column are held. For each of the shift registers 78 and 79, a NAND gate 90A,
A clear pulse is provided via 90B. This clear pulse is formed from timing pulses RDST and VBREN by RS flip-flop 92, and is generated at the beginning of each field period. Since the field switching pulse SVSL is inverted by the inverter 91 and applied to the AND gate 88A and the NAND gate 90A, this field switching pulse SVSL
During the field period when L is "0", the output of the AND gate 87 is supplied to the shift register 78 via the AND gate 88A and the OR gate 89A, and the shift register 78 is controlled during each field period by a clear pulse sent via the NAND gate 90A. Cleared first. During the period (SVSL="0"), the contents of the other shift register 79 simply circulate from its output terminal Q39 through the feedback group via the OR gate 89B. In other words, during the field period (SVSL="0"), one shift register 78 receives the detection signal CR indicating whether or not each sub-block can be corrected from the error block signal ERBLK regarding the current field.
CTBL is being generated, and the other shift register 79 is generating the error block signal ERBLK in the previous field.
A determination signal CRCTV is held that ultimately indicates whether or not each column can be corrected. During the field period when the field switching pulse SVSL is "1", the above operations are alternated, and the shift register 79 outputs the detection signal CRCTB.
The shift register 78 generates a judgment signal CRCTV.
occurs.

The detection signal CRCTBL is taken out from the output terminal Q1 of the shift register 78 or 79, and the judgment signal CRCTV is taken out from the output terminal Q36 of the shift register 78 or 79. The multiplexer 93 selects whether to take out the CRCTV. The multiplexer 93 is switched by a field switching pulse SVSL, and when (SVSL="0"), its A side input is taken out as an output, and when (SVSL="1"), its B side input is output. The output of the multiplexer 93 is inverted by the inverters 95 and 96, so that the detection signal CRCTBL and the judgment signal C
RCTV is available. As mentioned above (CRCTBL="
1”) or (CRCTV="1") means that the block can be corrected, and (CRCTBL
="0") or (CRCTV="0") means that the block cannot be corrected. However, the detection signal CRCTBL is “1” in that field.
” may be inverted to “0”. In other words, it is “1” when there is one error or less, but it becomes “0” when two or more errors are counted.

As described above, since the shift registers 77 and 78 perform alternate operations for each field, the shift pulses for each are also switched by the multiplexer 94 for each field. That is, the shift pulse CK2 shown in J in FIG. 19 is formed by the AND gates 81 and 83 (VBWEN·VPCEN·VBLKS). The timing pulse VBLKS has a sub-block period as shown in G in FIG. 19, and the timing pulse FBLK
Therefore, the shift pulse CK2 has a phase slightly delayed from the shift pulse CK1. Also, (VBREN・VPCEN・VBL
A shift pulse CK3 of KS) is formed by an inverter 84 and AND gates 85 and 86. The timing pulse VBREN becomes "1" from the beginning of the field as shown in FIG. 19B, and the timing pulse VBLKS
is shown in H in FIG. 19, so the shift pulse C
K3 is as shown in K in FIG. Shift pulse CK2 (J in FIG. 19) is supplied to a shift register that generates a detection signal CRCTBL, and shift pulse CK3
(K in FIG. 19) is supplied to a shift register that generates a determination signal CRCTV. For example, in a field where the field switching pulse SVSL is "0", the multiplexer 94 is controlled so that the shift register 78 is supplied with a shift pulse CK2, and the shift register 79 is supplied with a shift pulse CK3.

In this field (SVSL="0"), in the first horizontal row period TH0, the shift register 77
The shift pulse CK1 is not applied to the period TH1, and the shift pulse CK1 is applied from the next horizontal period TH1. Similarly, a shift pulse CK2 is supplied to the shift register 78 from the horizontal parallel period TH1. This horizontal period T
In H1, outputs appear sequentially at the output terminal Q37 of the shift register 77 as shown in M in FIG. 19, but since the initial state of the shift register 77 is a clear state, all outputs in the horizontal period TH1 are "0". , and the one supplied via the AND gates 87, 88A and the OR gate 89A is also "0", and the detection signal CR appearing at the output terminal Q1 of the shift register 78 as shown at N in FIG.
CTBL is all "0" during the horizontal row period TH1. On the other hand, in the field period (SVSL="0"), the shift register 79 is circulated by the shift pulse CK3, so as shown in O in FIG. A determination signal CRCTV of the previous field indicating whether or not the data is available is repeatedly generated from the output terminal Q36 of the shift register 79.

Furthermore, in the next horizontal row period TH2, error block signals ERBLK regarding the 1st to 36th subblocks appear from the output terminal Q37 of the shift register 77, and the input error block signal ERBL
It is supplied to the AND gate 87 along with K. Therefore, at the end of this horizontal period TH2, the shift register 7
The contents of 8 are set to "1" only where two error sub-blocks exist in the same column among the two horizontal rows. Such operations are repeated over 22 horizontal row periods of one field, and the final contents of the shift register 78 are such that the positions corresponding to the uncorrectable columns are set to "1". In the next field (SVSL="1"), the shift register 78 is
The contents of are taken out as the determination signal CRCTV, and the shift register 79 is operated by the shift pulse CK2 to generate the detection signal CRCTV.

As described above, in the vertical determination circuit shown in FIG. 17, the detection signal CRCTBL and the determination signal CRCTV can be generated by simply using the shift registers 77, 78, and 79, and the detection signal CRCTVL and the determination signal CRCTV can be generated corresponding to each of the 36 columns. There is no need to provide a counter, and the configuration can be simplified.

Detection signal CRCT from vertical determination circuit 37
BL is applied to the memory control circuit 39 as shown in FIG. 10, and writing of data to the sub-memory 35 is controlled. FIG. 20 shows the configuration of an example of this sub-memory 35 and memory control circuit 39.

Two sub-memories 97A, 97B and flag memories 99A, 99B are provided which perform write and read operations alternately for each field, and memory control circuits 98A, 98B, 100 are provided in association with each memory. ing. Data from the horizontal section 27 (DATA
．． SEQ) is the data input of the submemories 97A and 97B, and the data read from these is the output data DT.
The signal is taken out as S and applied to the error correction circuit 40. Flag memories 99A and 99B store 1-bit vertical error flags SFLA and SFLB for each of the total number of subblocks (858) included in one field, and submemories 97A and 97B
As mentioned above, the capacity is set to be able to store data of a predetermined number, for example, six sub-blocks. During the field period of the field switching pulse (SVSL="0"), for example, the submemory 97A and flag memory 99A perform a write operation, and the submemory 97B and flag memory 99B perform a read operation, and the next (S
In the field period when VSL="1"), the above operations are alternated.

Address codes from write address counter 101W and read address counter 101R are applied to flag memories 99A and 99B. The timing pulse FBLKS (F in FIG. 19) and the clock pulse RCK are supplied to the load pulse generator 102, and the 10-bit address signal in the data from the horizontal section 27 is input to the write address counter 10 by the load pulse.
Loaded into 1W. In addition, the timing pulse FBLK
S and RDST (A in Figure 18) are clear pulse generator 1
03, a clear pulse is formed at the beginning of the field, and this is supplied to the read address counter 101R. As the timing pulse FBLKS is counted by the read address counter 101R, the read address is incremented block by block. These parallel 10-bit write address signals and read address signals are supplied to multiplexers 104A and 104B, and (SVSL
="0"), the write address signal is selected by the multiplexer 104A and applied to the flag memory 99A, and the read address signal is selected by the multiplexer 104B and applied to the flag memory 99A.
Given to 9B. During the field period (SVSL="1"), the read address signal is sent to the flag memory 99.
A and a write address signal is also applied to flag memory 99B.

The timing signal (VPCEN/VBE) from the AND gate 105 is sent to the memory control circuit 100.
NT) is supplied. Timing signals VPCEN and V
Each BENT is shown in C and E of FIG. 18, and is designed to generate write pulses for the flag memories 99A and 99B only in the period in which the output of the AND gate 105 is "1". In other words, no write pulse is generated for sub-blocks related to horizontal parity data and vertical parity data, and the vertical error flags related to these are always set to "0". Similar consideration is given to writing data to submemories 97A and 97B. In other words, the above-mentioned timing signal VP
CEN and VBENT are memory control circuits 98A, 98
By supplying the signal to B, parity data is not written.

Furthermore, the detection signal C from the vertical determination circuit 37
RCTBL and error block signal ERBLK are supplied to AND gate 106. The fact that both of these are "1" and the output of the AND gate 106 is "1" means that the sub-block is correctable and erroneous. However, even when the detection signal CRCTBL is “1”,
Since an error sub-block subsequently occurs within the same column, this may become "0", that is, it may become uncorrectable. Therefore, the output of the AND gate 106 is supplied to the overflow prevention circuit 107, and the submemories 97A and 97B are prevented from overflowing. The output of the AND gate 106 via the overflow prevention circuit 107 becomes a data input to the flag memories 99A and 99B, and also serves as a data input to the sub memory control circuits 98A and 99B.
98B, and controls data writing and write addresses to submemories 97A and 97B. In other words, the data of the sub-block in which the output of the AND gate 106 becomes "1" (the parity data is canceled as described above) is written to the sub-memories 97A and 97B, and during this time the write address is changed to 96 by the clock pulse RCK.
The write address is incremented by a sample, and then when the output of the AND gate 106 becomes "1" again, a similar operation is performed, and the write address is further incremented by 96 samples.

As described above, the field switching pulse S
Submemory 9 in the field specified by VSL
Up to 6 correctable error subblocks are stored for 7A or 97B, and "
1" will be written. In other fields defined by the field switching pulse SVSL, a read address signal is generated that increments for each block generated by the read address counter 101R for the flag memory 99A or 99B, Readout output is vertical error flag S
The signals are extracted as FLA or SFLB, selected by multiplexer 108, and combined to obtain vertical error flag SFLG. This flag memory 9
Vertical error flag SF read from 9A or 99B
LA or SFLB is memory control circuit 98A or 98B
Vertical error flag SFLA or SFLB
The read address for the sub-memory 97A or 97B is incremented in one sub-block period in which is "1". In this way, the data of the correctable error subblock is read from the submemory 97A or 97B in a predetermined time slot in which the vertical error flag SFLG becomes "1".

FIG. 21 shows the configuration of an example of the overflow prevention circuit 107. In the figure, reference numeral 109 indicates a counter, and by applying a timing pulse RDST indicating the beginning of a field to a load terminal of this counter 109, a preset input of a predetermined value is loaded from the preset input generator 110. In the above example, the numerical value of 6 is taken as the preset input. The output of AND gate 106 is taken out as an output via AND gate 111 and is also used as a subtraction input of counter 109 . The carry output of the counter 109 is added to the AND gate 111 as another input. This carry output has been "1" since the preset input was loaded, and becomes "0" when the output of the AND gate 106 exceeds the preset number. Therefore, from this point on, the output from the AND gate 111 becomes "0", and the submemory 97A or 97B is prevented from overflowing.

An example of the error correction circuit 40 of the vertical section 28 is shown in FIG. The error correction circuit 40 receives the vertical syndrome series SDV from the vertical parity checker 36 and the data series DTF read from the field memory 34.
, submemory 35 (97A, 97B in FIG. 20)
A data series DTS read out from the data series DTS is supplied. Along with this, the judgment signal CRCTV and the vertical error flag SF
LG is supplied to the AND gate 112 and a select signal SLCT is formed. 113 and 114 are delay shift registers for phase matching. The select signal SLCT controls the on/off of the gate circuit 115 to which the vertical syndrome SDV is supplied, and
A multiplexer 116 for selecting the data series DTF and DTS is controlled. The output of the gate circuit 115 and the output of the multiplexer 116 are used for error correction (mod
．． 2) is supplied to the adder circuit 117, from which an output data series DRo is obtained.

The four combinations of "1" and "0" of the judgment signal CRCTV and the vertical error flag SFLG are as follows. When the select signal SLCT is "0", the gate circuit 115 is turned off. and the output is “
0" and the data series DTF is selected by the multiplexer 116 and supplied to the adder circuit 117. If the select signal SLCT is "1", the gate circuit 115 is turned on and the data series DTS is selected by the multiplexer 116 and supplied to the adder circuit 117. It is selected and supplied to the adder circuit 117.

(CRCTV="0", SFLG="0"
, SLCT="0") is uncorrectable but not erroneous, so the data series DTF is selected and taken out as the output data series DRo.

(CRCTV="1", SFLG="0"
, SLCT="0") is correctable but not erroneous, so the data series DTF is
is selected.

(CRCTV="0", SFLG="1"
, SLCT="0") is uncorrectable and erroneous. Therefore, the data series DTF from the field memory 34 is taken out as the output data series DRo. Writing of an erroneous subblock to the field memory 34 is prohibited, and the subblock appearing in the data series DTF is data contained in a line spatially located one line below the previous field. That is, an error correction operation is performed.

(CRCTV="1", SFLG="1"
, SLCT="1") is correctable and erroneous, and only in this case the select signal SLCT becomes "1". As a result, the data series DTS from the submemory 35 is transferred to the multiplexer 116.
At the same time, the gate circuit 115 is turned on, and the sub-block in the data series DTS and the corresponding vertical syndrome are added together in the adder circuit 117, and errors are corrected.

[0120]

[Effects of the Invention] As understood from the description of the above embodiment, according to the present invention, two memories, a field memory and a sub-memory, are prepared, and data for error correction is stored in the sub-memory. Therefore, it becomes easy to perform error correction and correction. Additionally, writing of erroneous data to the field memory is prohibited, and erroneous data is interpolated using the data of the previous field located one line below, so the correlation is higher than that of the data of the adjacent line of the same field. It can be interpolated with strong ones. However, unlike forming interpolation data through arithmetic processing, this method has the advantage of not requiring an arithmetic circuit. In the present invention, only correctable and erroneous subblock data is written to the submemory, so there is no need to increase the capacity of the submemory more than necessary. When writing to this submemory, the address is stored using an error flag, so reading from the submemory and correction processing can be easily performed. Furthermore, according to the present invention, it is possible to determine whether error correction in the column direction is possible with a simple configuration using only three shift registers.

[0121] In the above-mentioned embodiment, data for one field was recorded as two parallel tracks.
The data may be recorded as one track or as three or more parallel tracks. Furthermore, something other than a parity code may be used as the error correction code.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram schematically showing the sampling position of a digital video signal and the phase of a color subcarrier.

FIG. 2 is a schematic diagram schematically showing sampling positions of a digital video signal and phases of color subcarriers.

FIG. 3 is a schematic diagram used to explain address control for field memory.

FIG. 4 is a block diagram showing the configuration of a recording system of an embodiment in which the present invention is applied to a digital VTR.

FIG. 5 is a block diagram showing the configuration of a reproduction system of an embodiment in which the present invention is applied to a digital VTR.

FIG. 6 is a schematic diagram used to explain digitization of a video signal and code structure.

FIG. 7 is a schematic diagram used to explain digitization of a video signal and code structure.

FIG. 8 is a schematic diagram used to explain digitization of a video signal and code structure.

FIG. 9 is a time chart used to explain an error control encoder.

FIG. 10 is an overall block diagram of an error correction decoder.

FIG. 11 is a time chart used to explain an error correction decoder.

FIG. 12 is a block diagram of an example of a horizontal determination circuit.

FIG. 13 is a time chart used to explain a horizontal determination circuit.

FIG. 14 is a block diagram of an example horizontal parity checker.

FIG. 15 is a time chart used to explain a horizontal parity checker.

FIG. 16 is a block diagram of an example of a horizontal section buffer memory and error correction circuit.

FIG. 17 is a block diagram of an example of a vertical determination circuit.

FIG. 18 is a time chart showing various timing signals and control signals used in the vertical section.

FIG. 19 is a time chart used to explain a vertical determination circuit.

FIG. 20 is a block diagram of an example of a submemory and its peripheral configuration.

FIG. 21 is a block diagram of an example of an overflow prevention circuit.

FIG. 22 is a block diagram of an example of a vertical section error correction circuit.

[Explanation of symbols]

1 Input terminal for recorded analog video signal 8 Error control encoder 11A, 11B Output terminal for 2-channel recorded digital video signal 12A, 12B Input terminal for 2-channel reproduced digital video signal 18 Error correction decoder 23 Output terminal for reproduced analog video signal 27 Horizontal section 28 Vertical section 29 CRC checker 30 Horizontal judgment circuit 33 Error correction circuit 34 Field memory 35 Sub memory 37 Vertical judgment circuit 40 Error correction circuit

Claims (1)

[Claims] Claim 1: A video signal converted into a digital signal is divided into blocks, an error detection code is added to each data block, a plurality of blocks containing this error detection code are arranged in a matrix configuration, and each row of this matrix and In the digital video signal processing device, an error correction code is added to each column, and a data block in which an error is detected by the error detection code is corrected by the error correction code of the row or column to which it belongs. The configuration line (
Data blocks are transmitted sequentially for each column (or column), and the receiving side performs a first error correction process using the error correction code of the above row (or column), and then performs a second error correction process using the error correction code of the above column (or row). Error correction processing is performed, and a detection signal indicating that the error could not be corrected by the first error correction processing is transferred to a first shift register having a number of bits corresponding to the number of data blocks in one row (or one column). The output of the first shift register is circulated, the signal delayed by the first shift register and the detection signal are supplied to the second shift register via a logic gate circuit, and the output of the first shift register is supplied to the second shift register through a logic gate circuit. A determination signal indicating the position of a column (or row) containing two or more erroneous data in the configuration is generated in the second shift register, and this determination signal is used to perform the second error correction process. A digital video signal processing device characterized by: