JPH04350954A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance system flexibility such as of a gate array integrated circuit loaded with a plurality of output buffers and to optimize the system configuration of a digital apparatus including such a gate array integrated circuit. CONSTITUTION:A pair of output MOSFETs constituting an output buffer are divided into four output MOSFETs Q1, Q3, Q5, and Q7 and Q2, Q4, Q6, and Q8, respectively, which are provided with gate connection regions PFG1-PFGG to form contacts of these output MOSFETs with metal wiring layers corresponding to both ends of gate layer FG1-FG8. This design enables a plurality of split output MOSFETs to be connected in series, parallel, or series-parallel via gate connection regions provided at both ends of each gate layer; therefore, the gate resistors of substantial output MOSFETs are selectively switched on the basis of common master chips, and action characteristics of output buffers can be controlled easily and precisely.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and relates to a technique particularly effective for use in, for example, a gate array integrated circuit equipped with a plurality of output buffers.

0002

2. Description of the Related Art A first output MOSFET (metal oxide semiconductor field effect transistor) is provided between a power supply voltage and an output terminal of a circuit and is selectively turned on when an output signal is set to a high level. In this specification, MOSFE
A second output is provided between the output terminal and the ground potential of the circuit and is selectively turned on when the output signal is set to a low level. There is an output buffer including a MOSFET. Furthermore, there is a CMOS (complementary MOS) gate array integrated circuit that mounts such an output buffer as a standard cell.

A pair of output MOs that are turned on in a complementary manner
An output buffer including an SFET is described in, for example, Japanese Patent Laid-Open No. 146965/1983.

0004

[Problems to be Solved by the Invention] FIG. 10 shows a basic layout diagram of an embodiment of an output buffer mounted on a gate array integrated circuit developed by the inventors of the present invention prior to the present invention. shows its equivalent circuit diagram. Gate array integrated circuits have multiple output buffers,
As illustrated in FIG. 11, each output buffer includes two N-channel type output MOSFETs Q provided in parallel between the power supply voltage VDD of the circuit and the output terminal Dout.
9 and QB, output terminal Dout and circuit ground potential VS
Two other N-channel type output MOSFETs QA and QC are provided between the output MOSFETs QA and QC, respectively. As illustrated in FIG. 10, these output MOSFETs have an N-type diffusion layer ND3 as its drain regions D9-DC and source regions S9-SC, and a predetermined insulating film sandwiched above the P-type diffusion layer. The formed polysilicon layer is configured as the gate layers FG9 to FGC.

The drain regions D9 and DB of the output MOSFETs Q9 and QB are coupled to an aluminum wiring layer (not shown) for supplying the circuit power supply voltage VDD via a contact row CONGD consisting of a plurality of contacts, and the drain regions D9 and DB of the output MOSFETs Q9 and QB are connected to an aluminum wiring layer (not shown) for supplying the power supply voltage VDD of the circuit. Source regions SA and SC are respectively coupled to other aluminum wiring layers (not shown) for supplying a circuit ground potential VSS via contact rows CONGB or CONGF. Further, the source region S9 of the output MOSFET Q9 and the drain region DA of the output MOSFET QA are coupled to the aluminum wiring layer AL13 via the contact row CONGC, and then to the bonding pad PAD which becomes the output terminal Dout, and the source region S9 of the output MOSFET QB is coupled to the bonding pad PAD which becomes the output terminal Dout. Drain region D of SB and output MOSFET QC
C is coupled to the aluminum wiring layer AL14 via the contact row CONGE, and then to the bonding pad PAD. Then, the gate layer FG9 of the output MOSFET Q9 is coupled to the aluminum wiring layer AL1I in its gate connection region PFGI, and then to the non-inverting output node DO of a pre-stage circuit (not shown), and the gate layer FGA of the output MOSFET QA is After being coupled to the aluminum wiring layer AL1H in the connection region PFGH, it is coupled to the inverted output node DOB of the preceding stage circuit. The gate layers FGB and FGC of the output MOSFETs QB and QC have their gate connection regions PFGJ and PFGK open in the master chip, and are used to form an optional wiring path.

However, the inventors of the present invention have discovered that the output buffer as described above has the following problems. In other words, as gate array integrated circuits, etc. become more highly integrated and larger in scale, the influence of power supply noise due to multiple output buffers being activated at the same time is becoming greater. One way to do this is to control the characteristics of the output buffer to suppress changes in the rise or fall of the output signal. On the other hand, from the standpoint of configuring the system, it is desirable that the characteristics of the output buffer can be finely controlled depending on its purpose and the size of the load capacity. However, in the above output buffer, as mentioned above, at most the output MOSFET Q9 or QA is connected in parallel with the output MOSFET Q9 or QA.
It is only possible to selectively connect SFETQB or QC, but it is not possible to finely control its operating characteristics. This impairs the system flexibility of the gate array integrated circuit and makes it difficult to optimize the system.

An object of the present invention is to provide an output buffer whose operating characteristics can be easily and precisely controlled based on a common master chip. Another object of the present invention is to increase the flexibility of a system such as a gate array integrated circuit equipped with a plurality of output buffers, and to optimize the system configuration of a digital device including such a gate array integrated circuit.

[0008]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, each of the pair of output MOSFETs constituting the output buffer is divided into a plurality of parts, and gate connection regions are provided at both ends of the gate layers of these output MOSFETs for forming contacts with the corresponding metal wiring layers.

[0009]

[Operation] According to the above means, a plurality of divided output MOs
SFETs can be selectively connected in series, parallel, or series-parallel via the gate connection regions provided at both ends of each gate layer, so the gate resistance of the output MOSFET can be effectively reduced based on a common master chip. selectively switch,
The operating characteristics of the output buffer can be easily and precisely controlled. As a result, system flexibility such as gate array integrated circuits equipped with multiple output buffers is increased,
The system configuration of a digital device including such a gate array integrated circuit can be optimized.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a partial basic layout of an embodiment of an output buffer master chip to which the present invention is applied. Further, FIGS. 2 to 4 respectively show partial layout diagrams of first to third embodiments of the output buffer, which are the master chip of FIG. 1 plus optional wiring paths, and FIGS. shows equivalent circuit diagrams of the output buffers of FIGS. 1 to 4, respectively. Further, FIG. 9 shows an operational characteristic diagram of the output buffer of FIGS. 2 to 4. Based on these figures, an outline of the configuration and layout of the output buffer of this embodiment and its characteristics will be explained. Note that the output buffer of this embodiment is mounted on a CMOS gate array integrated circuit, although this is not particularly limited. A gate array integrated circuit is equipped with a plurality of output buffers and constitutes a digital device such as a computer. The circuit elements of FIGS. 1-8 are formed on a single semiconductor substrate, such as P-type single crystal silicon, along with other circuit elements mounted on a gate array integrated circuit.

Although not particularly limited, the output buffer of this embodiment has a power supply voltage VD of the circuit as shown in FIG.
Four output MOSFETs Q1 are provided in parallel between D (first power supply voltage) and the output terminal Dout of the circuit.
Q3, Q5, and Q7 (first output MOSFETs) and four more output MOSFETs provided in parallel between the output terminal Dout and the circuit ground potential VSS (second power supply voltage).
SFETQ2, Q4, Q6 and Q8 (second output MOS
FET). Among these, output MOSFETQ1~
As shown in FIG. 1, Q4 connects the N-type diffusion layer ND1 to its drain regions D1 to D4 and source regions S1 to S.
4, and a polysilicon layer formed by sandwiching a predetermined insulating film over the P-type diffusion layer is used as its gate layer FG1 to FG4.
Constructed as. In addition, the output MOSFETs Q5 to Q8
In this example, the N type diffusion layer ND2 is used as its drain region D5 to D8 and the source region S5 to S8, and the polysilicon layer formed on the P type diffusion layer with a predetermined insulating film sandwiched therebetween is used as its gate layer FG5 to FG8. Constructed as. In other words,
In the output buffer of this embodiment, the N-type diffusion layer ND3 of the conventional output buffer shown in FIG. Eight output MOSFETs are formed. Note that the power supply voltage VDD is not particularly limited, but +
It is assumed to be a positive power supply voltage such as 5V.

The drain regions D1 and D3 of the output MOSFETs Q1 and Q3 are coupled to an aluminum wiring layer (not shown) for supplying the power supply voltage VDD through a contact row CONG3 consisting of a plurality of contacts, although not particularly limited thereto. Source regions S2 and S4 of MOSFETs Q2 and Q4 are respectively coupled to two other aluminum wiring layers (not shown) for supplying ground potential VSS via contact row CONG1 or CONG5. In addition, the source region S1 of the output MOSFET Q1 and the drain region D2 of the output MOSFET Q2
is coupled to the aluminum wiring layer AL13 via the contact row CONG2, and then to the bonding pad PAD which becomes the output terminal Dout, and the output MOSFET
The source region S3 of Q3 and the drain region D4 of output MOSFET Q4 are coupled to the aluminum wiring layer AL14 via the contact row CONG4, and then to the bonding pad PAD.

Similarly, the drain regions D5 and D7 of the output MOSFETs Q5 and Q7 are connected to the contact column CONG8.
The source regions S6 and S8 of the output MOSFETs Q6 and Q8 are coupled to the aluminum wiring layer for supplying the power supply voltage VDD via the contact column CONG6 or CONGA, and the other two for supplying the ground potential VSS via the contact column CONG6 or CONGA. are respectively bonded to aluminum wiring layers. Further, the source region S5 of the output MOSFET Q5 and the drain region D6 of the output MOSFET Q6 are coupled to the aluminum wiring layer AL13 and the bonding pad PAD via the contact row CONG7, and the output MOSFET
Source region S7 of TQ7 and output MOSFETQ8
Drain region D8 is coupled to the aluminum wiring layer AL14 and bonding pad PAD via contact row CONG9.

In this embodiment, the output MOSFETQ
At both ends of the gate layers FG1 to FG8 of 1 to Q8, there is a pair of gate connection regions made of the same material as each gate layer, that is, a polysilicon layer, and for forming contact with the corresponding aluminum wiring layer (metal wiring layer). PFG1~PF
A GF is provided for each. Of these, gate connection region PFG2 is coupled to aluminum wiring layer AL11 via a corresponding contact, and further coupled to a non-inverting output terminal DO of a pre-stage circuit (not shown). Furthermore, the gate connection region PFG1 is coupled to the aluminum wiring layer AL12 via a corresponding contact, and further coupled to the inverting output terminal DOB of the preceding stage circuit. Here, the non-inverted output signal DO of the preceding stage circuit is set to high level at a predetermined timing when the corresponding output signal of the gate array integrated circuit is set to logic "1", and is set to low level when set to logic "0". It is said that Moreover, the inverted output signal DOB is
The corresponding output signal of the gate array integrated circuit is logic “1”
When it is set to logic "0", it is set to low level, and when it is set to logic "0", it is set to high level.

[0015] For these reasons, in the master chip of the gate array, the output MOS constituting the output buffer is
As shown in FIG. 5, the gates of FETs Q1 and Q2 are connected to the non-inverting output terminal DO or the inverting output terminal DO of the previous stage circuit.
are coupled to output MOSFETs Q3 to Q, respectively.
Gate No. 8 is left open. Note that, as is clear from FIG. 1, the gate layers FG1 to FG8 of each output MOSFET are short in the so-called gate length direction and long in the gate width direction. For this reason, gate layers FG1 to
FG8 has a predetermined gate resistance RG1 in its width direction.
~ It will have RG8. Needless to say, the resistance values of these gate resistors RG1 to RG8 are as shown in FIGS.
The output MOSFET Q of the conventional output buffer shown in 1
The gate resistance of 9-QC is approximately half that of RG9-RGC.

Furthermore, the output buffer of this embodiment has gate connection regions PFG5 to PFG8 and PFGD to PFG.
Wiring gate layers CFG1 and CFG2 are provided close to FGG and made of the same material as each gate layer, that is, a polysilicon layer. As mentioned above, the upper layer and the periphery of the output buffer include the first layer aluminum wiring layers AL13 and AL14 that serve as the wiring route to the bonding pad PAD, and the second layer or The third aluminum wiring layer is laid out in a complicated manner. Each output M
As described later, the gate layers FG1 to FG8 of the OSFETs are selectively coupled in series, in parallel, or in series-parallel via the corresponding gate connection regions PFG1 to PFGG and the aluminum wiring layer. In some cases, it may not be possible to form an aluminum wiring layer. At this time, the wiring gate layers CFG1 and CFG2 are used in a predetermined combination, thereby making the layout design of the gate array integrated circuit more efficient.

Let us now turn to a description of the output buffer along with optional wiring paths. First, in FIG. 2, an aluminum wiring layer A coupled to the non-inverting output terminal DO of the previous stage circuit
L11 is the gate connection region PF of the output MOSFET Q1
G2, and the second layer aluminum wiring layer AL23 (here, the third layer in the name of the aluminum wiring layer)
The letters represent the number of layers of each aluminum wiring layer. (same below) through output MOSFETQ
3 to the gate connection region PFG3, and further connected to the aluminum wiring layer AL via the aluminum wiring layer AL21.
15. The aluminum wiring layer AL15 is connected to the wiring gate layer CF via the aluminum wiring layer AL27.
G1, and to wiring gate layer CFG2 via aluminum wiring layer AL2E. Further, the wiring gate layer CFG1 connects the output MOSFET Q1 via the aluminum wiring layer AL19 and AL25 and AL29.
, Q3, Q5 and Q7 gate connection regions PFG6, PF
G7, PFGA and PFGB, and the wiring gate layer CFG2 is connected to the aluminum wiring layers AL1A and AL2.
It is coupled to gate connection regions PFGE and PFGF of output MOSFETs Q5 and Q7 via C. As a result, the gate resistances RG1, RG3, RG5 and RG7 of the output MOSFETs Q1, Q3, Q5 and Q7 are coupled in parallel as shown in FIG.
The value of the gate resistance as a whole is one quarter of the resistance value of each gate layer.

Similarly, the inverting output terminal DO of the preceding stage circuit
The aluminum wiring layer AL12 coupled to the output M
It is coupled to the gate connection region PFG1 of the OSFETQ2, and is connected to the gate connection region PFG4 of the output MOSFETQ4 via the aluminum wiring layers AL22 and AL17.
It is further coupled to the aluminum wiring layers AL16 and AL18 via the aluminum wiring layer AL22. The aluminum wiring layer AL16 is coupled to the gate connection region PFG5 of the output MOSFET Q2 via the aluminum wiring layer AL24, and the aluminum wiring layer AL
28 and AL2B to gate connection regions PFG9 and PFGD of output MOSFET Q6, respectively. Further, the aluminum wiring layer AL18 is coupled to the gate connection region PFG8 of the output MOSFET Q4 via the aluminum wiring layer AL26, and the aluminum wiring layer AL
2A and AL2D to the gate connection regions PFGB and PFGG of the output MOSFET Q8, respectively. As a result, the gate resistances RG2, RG4, RG6 and RG8 of the output MOSFETs Q2, Q4, Q6 and Q8 are coupled in parallel as shown in FIG.
The gate resistance value of the ET as a whole is one quarter of the resistance value of each gate layer. Note that the above-mentioned optional wiring route is selectively realized by partially changing the photomask for forming the aluminum wiring layer.

As mentioned above, the output MOSFETs Q1 to Q
8 gate resistors RG1 to RG8 are the output MOSFEs that constitute the conventional output buffer shown in FIGS. 10 and 11.
It is set to be one half of the gate resistance RG9 to RGC of TQ9 to QC. Therefore, the value of the gate resistance of the output MOSFET of the output buffer of this embodiment as a whole is 1/16 of that of the conventional output buffer, and its operation is correspondingly accelerated. Therefore, the signal waveform of the output signal Dout exhibits relatively steep rises and falls, as shown by the thick solid line in FIG. Output buffers with these operating characteristics can be used to transmit high-speed signals that determine the system's machine cycle, or to transmit signals with a small number of bits that are simultaneously output, thereby suppressing power supply noise and increasing system speed. can be achieved.

Next, in FIG. 3, the aluminum wiring layer AL11 coupled to the non-inverting output terminal DO of the previous stage circuit is coupled to the gate connection region PFG2 of the output MOSFET Q1, and is connected to the output MOSFET Q3 via the aluminum wiring layer AL23. is coupled to the gate connection region PFG3. The other gate connection region PF of the gate layer FG1
G6 connects the output MO via the aluminum wiring layer AL1C.
The other gate connection region PFG7 of the gate layer FG3 is coupled to the gate connection region PFGA of SFETQ5 and connected to the output MOSFETQ7 via the aluminum wiring layer AL1D.
is coupled to the gate connection region PFGB of. This results in
Gate resistances RG1 and RG5 and RG3 and RG7 of output MOSFETs Q1 and Q5 and Q3 and Q7
As shown in FIG. 7, they are each connected in series and then connected in parallel, resulting in a so-called series-parallel connection. As a result, the gate resistance value of the output MOSFET as a whole becomes the same as the resistance value of each gate layer, and is four times as large as that in the case of FIG. 2.

Similarly, the inverting output terminal DO of the preceding stage circuit
The aluminum wiring layer AL12 coupled to the output M
It is coupled to the gate connection region PFG1 of the OSFETQ2, and is connected to the gate connection region PFG4 of the output MOSFETQ4 via the aluminum wiring layers AL2F and AL17.
is combined with The other gate connection region PFG5 of the gate layer FG2 is coupled to the gate connection region PFG9 of the output MOSFET Q6 via the aluminum wiring layer AL1B, and the other gate connection region PFG8 of the gate layer FG4 is
Output MOSFET via aluminum wiring layer AL1E
It is coupled to the gate connection region PFGC of Q8. This allows output MOSFETs Q2 and Q6 and Q4 and Q
8 gate resistances RG2 and RG6 and RG4 and R
G8 is connected in series and parallel as shown in FIG. As a result, the gate resistance value of the output MOSFET as a whole becomes the resistance value of each gate layer itself,
The size is four times that of the case shown in FIG.

For these reasons, the output buffer of this embodiment has a slower operating speed than the output buffer of FIG. 2, and the signal waveform of its output signal Dout is as shown by the thin solid line in FIG. In addition, the rise and fall are somewhat gradual. Output buffers with such operating characteristics can be used to transmit signals that require an intermediate transmission speed or an intermediate number of bits to be output simultaneously, thereby suppressing power supply noise and optimizing the system. can be achieved.

On the other hand, in FIG. 4, the aluminum wiring layer AL11 coupled to the non-inverting output terminal DO of the previous stage circuit is coupled to the gate connection region PFG2 of the output MOSFET Q1, and the other gate connection region P of this gate layer FG1 is connected to the gate connection region PFG2 of the output MOSFET Q1.
FG6 outputs M via the aluminum wiring layer AL1C.
It is coupled to the gate connection region PFGA of OSFETQ5. The other gate connection region PFGE of the gate layer FG5 is
Output MOSFET via aluminum wiring layer AL2C
Q7 is coupled to the gate connection region PFGF, and the gate layer F
The other gate connection region PFGB of G7 is further coupled to the gate connection region PFG7 of the output MOSFET Q3 via the aluminum wiring layer AL1D. Thereby, the gate resistances RG1, RG3, RG5, and RG7 of the output MOSFETs Q1, Q3, Q5, and Q7 are connected in series, as shown in FIG. As a result, the output MOSFE
The value of the gate resistance as a whole is four times as large as the resistance value of each gate layer, and is also four times as large as that in FIG. 3.

Similarly, the aluminum wiring layer AL12 coupled to the inverting output terminal DOB of the previous stage circuit is connected to the output MOS
The other gate connection region PFG5 of this gate layer FG2 is coupled to the gate connection region PFG1 of the FETQ2, and the other gate connection region PFG5 of the gate layer FG2 is connected to the output MOSFETQ via the aluminum wiring layer AL1B.
It is coupled to the gate connection region PFG9 of No. 6. Gate layer F
The other gate connection region PFGD of G6 is coupled to the wiring gate layer CFG2 via the aluminum interconnection layer AL1F, and further coupled to the gate connection region PFGG of the output MOSFET Q8 via the aluminum interconnection layer AL1G. The other gate connection region PFGC of the gate layer FG8 is further connected to the output MO via the aluminum wiring layer AL1E.
It is coupled to the gate connection region PFG8 of SFETQ4. This allows the output MOSFETs Q2, Q4, Q6 and Q
The gate resistances RG2, RG4, RG6 and RG8 of 8 are:
As shown in FIG. 8, they are arranged in series. the result,
The gate resistance value of the output MOSFET as a whole is four times as large as the resistance value of each gate layer, and is also four times as large as that in the case of FIG. 3.

For these reasons, the output buffer of this embodiment has a slower operating speed than the output buffer of FIG. 3, and the signal waveform of its output signal Dout is as follows:
As shown by the dotted line in FIG. 9, the rise and fall are very gradual. Output buffers with these operating characteristics can be used to transmit signals that do not require high transmission speeds or signals that have a large number of bits that are output simultaneously, thereby suppressing power supply noise and optimizing the system. can.

As shown in the above embodiment, by applying the present invention to a semiconductor device such as a gate array integrated circuit equipped with a plurality of output buffers, the following effects can be obtained. That is, (1) a pair of output MOSFETs forming an output buffer
By dividing each of the output MOSFETs into a plurality of parts and providing gate connection regions for forming contacts with the corresponding metal wiring layers at both ends of the gate layers of these output MOSFETs, the divided output MOSFETs can be connected to each gate layer. The effect of selectively connecting in series, in parallel, or in series-parallel can be obtained through the gate connection regions provided at both ends. (2) According to item (1) above, it is possible to realize an output buffer that can selectively switch the gate resistance of the actual output MOSFET and easily and finely control its operating characteristics based on a common master chip. Effects can be obtained. (3) Items (1) and (2) above make it possible to increase the system flexibility of gate array integrated circuits equipped with multiple output buffers and to optimize the system configuration of digital devices including gate array integrated circuits. Effects can be obtained. (4) In terms (1) to (3) above, multiple outputs M
By providing a wiring gate layer made of the same material as the gate layer in close proximity to the gate connection region of the OSFET, it is possible to easily realize connection between gate layers in a region where aluminum wiring layers are crowded.

[0027] Above, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, the number of divisions of the N-type diffusion layer may be three or more, and the output MO provided in one N-type diffusion layer may be
The number of SFETs is also arbitrary. Furthermore, the connection between the drain or source of the output MOSFET formed in each N-type diffusion layer and the output terminal Dout of the circuit is formed in each N-type diffusion layer without going through a common aluminum wiring layer. The connection form of the output MOSFETs may also be switched between series and parallel form. Either one of the wiring gate layers CFG1 and CFG2 may be deleted, or the gate connection regions PFG1 to PF may be removed.
A third wiring gate layer may be added close to G4. The connection between the drain or source of the output MOSFET formed in the N-type diffusion layer and the aluminum wiring layer for supplying the power supply voltage VDD and the ground potential VSS can be exchanged with each other. The relationship between aluminum wiring layers AL13 and AL14 for coupling to bonding pad PAD can also be interchanged. Each output MOSFET is N
P-channel MOSF instead of channel MOSFET
ET can be used. Furthermore, the specific connection method of the output buffer shown in FIGS. 2 to 4, the shape and material of the N-type diffusion layer, gate layer, gate connection region, wiring gate layer, etc., the polarity of the power supply voltage, and the conductivity type of the MOSFET are explained. etc., various embodiments can be adopted.

In the above description, the invention made by the present inventor was mainly applied to the field of application, which is the field of application, which is the gate array integrated circuit equipped with an output buffer, but the invention is not limited thereto. For example, the present invention can also be applied to a dedicated logic integrated circuit device formed as a single output buffer, a dedicated logic integrated circuit device including an output buffer, and a semiconductor memory device such as a dynamic RAM and a static RAM. The present invention is widely applicable to output buffers including at least one pair of output MOSFETs and semiconductor devices including such output buffers.

[0029]

[Effect of the invention] A pair of output MOs forming an output buffer
Each SFET is divided into multiple parts, and these output MOSFs are
By providing gate connection regions for forming contacts with the corresponding metal wiring layers at both ends of the gate layer of the ET,
Since a plurality of divided output MOSFETs can be selectively connected in series, parallel, or series-parallel via the gate connection regions provided at both ends of each gate layer, the output MOSFETs can be connected based on a common master chip. By selectively switching the gate resistance, the operating characteristics of the output buffer can be easily and precisely controlled. As a result, system flexibility of a gate array integrated circuit or the like equipped with a plurality of output buffers can be increased, and the system configuration of a digital device including such a gate array integrated circuit can be optimized.

[Brief explanation of the drawing]

FIG. 1 is a partial basic layout diagram showing an embodiment of an output buffer master chip to which the present invention is applied.

FIG. 2 is a partial layout diagram showing a first embodiment of an output buffer in which the master chip of FIG. 1 is added with an optional wiring route;

FIG. 3 is a partial layout diagram showing a second embodiment of an output buffer in which the master chip of FIG. 1 is added with an optional wiring route.

4 is a partial layout diagram showing a third embodiment of an output buffer in which an optional wiring path is added to the master chip of FIG. 1; FIG.

FIG. 5 is an equivalent circuit diagram of the output buffer of FIG. 1;

FIG. 6 is an equivalent circuit diagram of the output buffer of FIG. 2;

FIG. 7 is an equivalent circuit diagram of the output buffer of FIG. 3;

FIG. 8 is an equivalent circuit diagram of the output buffer of FIG. 4;

FIG. 9 is an operational characteristic diagram of the output buffer of FIGS. 2 to 4;

FIG. 10 is a basic layout diagram showing an example of a conventional output buffer.

11 is an equivalent circuit diagram of the output buffer of FIG. 10. FIG.

[Explanation of symbols]

ND1 to ND3...N-type diffusion layer, FG1 to FGC...
・Gate layer, PFG1 to PFGK... Gate connection region, CFG1 to CFG2... Wiring gate layer, D1 to D
C... drain region, S1 to SC... source region,
PAD...Bonding pad, AL11~AL1I
, AL21~AL2F...aluminum wiring layer, CO
NG1~CONGF...Contact row. Q1~QC・
・・N-channel type output MOSFET, RG1~RGC
...Gate resistance.

Claims (5)

[Claims] Claim 1: A plurality of first output MOSFEs provided in parallel between a first power supply voltage and an output terminal of the circuit.
T, and a plurality of second output MOSFETs provided in parallel between an output terminal of the circuit and a second power supply voltage, and a metal wiring layer corresponding to both ends of the gate layer of each of the output MOSFETs. A semiconductor device characterized in that a connection region for forming a contact is provided. 2. A plurality of first output MOSFEs provided in parallel between the first power supply voltage and the output terminal of the circuit.
T, and a plurality of second output MOSFETs provided in parallel between an output terminal of the circuit and a second power supply voltage, and a gate layer of the plurality of first or second output MOSFETs, respectively. A semiconductor device characterized in that it can be selectively connected in series, parallel, or series-parallel configuration. Claim 3: The plurality of first or second output MOSs.
The connection form of the gate layer of the FET is selectively switched by partially changing a part of a photomask for forming a metal wiring layer, and at both ends of each gate layer, 3. The semiconductor device according to claim 2, further comprising a connection region for forming contact with a corresponding metal wiring layer. 4. The semiconductor device includes the plurality of first or second output MOSs using the same material as the gate layer.
These output MOSFs are formed near the FETs.
4. The semiconductor device according to claim 2, further comprising a wiring gate layer that can be a part of a wiring path for connecting gate layers of ETs in series or in parallel. 5. The semiconductor device is a gate array integrated circuit, and the output MOSFET constitutes an output buffer. 4 semiconductor device.