JPH04349660A - Semiconductor devicce and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the parasitic resistance of an element as a whole and to make the element characteristics better especially in the case of an element of minute size, by providing, etc., first metal silicides touching first-conductivity type impurity diffused layers and second metal silicides touching second- conductivity type impurity diffused layers. CONSTITUTION:A device of this invention has first- and second-conductivity type impurity diffused layers 10 and 11 formed on the surface of a semiconductor substrate 8 separated from each other, first metal silicides 15 touching the first-conductivity type impurity diffused layers 10, and second metal silicides 16 touching the second-conductivity type impurity diffused layers 11. For example, the above-mentioned first-conductivity type impurity diffused layers 10 are n-type impurity diffused layers, the first metal silicides 15 are composed of a titanium silicide, the second-conductivity type impurity diffused layers 11 are p-type impurity diffused layers, and the second metal silicides 16 are composed of a cobalt silicide, nickel silicide, platinum silicide, or palladium silicide.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a low resistance diffusion layer using silicide.

0002

2. Description of the Related Art A structure having a metal silicide layer on the surface of an impurity diffusion layer of a semiconductor device has two advantages: (1) the sheet resistance of the diffusion region is substantially reduced and device characteristics are improved; and (2) the sheet resistance is reduced. It has become widely used because it has the advantage that it is more thermally stable than a structure in which a metal layer is placed on the diffusion region for the purpose of this purpose, and it is easily adaptable to manufacturing processes that use high-temperature heat treatment.

In fact, when the diffusion layer becomes shallow, it is not uncommon for the sheet resistance to become about 100Ω/□, but if a structure having a silicide layer on the surface of the diffusion layer is used, the effective sheet resistance of the diffusion layer can be reduced to 1Ω. /□ can be significantly reduced, and device characteristics can be improved.

Furthermore, according to this structure, there is no need to add extra impurities to reduce the sheet resistance of the diffusion layer, so when applied to a MOS type semiconductor device, for example,
The diffusion layer itself only needs to have the minimum impurity concentration necessary for the operation of the device. That is, compared to a structure that does not use a normal silicide layer, the impurity concentration required for forming the diffusion layer can be significantly reduced.

Since increasing the impurity concentration usually leads to an increase in the depth of the diffusion layer, conversely, decreasing the impurity concentration of the diffusion layer is obviously necessary for miniaturizing the device size. This means that it is suitable for forming a shallow diffusion layer. Furthermore, lowering the concentration of the diffusion layer is also effective in preventing the reliability of the device from deteriorating due to electric field concentration within the substrate due to miniaturization.

[0006]

[Problems to be Solved by the Invention] As mentioned above, the structure having a silicide layer is extremely effective in substantially reducing the resistance of the impurity diffusion layer, but by realizing this structure, another resistance element is created. It is meaningless if it happens.

The most important problem here is the contact resistance between the silicide layer and the diffusion layer. The current that flows during the operation of a semiconductor device not only flows through the silicide layer;
Particularly in active device regions such as transistors, the flow flows into the diffusion layer via the silicide layer, so even if the resistance within the silicide layer is reduced, if the contact resistance between the silicide layer and the diffusion layer increases, the effect of lowering the resistance will be reduced. will be canceled out as a whole.

The contact resistance at the metal-semiconductor interface is generally determined by the state of the Schottky barrier formed at the interface between the two layers. That is, the higher the height of the Schottky barrier and the wider the Schottky barrier, the greater the contact resistance. Among these, the height of the Schottky barrier is determined by the combination of metal and semiconductor types, the impurity concentration in the semiconductor substrate, and the type, ie, the conductivity type. As described above,
Since the height of this Schottky barrier is a major factor determining the magnitude of contact resistance, it is a serious problem that the height of the Schottky barrier changes depending on the conductivity type of the semiconductor.

FIG. 13 shows the results showing the change in contact resistance between the p-type impurity diffusion layer and the silicide layer depending on the impurity concentration in the diffusion layer. In the figure, the horizontal axis shows the boron concentration of the diffusion layer, and the vertical axis shows the contact resistance, 121 is the case of titanium silicide, and 122 is the case of cobalt silicide. for example,
When the boron concentration in the diffusion layer is 3 x 1019 cm-3,
In the case of titanium silicide, the contact resistance is approximately 10-4Ωcm2
, 10-6 Ωcm2 for cobalt silicide, and clearly titanium silicide has a p
High contact resistance against mold diffusion. This value of contact resistance of titanium silicide means that it produces a fairly high resistance of about 100 Ω even over a fairly wide area of 100 μm 2 . Since the silicide layer is normally used to make the sheet resistance about 1 Ω/□, such high contact resistance almost cancels out the effect of using the silicide.

FIG. 14 shows a case 131 in which cobalt silicide is used on the surface of the source/drain diffusion layer of a p-channel MOS transistor, a case 132 in which titanium silicide is used, and a case 133 in which no silicide layer is used at all.
The voltage and current characteristics are compared. Here, the channel length of the MOS transistor is 0.5 μm, the channel width is 20 μm, the diffusion depth is approximately 180 nm, and the impurity concentration at the corresponding silicide-diffusion layer interface is 3×101.
It is approximately 9 cm-3, and the gate voltage is 3V. In case 131 using cobalt silicide, the drain current increases by about 20% compared to case 133 not using any silicide layer, and the intended effect of reducing resistance by using the silicide layer is evident. Therefore, in the case 132 where titanium silicide is used, the drain current is rather reduced compared to the case 133 where no silicide layer is used. The fact that this is an effect of the high contact resistance mentioned above is confirmed by the fact that the rise of the characteristic curve in the part where the drain voltage is low has a curvature that is opposite to normal, which is not seen in other cases. It will be done.

It is generally known that the height of the Schottky barrier at the interface between a metal and a semiconductor is almost reversed between an n-type impurity diffusion layer and a p-type impurity diffusion layer. In other words, the lower the metal's Schottky barrier to the n-type impurity diffusion layer, the higher the barrier to the p-type impurity diffusion layer.
The same is true vice versa. This means that the easier it is for a metal to lower the contact resistance with respect to a substrate of one conductivity type, the more difficult it is to lower the contact resistance with respect to a substrate of the other conductivity type. For example, as shown in FIG. 14, when titanium silicide is used for the p-channel MOS transistor 132, the contact resistance is higher than when no silicide is used 133, but when titanium silicide is used for the n-channel MOS transistor, No abnormal characteristics appear due to an increase in contact resistance.

Therefore, when attempting to simultaneously form electrical contact with both n-type and p-type impurity diffusion layers existing on the same substrate using one type of metal silicide, the height of the Schottky barrier increases. For combinations of metal silicide and conductivity type, it is necessary to devise ways to keep this contact resistance low.

One possible way to suppress the contact resistance is to reduce the width of the Schottky barrier by increasing the impurity concentration in the diffusion layer, but this is clearly caused by the lower concentration of the diffusion layer mentioned above. This is nothing but abandoning the effect of miniaturizing element dimensions. Furthermore, if an attempt is made to suppress diffusion and maintain a high impurity concentration at the interface, severe restrictions will be imposed on the overall heat treatment conditions, which will pose a major problem in the actual manufacturing process. Therefore, it can be seen that there is a fundamental problem in attempting to simultaneously obtain low contact resistance for two types of diffusion layers of different conductivity types using only one type of metal.

However, in the case of a CMOS type semiconductor device, for example, an n-type diffusion layer and a p-type diffusion layer exist on the same semiconductor substrate, and considering the symmetry of the circuit, it is difficult to improve device characteristics. It is essential to reduce the resistance of the diffusion layers of both conductivity types at the same time.

[0015] In such a case, in conventional technology, the impurity concentration of one of the diffusion layers is reduced sufficiently to reduce the contact resistance, while being aware of the disadvantages to miniaturization of element dimensions and the restrictions on thermal processing. In practice, the only solution was to increase the number of silicide layers to such an extent that the same silicide layer was formed on the n-type diffusion region and the p-type diffusion region. For example, when titanium silicide is used as the silicide, the Schottky barrier between the p-type diffusion layer and titanium silicide is higher than that of the n-type diffusion layer, so the concentration of p-type impurity must be relatively increased. On the other hand, in the case of cobalt silicide and nickel silicide, the Schottky barrier between them and the n-type diffusion layer is higher, so the concentration of n-type impurities had to be increased. [Structure of the invention]

[0016]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides first and second conductivity type impurity diffusion layers formed spaced apart from each other on the surface of a semiconductor substrate, and the first conductivity type impurity diffusion layers. A semiconductor device is provided, comprising a first metal silicide in contact with the layer and a second metal silicide in contact with the second conductivity type impurity diffusion layer. Here, a Schottky barrier of the first metal silicide to the first conductivity type impurity diffusion layer is lower than a Schottky barrier to the second conductivity type impurity diffusion layer, and The Schottky barrier for the conductivity type impurity diffusion layer is lower than the Schottky barrier for the first conductivity type impurity diffusion layer. Further, the first conductivity type impurity diffusion layer is an n-type impurity diffusion layer, the first metal silicide is made of titanium silicide, the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer, and the first conductivity type impurity diffusion layer is a p-type impurity diffusion layer. The second metal silicide is characterized in that it consists of cobalt silicide, nickel silicide, platinum silicide, or palladium silicide.

Further, a step of forming an impurity diffusion layer of the first conductivity type and an impurity diffusion layer of the second conductivity type on the surface of the semiconductor substrate at a distance from each other; forming a first metal layer on the second conductivity type impurity diffusion layer; next, forming a resist layer on the first conductivity type impurity diffusion layer; and then, at least the second conductivity type impurity diffusion layer. removing the first metal layer on the impurity diffusion layer, then forming a second metal layer on at least the second conductivity type impurity diffusion layer, and then removing the resist layer. A method for manufacturing a semiconductor device is provided, comprising: a step of siliciding the first metal layer and the second metal layer. Further, a step of forming a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer on the semiconductor substrate, and then a step of introducing a first metal ion into the first conductivity type impurity diffusion layer. and a step of introducing a second metal ion into the second conductivity type impurity diffusion layer, and then a step of siliciding the first metal ion and the second metal ion. A method for manufacturing a semiconductor device is also provided.

[0018]

[Operation] In the p-type and n-type impurity diffusion layers on one semiconductor substrate,
For each diffusion layer, the Schottky barrier is low,
That is, by selectively combining silicides capable of reducing contact resistance to form a substantially low-resistance diffusion layer, the parasitic resistance of the element as a whole can be significantly suppressed. In particular, it can be seen that the structure of the present invention has an extremely large effect in improving device characteristics for devices with minute dimensions.

[0019]

【Example】

(Embodiment 1) A first embodiment of the present invention will be described below with reference to FIGS. 1 to 8.

In the first embodiment, metal silicide is selectively formed in a MOS type semiconductor device using a lift-off method.

First, as in the normal SALICIDE process, a p-type well region 9 is formed in an n-type semiconductor substrate 8, and an insulating film 3 for element isolation is formed by selective oxidation. form. Subsequently, as shown in FIG. 1, a gate electrode 4 is formed of polysilicon or the like on the oxide film 31, and using this gate electrode 4 as a mask, a p-type impurity such as boron is added to the n-type semiconductor substrate 8. An n-type impurity such as phosphorus is introduced into the type well region 9 using an ion implantation method or the like to form a high-concentration p-type impurity diffusion region 11 that will become a source/drain region and a high-concentration n-type impurity diffusion region 10. do. Furthermore, an oxide film or nitride film is deposited, and by anisotropic etching, the oxide film or nitride film is removed, leaving the side walls of the gate electrode 4, as shown in FIG.

Next, after forming, for example, a titanium film 12 to a desired thickness as a metal for forming silicide having low contact resistance with the n-type semiconductor, a p-type well is formed using a normal photolithography process. As shown in FIG. 3, the titanium film on at least the p-type impurity diffusion layer 11 on the surface of the n-type semiconductor substrate 8 is selectively removed, leaving the photoresist 13 on the region 9. Subsequently, as shown in FIG. 4, a cobalt film 14, for example, is deposited as a metal that forms silicide with low contact resistance with the p-type semiconductor. Thereafter, as shown in FIG. 5, the photoresist 13 and the cobalt film 14 thereon are simultaneously removed using a suitable solvent.

Through the above steps, the titanium film 12 is deposited on the n-type impurity diffusion layer 10, and the cobalt film 14 is deposited on the p-type impurity diffusion layer 11. Next, by performing heat treatment as in a normal SALICIDE process, as shown in FIG. Each is selectively formed.

Finally, as shown in FIG. 7, the remaining unreacted titanium layer 12 and cobalt layer 14 are etched using a sulfuric acid/hydrogen peroxide mixture and a hydrochloric acid/hydrogen peroxide mixture, respectively. do. If necessary, heat treatment may be performed to further stabilize the silicide layer. Due to the above,
Silicide having low resistance can be formed on the impurity diffusion region for each conductivity type. Subsequently, an insulating layer is formed, contacts are provided, and metal wiring is formed through the contact holes to complete the MOS transistor (FIG. 8).

In the above embodiment, cobalt silicide was used as the type of silicide layer formed on the p-type impurity diffusion layer, but other silicides such as platinum, palladium, and nickel may also be used.

FIG. 12 shows the relationship between gate delay time and load capacitance in the case 111 when the structure of the present invention is applied to a CMOS logic gate circuit, the case 112 when only conventional titanium silicide is used, and the case 113 when no silicide layer is used. shows. Here, the channel length of the CMOS transistor is 0.
5 μm, channel width 20 μm, and diffusion depth approximately 1
80 nm, the impurity concentration at the corresponding silicide-impurity diffusion layer interface is approximately 3×10 19 cm −3 , and the gate voltage is 3V. Since the contact resistance between the titanium silicide and the p-type impurity diffusion layer mentioned above acts as a large load resistance, the case 112 when only titanium silicide is used is rather the case 113 when no silicide layer is used at all. The gate delay time is large compared to . In other words, the original advantage of using a silicide layer is not utilized in a circuit using a fine element having a shallow impurity diffusion layer. On the other hand, in the structure of the present invention, the gate delay time is reduced by about 20% compared to the case where no silicide layer is used, and the advantage of using a silicide layer is utilized in an actual circuit structure. From these results, it can be seen that the structure of the present invention has an extremely large effect in improving the original device characteristics for devices with minute dimensions as shown here.

By the way, the Schottky barrier, which is important in the present invention, occurs at the interface between silicide and silicon, so as long as an appropriate material is selected for this part, various film structures can be formed on it. Deformation is possible.

For example, between the titanium silicide and cobalt silicide used above, titanium silicide has a slightly lower resistivity, so in order to more effectively reduce the parasitic resistance of the device, p-type impurity is added. It is also possible to form another titanium silicide layer above the cobalt silicide layer on the diffusion layer to reduce the sheet resistance. This structure can be realized, for example, by using a method in which after FIG. 7, a titanium film is further formed at necessary locations and then heat treatment is performed. (Embodiment 2) A second embodiment of the present invention will be described with reference to FIGS. 9 to 11. This embodiment is a method of separately introducing into each conductivity type diffusion layer a metal capable of forming a silicide with a small Schottky barrier between it and each diffusion layer.

Similar to the first embodiment, as shown in FIG. 2, a gate electrode 4, a heavily doped n-type impurity diffusion layer 10, and a heavily doped p-type impurity diffusion layer 11 are formed as source/drain regions.

After this, as shown in FIG.
3 is deposited, and through a normal photolithography process,
At least n-type impurity diffusion layer 1 on the surface of p-type well region 9
For example, titanium ions 17 are introduced into the n-type semiconductor by ion implantation as a metal that forms silicide with low contact resistance.

Next, as shown in FIG.
3 is removed once, and a photoresist 13 is deposited again on the p-type well region 9 to form silicide, which has a low contact resistance with respect to the p-type semiconductor, at least in the p-type impurity diffusion layer 11 on the surface of the n-type semiconductor substrate 8. For example, metals that
Cobalt ions 18 are introduced by ion implantation.

Thereafter, the photoresist 13 is removed, and titanium silicide 15 is formed on the surface of the n-type impurity diffusion layer 10 and cobalt silicide 16 is formed on the surface of the p-type impurity diffusion layer 11 by a heating process. As described above, silicide having low contact resistance for each conductivity type can be formed on each impurity diffusion layer. The effect of improving the circuit characteristics of the semiconductor device formed by this example is similar to that of the first example.

In the above embodiment, cobalt silicide was used as the type of silicide layer formed on the p-type impurity diffusion region, but other silicides such as platinum, palladium, nickel, etc. may also be used.

Further, as in the first embodiment, as long as an appropriate material is selected for the silicide-silicon interface, the film structure thereon can be modified in various ways. For example, it is also possible to form another titanium silicide layer above the cobalt silicide layer on the p-type impurity diffusion layer to reduce the sheet resistance. This structure can be realized, for example, by using a method in which after FIG. 11, a titanium film is further formed at necessary locations and then heat treatment is performed.

[0035]

Effects of the Invention As is clear from the above explanation, low resistance can be achieved by selectively combining p-type and n-type impurity diffusion layers on the same substrate with silicide that can reduce contact resistance for each diffusion layer. A diffusion layer can be realized, and the parasitic resistance of the device as a whole can be significantly suppressed. In particular, it can be seen that the structure of the present invention has an extremely large effect in improving device characteristics for devices with minute dimensions. With this structure, it is possible to avoid an increase in impurity concentration in the diffusion layer and restrictions on thermal processes, which are disadvantageous to miniaturization of device dimensions.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of the first embodiment of the present invention.

FIG. 3 is a process sectional view of the first embodiment of the present invention.

FIG. 4 is a process sectional view of the first embodiment of the present invention.

FIG. 5 is a process sectional view of the first embodiment of the present invention.

FIG. 6 is a process sectional view of the first embodiment of the present invention.

FIG. 7 is a process sectional view of the first embodiment of the present invention.

FIG. 8 is a process sectional view of the first embodiment of the present invention.

FIG. 9 is a process sectional view of a second embodiment of the present invention.

FIG. 10 is a process sectional view of a second embodiment of the present invention.

FIG. 11 is a process sectional view of a second embodiment of the present invention.

FIG. 12 is a diagram showing the dependence of gate delay time on load capacitance when the structure of the present invention is applied to a CMOS type semiconductor device.

FIG. 13 is a diagram showing how the contact resistance between the silicide layer and the p-type diffusion layer changes when the boron concentration in the p-type diffusion layer changes.

FIG. 14 is a diagram showing current-voltage characteristics of a p-channel MOS transistor when the type of silicide layer is changed.

[Explanation of symbols]

3 Insulating film for element isolation 4 Gate electrode 5 Gate electrode sidewall insulating film 8 N-type semiconductor substrate 9 P-type well region 10 N-type diffusion layer 11 P-type diffusion layer 12 Titanium thin film 13 Photoresist 14 Cobalt thin film 15 Titanium silicide 16 Cobalt silicide 17 Titanium ions 18 Cobalt ions 31 Oxide film 111 Load capacitance and gate delay time when using the structure of the present invention 112 Load capacitance and gate delay time when using the conventional structure 113 Load capacitance when not using a silicide layer and gate delay time 121 Contact resistance when titanium silicide is used for the boron diffusion layer 122 Contact resistance when cobalt silicide is used for the boron diffusion layer

Claims (5)

[Claims] 1. First and second conductivity type impurity diffusion layers formed at a distance from each other on the surface of a semiconductor substrate, a first metal silicide in contact with the first conductivity type impurity diffusion layer, and the second conductivity type impurity diffusion layer. and a second metal silicide in contact with the layer. 2. A Schottky barrier of the first metal silicide to the first conductivity type impurity diffusion layer is lower than a Schottky barrier to the second conductivity type impurity diffusion layer, and 2. The semiconductor device according to claim 1, wherein a Schottky barrier to the second conductivity type impurity diffusion layer is lower than a Schottky barrier to the first conductivity type impurity diffusion layer. 3. The first conductivity type impurity diffusion layer is an n-type impurity diffusion layer, the first metal silicide is made of titanium silicide, and the second conductivity type impurity diffusion layer is a p-type impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein the second metal silicide is made of cobalt silicide, nickel silicide, platinum silicide, or palladium silicide. 4. A step of forming a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer on the surface of the semiconductor substrate, and then forming the first conductivity type impurity diffusion layer and the second conductivity type impurity diffusion layer. forming a first metal layer on the second conductivity type impurity diffusion layer; next, forming a resist layer on the first conductivity type impurity diffusion layer; and then, at least the second conductivity type impurity diffusion layer. removing the first metal layer on the impurity diffusion layer, then forming a second metal layer on at least the second conductivity type impurity diffusion layer, and then removing the resist layer. A method for manufacturing a semiconductor device, comprising the steps of: siliciding the first metal layer and the second metal layer. 5. Forming a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer on the semiconductor substrate;
a step of introducing a first metal ion into the first conductivity type impurity diffusion layer; a step of introducing a second metal ion into the second conductivity type impurity diffusion layer; , and the step of siliciding the second metal ion.