JPH0434849B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a charge pump circuit used as a component of a phase synchronization circuit in a digital magnetic recording device or the like.

Prior Art Conventionally, this type of charge pump has been constructed as shown in FIG. That is, a series connection circuit of charge current source 1 and current switch 3 and a series connection circuit of discharge current source 2 and current switch 4 are connected to the load via output line 7, and charge input signal 5 is input to current switch 3. When the current switch 3 is turned on, the current switch 3 is turned on and a constant charge current 8 is supplied to the load, and when the current switch 4 is turned on by the discharge input signal 6, the discharge current 9 is caused to flow to discharge the charge of the load.
When both the current switch 3 and the current switch 4 are in the OFF state, neither charging nor discharging is performed, and the charge on the load is stored as is. This circuit uses a charge input signal 5 and a discharge input signal 6 to arbitrarily control charge to the load, discharge, and charge retention, and digitally control the load potential. The transmission frequency can be controlled by

FIG. 2 is a circuit diagram showing a specific configuration of the charge pump circuit of FIG. 1. That is, two
A charge current source 10 is configured by connecting PNP transistors as shown in the figure, a discharge current source 11 is configured by two NPN transistors, and a collector of one transistor of each of the charge current source 10 and discharge current source 11 is configured. Connect in series through a resistor. Therefore, the charge current of charge current source 10 and the discharge current of discharge current source 11 are equal in magnitude.

The charge current output from the charge current source 10 is supplied to the load through the output line 16 when the charge current switch 12 is on, and the charge on the load is
When the discharge current switch 13 is on, the discharge current is discharged via the discharge current source 11. When both the charge current switch 12 and the discharge current switch 13 are off, the charge on the load is maintained as is.

The charge current switch 12 includes two PNP transistors and a set of NPN for controlling the base voltages of the two PNP transistors, respectively.
A circuit in which transistors are connected as shown in the figure, and the on/off of the two PNP transistors is controlled by applying a charge input signal 14 between the bases of the pair of NPN transistors. . That is, charge current switch 1
2 is controlled by a charge input signal 14. Discharge current switch 13
is a circuit in which two NPN transistors are connected as shown in the figure, and the on/off of the discharge current switch 13 is controlled by applying the discharge input signal 15 between the bases of the two NPN transistors. be done.

The conventional circuit described above has a charge current switch 12
Since a PNP transistor is used in the circuit, it is difficult to perform high-speed switching operations when integrated into an IC. In other words, the conventional charge pump circuit has the drawback of hindering the implementation of high-speed charge pump circuits into ICs.

OBJECT OF THE INVENTION The object of the invention is to solve the above-mentioned conventional drawbacks and
without using a high speed PNP transistor switch,
The object of the present invention is to provide a charge pump circuit that can operate at high speed.

Structure of the Invention The charge pump circuit of the present invention includes a charge current source, a first discharge current switch for discharging the output current of the charge current source, and a second discharge current switch connected in parallel to the first discharge current switch. a current switch; and first and second discharge current sources connected to the first and second discharge current switches, respectively, to charge current to the load by turning on the first discharge current switch. is set to 0, a constant charge current is output when the switch is turned off, and the charge of the load is discharged when the first and second discharge current switches are turned on.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention. That is, the resistor 40, the PNP transistor 31, the resistor 42, the NPN transistor 32, and the resistor 43 are connected in series between the positive power supply Vcc and the negative power supply Vee, and the PNP transistor 31 and the NPN transistor 32 are connected between their respective collectors and bases. Make a short-circuit connection to form a reference current source. and,
Connect the collector of PNP transistor 33 to resistor 41
The base of the PNP transistor 31 is connected to the positive power supply Vcc through the PNP transistor 31, and the PNP transistor 33 and the resistors 40 and 41 constitute a current mirror circuit.
A certain charge current is output depending on the collector current of . In this embodiment, the PNP transistor 33 constitutes a charge current source.

Further, the emitter of the NPN transistor 34 is connected to the negative power supply Vee through the resistor 44, and the base is connected to the base of the NPN transistor 32 to form a current mirror circuit. Set the discharge current. In this example,
NPN transistor 34 is the first discharge current source. Similarly, NPN transistor 35
The emitter of is connected to the negative power supply Vee through a resistor 45, and the base thereof is connected to the base of the NPN transistor 32 to constitute a second discharge source.

The collector of the NPN transistor 34 is connected to the emitters of the NPN transistor switches 36 and 37, the collector of the NPN transistor switch 36 is connected to the positive power supply Vcc, and the collector of the NPN transistor switch 37 is connected to the emitters of the NPN transistor switches 36 and 37.
Connect to collector 3. In this example, NPN
Transistor switch 37 constitutes a first discharge current switch and connects the differential logic signal 4 between the bases of NPN transistor switches 36 and 37.
6 and 47, the NPN transistor switch 37 is controlled to be turned on and off by the current switching operation of the switches 36 and 37. When the NPN transistor switch 37 is on, the charge current output from the PNP transistor 33 and
The discharge current flowing through the NPN transistor switch 37 is equal, so that neither charge nor discharge current flows through the load.
When the NPN transistor switch 37 is in the off state, the charge current output from the PNP transistor 33 is supplied to the load through the output line 50.

On the other hand, NPN transistor switches 38 and 39
The emitters of the NPN transistor switches 38 and 39 are connected in common to the collector of the NPN transistor 35. The NPN transistor switch 38 is controlled on and off by differential logic signals 48 and 49 input between the bases of the NPN transistor switches 38 and 39. When the NPN transistor switch 38 is in the on state, a discharge current flows through the collector of the NPN transistor switch 38, and the charge on the load is transferred to the output line 50 and
It is discharged through NPN transistor switch 38. In this embodiment, resistors 40 and 4
1 have the same resistance value, and resistors 43 and 43 have the same resistance value.
44 and 45 are also set to the same resistance value. Therefore, the collector currents of PNP transistor 33, NPN transistors 34 and 35 are all the same value.

To summarize the above, when both the NPN transistor switches 37 and 38 are off, a constant charge current is supplied from the collector of the PNP transistor 33 to the load, and the NPN transistor switch 38
When 37 is off and 37 is on, neither charge nor discharge is performed, and the NPN transistor switch 3
When 7 and 38 are both on, a constant discharge current reduces the charge on the load. Therefore, a charge pump operation is possible in which charge and discharge to the load are arbitrarily controlled by the logic signals 46 to 49. In this embodiment, all the switch circuits are composed of NPN transistor switches, so it is possible to easily integrate a high-speed charge pump circuit into an IC.

Effects of the Invention As described above, in the present invention, the first discharge current switch that turns on and off the same discharge current as the output current of the charge current source, and the similar second discharge current switch are all NPN transistors. When the first discharge current switch is turned off, a constant charge current is supplied to the load, and when the first discharge current switch is turned on, charge and discharge current are set to the same current value, and neither charge nor discharge is performed. Since constant discharge is performed by turning on the second discharge current switch, it is possible to construct a high-speed charge pump circuit without using a high-speed PNP transistor switch. As a result, the high-speed charge pump circuit can be easily integrated into an IC.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional charge pump circuit, FIG. 2 is a circuit diagram showing a specific example of the conventional charge pump circuit, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. In the figure, 1... Charge current source, 2... Discharge current source, 3, 4... Current switch, 5... Charge input signal, 6... Discharge input signal,
7... Output line, 8... Charge current, 9... Discharge current, 10... Charge current source, 11... Discharge current source, 12... Charge current switch,
13... Discharge current switch, 14... Charge input signal, 15... Discharge input signal,
31, 33...PNP transistor, 32, 34,
35...NPN transistor, 36-39...NPN transistor switch, 40-45...Resistor, 46
~49...Differential logic signal.

Claims (1)

[Claims] 1 a charge current source 33, a first discharge current switch 37 for discharging the output current of the charge current source, and second discharge current switches 38, 39 connected in parallel to the first discharge current switch; Said first
and a first discharge current source 34 respectively connected to a second discharge current switch.
and a second discharge current source 35, the first discharge current source being the first discharge current source.
The discharge current source is set so that when the discharge current switch is on, the charge current to the load circuit 50 is zero, and when it is off, the charge current to the load circuit is constant, and the second discharge current source is connected to the first and second discharge current sources. A charge pump circuit characterized in that the charge pump circuit is configured to discharge the charge in the load circuit when both of the two discharge current switches are on.