JPH04348437A - Debugging device - Google Patents

Abstract

PURPOSE:To use effectively a register contained in a debugger by performing a debugging job in consideration of the synchronization between the microprocessors when the data are transferred between the CPUs and also omitting the need to set the break conditions to plural debuggers. CONSTITUTION:A debugging job is applied to a parallel processing computer where the processors 11-14, a 1st memory 20 which stores the data shared to all processors, and a 2nd memory are connected to each other via a common bus. A shared debugger 21 monitors the operation of each microprocessor when the data are transferred to the memory 20 or to another microprocessor. Meanwhile each 2nd local debugger monitors the operation of each microprocessor when the data are transferred to the microprocessors and the 2nd memories corresponding to these microprocessors. Then the date on the debugging jobs are transferred to a local debugger from the debugger 21.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a system in which a plurality of microprocessors, a memory for storing data shared by these microprocessors, and a plurality of dedicated memories for storing data exclusive to each microprocessor are connected by a common bus. The present invention relates to a debugging device that performs debugging work on a parallel processing computer.

0002

2. Description of the Related Art FIG. 6 is a block diagram of a conventional debugging device using four microprocessors each having a function of accepting break requests.
-18 specific examples are shown in FIG.

In FIG. 6, the CPU units 15 to 18 include a CPU 90, a local debugger 92, and a cache memory 94, as shown in FIG.
The CPUs included in each of the PU units 15 to 18 are referred to as CPUa.
, CPUb, CPUc, and CPUd. shared memory 2
0 holds the addresses output by CPUa to CPUd, data input/output, etc., and the bus arbiter 22 holds the addresses output by CPUa to CPUd.
The transfer interrupt controller 23 outputs the arbitration result for bus use according to the signal output by PUd requesting bus use, and the transfer interrupt controller 23
When transferring data between U, a signal from the transfer source CPU is input, and an interrupt signal is output to the transfer destination CPU.

The shared bus 24 is connected to the CPUs CPUa to CPUd and the shared memory 20, and the request signals 31 to 34 are the outputs of the CPUs CPUa to CPUd, respectively, and are connected to the bus arbiter 22.
A request to use the shared bus 24 is made to the CP.Acknowledge signals 36 to 39 are outputs of the bus arbiter 22, and each
The arbitration result of the use of the shared bus 24 is transmitted to Ua to CPUd. Transfer request signals 41 to 44 request an interrupt to the transfer destination CPU during data transfer between CPUs, and transfer interrupt signals 46 to 49 are outputs of the transfer interrupt controller 23,
When transferring data between PUs, an interrupt is sent to the transfer destination CPU, and local buses 65 to 68 are connected to CPU units 15 to 18 (CPU
It is the input/output of Ua to CPUd) and is connected to the shared bus 24.

FIG. 7 is a block diagram of a specific example of the CPU section 15 in FIG. 6, and the CPU sections 16 to 18 also receive request signals,
They are the same except that the acknowledge signal, transfer interrupt request signal, transfer interrupt signal, and local bus number are different. This CPU section is composed of a CPU 90, a local debugger 92, and a cache memory 94, and the local debugger 92 is composed of a register 73 and a comparator 78. The break signal 58, which is the output of the comparator 78, issues a break request to the CPU 90 (in this case, CPUa), and the register(s) 73 holds information such as addresses and data to be broken. The comparator 78 receives the local bus 65 and the register signal 83 output from the register 73.
The comparison result is output as a break signal 58.

The CPU 90, as a microprocessor, outputs addresses and inputs/outputs data etc. on the local bus 65, requests the bus arbiter 22 to use the bus, accepts arbitration results, and uses the other three when transferring data between CPUs. C
Transfer interrupt request signal 41 for interrupting the PU
It outputs a transfer interrupt signal 46 from the other three CPUs, and accepts a break request. local debugger 92
accepts addresses, data, etc. on the local bus 65,
C by the break condition set in the internal register 73.
Outputs a break request to the PU 90 and stores it in the cache memory 9.
4 holds data exclusive to the CPU 90.

FIG. 8 is a circuit diagram of an example of comparator 78 of FIG. This comparator performs an exclusive NOR operation on each bit of the register signal 83 and the local bus 65 corresponding to this register signal 83, and applies the result to the AN
This is achieved by integrating using D operations.

FIG. 9 is a circuit diagram of an example of the transfer interrupt controller 23 of FIG. 6. There are 12 transfer interrupt request signals 41 to 44, three each, from CPUa to CPU
b, CPUc, CPUd, from CPUb to CPUa,
CPUc to CPUa, CP to CPUc, CPUd
Ub, CPUd, from CPUd to CPUa, CPUb
, CPUc, respectively. The transfer interrupt controller 23 performs an OR operation on three transfer interrupt request signals to the CPU a and outputs the result as a transfer interrupt signal 46. Similarly, CPUb, CPUc,
The three transfer interrupt request signals to CPUd are ORed and the results are output as transfer interrupt signals 47 to 48, respectively.

FIG. 10 is a schematic diagram illustrating data transfer between CPUs via the shared memory 20.
An example of data transfer between CPUs via the shared memory 20 when data is transferred to PUa is shown.

First, at t1, a lock area is set in the shared memory 20 in order to synchronize CPUa and CPUb. Next, the data to be transferred is written into the shared memory 20 at t2. Next, at t3, the CPUb outputs a transfer interrupt request signal 42 to the CPUa, and the transfer interrupt signal 46 passes through the transfer interrupt controller 23 to interrupt the CPUa. If an interrupt is applied to CPUa, CPUa
reads the transfer data in the shared memory 20. lastly,
At t5, the CPUa releases the clock region set in the shared memory 20.

The operation in FIGS. 6 and 7 will be explained. Local debugger 92 connected to each of the four CPUs 90
A break condition address, data, etc. are held in advance in a register 73 (setting of break conditions is done by software), and the content of the register signal 83 output by that register 73 and the contents of the register signal 83 output by the CPU 90 are stored in the cache memory 94 or shared memory. It compares the contents of the local bus 65, such as addresses and data used when accessing (reading, writing, etc.) 20, and outputs the comparison result to the CPU 90 as a break signal 58.

[0012] The four local debuggers independently
When U is debugged and a certain local debugger satisfies a break condition, the CPU connected to that local debugger stops execution of the program.

[0013]

[Problems to be Solved by the Invention] In the conventional debugging device described above, debugging for each microprocessor only performs debugging work for that microprocessor. When attempting to cause a break, even if the break condition is satisfied at the transfer source, the break condition does not necessarily hold true because the transfer destination does not recognize which CPU the data is transferred from. To avoid this, you can set the break condition in the transfer source and transfer destination debuggers, or set it in all debuggers, but this has the disadvantage of wasting the register resources in the debugger. .

[0014] The purpose of the present invention is to eliminate such drawbacks,
It is an object of the present invention to provide a debugging device that can effectively utilize registers without setting break conditions for multiple debuggers by using a shared debugger.

[0015]

[Means for Solving the Problems] The structure of the present invention includes a plurality of microprocessors, a first memory capable of storing data shared by all of these microprocessors, and a first memory capable of storing data exclusive to each of the microprocessors. In a debugging device that performs debugging work on a parallel processing computer in which a plurality of second memories capable of a first debugger that monitors the operation of each microprocessor during data transfer from one microprocessor to another;
a plurality of second debuggers that respectively monitor the operation of each microprocessor during data transfer between each of the microprocessors and each of the second memories corresponding to the microprocessors; The present invention is characterized by comprising means for transferring data for debugging work to a debugger.

[0016] In the present invention, the first debugger detects an arbitrary data pattern that corresponds to a data pattern constituted by an address signal outputted by a microprocessor, an input/output data signal, and other input/output signals. a CP that holds registers that hold and identification numbers that correspond to the unique identification numbers that each of the microprocessors has;
The UID circuit compares the contents held in the register with the address signal outputted by the microprocessor, the input/output data signal, and other input/output signals, and
A comparator that compares the contents held in the PUID circuit with a signal representing the arbitration result output by a circuit that arbitrates bus use, and outputs a comparison result that integrates these comparison results, and a comparator that outputs a comparison result that integrates these comparison results, and a a logic circuit that performs a logical operation using a signal that temporarily interrupts the execution of the transfer destination microprocessor, a signal representing the arbitration result of the bus use, and an output signal of the comparator, and outputs the result of the operation as a break signal; It can consist of.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention using four microprocessors having the function of accepting break requests. In this embodiment, the CPU units 11 to 14
, a shared memory 20 , a shared debugger 21 , a bus arbiter 22 , a transfer interrupt controller 23 , a shared bus 24 , and a local bus 25 .

In the figure, the CPU sections 11 to 14 are shown in FIG.
As shown in the figure, each includes a CPU 90, a local debugger 91 and a cache memory 94.
The CPUs included in the U units 11 to 14, respectively, are CPUa,
Let them be CPUb, CPUc, and CPUd. shared debugger 2
1 sets a break condition internally in advance, outputs the break condition to the debugger bus 25, and outputs the break condition to the bus arbiter 22.
, the transfer interrupt signals 46 to 49 output from the transfer interrupt controller 23, and the shared bus 24, and output break signals 51 to 54 according to internal break conditions.

Further, the debugger bus 25 is connected to the shared debugger 2.
The break condition output from 1 is output to the local debugger 91 in the CPU sections 11 to 14, and the break conditions are output to the local debugger 91 in the CPU units 11 to 14, and break signals 51 to
54 is output from the shared debugger 21 to break the CPU 90 in the CPU units 11 to 14, and is output to the local bus 6.
1 to 64 are CPU units 11 to 14 (CPUa to CPUd)
, and is connected to the shared bus 24. Note that the other parts are the same as those of the conventional example, so the explanation will be omitted.

FIG. 2 is a concrete block diagram of the shared debugger 21 shown in FIG. 1. This circuit consists of M registers 7 that hold information such as addresses and data to be broken.
1, M CPU IDs 75 holding identification numbers corresponding to the CPUs on which the break condition set in this register 71 is processed, a shared bus 24, and a register signal 81.
In addition to comparing the acknowledge signals 36 to 39 and CP
It is composed of a comparator 76 that compares UID signals 85 to 89 and outputs the comparison result as a break signal 55, and a logic circuit section. The register signal 81 is the contents held in the register 71 and becomes an input to the comparator 71 and the debugger bus 25, and the CPUID signals 85 to 89 are the contents held in the CPUID 75 and are input to the comparator 71 and the debugger bus 25.

FIG. 3 is a circuit diagram of an example of the comparator 71. This comparator 71 performs an exclusive NOR operation bit by bit on the register signal 81 and the shared bus 24 corresponding to this register signal 81, and also performs an exclusive NOR operation on the register signal 81 and the shared bus 24 corresponding to this register signal 81.
6 to 39 and CPUID signals 85 to 89, respectively, and perform an exclusive NOR operation on them, and AND the results.
The signals are integrated by calculation and output as a break signal 55.

FIG. 4 is a block diagram of a specific example of the CPU section 11 in FIG. 1, and the CPU sections 12 to 14 also receive request signals,
They are the same except that the acknowledge signal, transfer interrupt request signal, transfer interrupt signal, break signal, and local bus number are different. This CPU section 11 includes a CPU 90
, a local debugger 91 , and a cache memory 94 , and the local debugger 91 is comprised of a register 72 and a comparator 77 . local debugger 91
A break signal 56, which is the output of the CPU 90, issues a break request to the CPU 90 (in this case, CPUa). The result of ORing this break signal 56 and the input break signal 51 becomes a break signal 57 to the CPU 90.

The register 72 is an input from the debugger bus 25 and holds information such as address and data to be broken, and the comparator 77 is input from the local bus 61 and register 7.
2 and outputs the comparison result as a break signal 56. This local debugger 91 accepts addresses, data, etc. on the local bus 61, and outputs a break request to the CPU 90 according to break conditions set in an internal register 72.

The operation of this embodiment will be explained below. Before program execution, a break condition address, data, etc. are set in the register 71 in the shared debugger 21. When this setting is made, the identification number corresponding to the CPU that processes the address is held in the CPU ID 75. for example,
When processing is performed by CPUa, it is held as "1000". This setting to the CPU ID 75 is managed by software, for example, an OS (operating system).

Next, the contents of the register 71 are set to CPUID.
It is output via the debugger bus 25 to the register 72 in the local debugger 91 which performs debugging of the CPU corresponding to the identification number 75. At this time, the contents of the CPUID 75 are also output to the debugger bus 25, and it is managed which of the four local debuggers to output to. For example, C.P.
When the UID 75 is "1000", the contents of the register 71 are output only to the local debugger 91 that debugs the CPU section 11, that is, the CPUa. Repeat this process as many times as the set break condition.

During program execution, the four local debuggers 91 mainly perform debugging work when accessing each cache memory 94. In the register 72 in each local debugger 91, the break condition of the address processed by the CPU 90 corresponding to that local debugger 91 is held by the above operation. Therefore, the local debugger 91 uses the cache memory 94
If the break condition is met when accessing, the CPU90
breaks and stops program execution. In this case, the four local debuggers 91 are operating independently in this case.

The shared debugger 21 mainly uses the shared memory 20
Perform debugging work when accessing the CPU and when transferring data from one CPU to another CPU. When accessing the shared memory 20, the accessing CPU, that is, the CPU using the shared bus 24, can be recognized by the acknowledge signals 36 to 39 output from the bus arbiter 22. Therefore, the shared bus 24 and the register 71, the acknowledge signals 36 to 39, and the CPU ID 75 are compared, and the break signal 55, which is the result of integrating the comparison results, is ANDed with the acknowledge signals 36 to 39, respectively, and the results are used as the break signals 51 to 39. 54 to each CPU, only the CPU that has accessed the shared memory 20 is broken.

When transferring from a CPU to another CPU, the acknowledge signals 36 to 39 represent the transfer source CPU, and the transfer interrupt signals 46 to 49 represent the transfer destination CPU, so an OR operation is performed on each of them. Furthermore, each break signal 5
By outputting the result of the AND operation with 5 to each CPU as break signals 51 to 54, the transfer source and destination CPUs
Break PU.

FIG. 5 shows a block diagram of an example of a shared debugger according to the second embodiment of the present invention using four microprocessors.

In this embodiment, all of the transfer interrupt signals 46 to 49 are ORed, and the result and the acknowledge signals 36 to 3 are
9 are ORed and the result is sent to the break signal 55.
The results of the AND operation are sent to break signals 51 to 5.
4 and is output to each CPU. This case differs from the first embodiment in that, at the time of transfer, not only the transfer source and transfer destination but also all CPUs are broken.

[0031]

As explained above, the present invention uses a shared debugger that manages all N microprocessors in addition to N local debuggers that manage each of N microprocessors. Especially CPU
When transferring data from one CPU to another, it is possible to perform debugging work that takes into account synchronization between microprocessors, and there is no need to set break conditions in multiple debuggers, allowing effective use of registers within the debugger. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention;

[Figure 2] Figure 1
A block diagram of an example of the shared debugger 21 of

[Figure 3] Figure 2
A circuit diagram of an example of the comparator 76 of

FIG. 4 is a block diagram of a specific example of the CPU section in FIG. 1;

FIG. 5 is a block diagram of a second embodiment of the shared debugger of FIG. 1;

[Fig. 6] Block diagram of a conventional debug device,

[Figure 7]
A block diagram showing a specific example of the CPU section in FIG. 6,

[Figure 8]
Circuit diagram of comparator 78 in local debugger of FIG.

FIG. 9 is a circuit diagram of an example of the transfer interrupt controller 23 in FIG. 6a;

FIG. 10 is a schematic block diagram illustrating data transfer between CPUs via the shared memory 20;

[Explanation of symbols]

11-18 CPU section 20 Shared memory 21 Shared debugger 22 Bus arbiter 23 Transfer interrupt controller 24 Shared bus 25 Debugger buses 31-34 Request signals 36-39 Acknowledge signals 41-44 Transfer request signals 46-49
Transfer interrupt signals 51-58 Break signals 61-68 Local buses 71-73 Register 75 CPUID 76-78 Comparators 81-83 Register signals 85-89 CPUID signal 90 CPU 91, 92 Local debugger 94 Cache memory

Claims (2)

[Claims] 1. A plurality of microprocessors, a first memory capable of storing data shared by all of these microprocessors, and a plurality of second memories capable of storing data exclusive to each of the microprocessors. In a debugging device that performs debugging work on a parallel processing computer connected by a common bus, when data is transferred between the microprocessor and the first memory, or when data is transferred from one microprocessor to another microprocessor. a first debugger that monitors the operation of each of the microprocessors during data transfer between each of the microprocessors and the second memories that correspond to the microprocessors; 1. A debugging device comprising: two debuggers; and means for transferring debugging data from the first debugger to each of the second debuggers. 2. A first debugger holds an arbitrary data pattern corresponding to a data pattern formed by an address signal outputted by the microprocessor, an input/output data signal, and other input/output signals. A register, a CPUID circuit that holds an identification number corresponding to the unique identification number of each microprocessor, the contents held in the register, address signals output by the microprocessor, data signals input/output, and other inputs. a comparator that compares the content held in the CPUID circuit with a signal representing an arbitration result output from a circuit that arbitrates bus use, and outputs a comparison result that integrates these comparison results; Performing a logical operation using a signal that temporarily suspends execution of the transfer destination microprocessor during data transfer between the respective microprocessors, a signal representing the arbitration result of the bus use, and an output signal of the comparator. 2. The debugging device according to claim 1, further comprising a logic circuit that outputs a result as a break signal.