JPH04333828A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To improve the resolution and sensitivity of a liquid crystal display by increasing additional capacity. CONSTITUTION:A TFT gate electrode 7 and a 1st additional capacitor are formed of a polycrystalline silicon layer as a 2nd layer on the active layer 3 of a TFT formed of a polycrystalline silicon layer as a 1st layer formed on a quartz substrate 1 across a gate insulating film 9 to form the 1st additional capacitor of the active layer 3 and a capacitor electrode 11, and a capacitor electrode 14 is formed of a transparent electrode film separated from a picture element electrode 2 on the capacitor electrode 11 across an insulating film 12 for the additional capacitor to form a 2nd additional capacitor of the capacitor electrodes 11 and 13. Then the capacitor electrode 13 is connected to the active layer 3 through a contact hole 14 and the ground potential is applied to the capacitor electrode 11 to connect the 1st and 2nd additional capacitors in parallel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of an additional capacitor for a TFT (thin film transistor) used as a drive switch for liquid crystal in a liquid crystal display device, particularly in an active matrix display type liquid crystal display device.

0002

2. Description of the Related Art Generally, when displaying fine images such as on a television, a high-resolution image is required, so a more fine matrix structure is required than in a character display or the like. In the case of the conventional simple matrix display method, the finer the matrix structure, the greater the number of scanning electrodes and display electrodes, which slows down the response speed of the liquid crystal and causes problems due to crosstalk.

[0003]Recently, therefore, a so-called active matrix display system, in which a liquid crystal is directly switched and driven using an array of switching elements arranged in a matrix, has attracted attention and has been put into practical use. This display method does not have the problem of crosstalk, and by making full use of LSI manufacturing technology that has recently made remarkable progress, it is possible to easily realize liquid crystal televisions and the like that can display extremely fine images.

A conventional active matrix display type liquid crystal display device will be explained with reference to a plan view of FIG. 21 and a cross-sectional view of FIG. 22. Here, the left half of FIG. 22 is a cross-sectional view taken along the line A--A in the area ■ in FIG. 21, and the right half is a cross-sectional view taken along the line B--B in the area ■.

That is, a picture element electrode 42 made of a transparent electrode film (for example, an ITO film) is formed on a quartz substrate 41 corresponding to each picture element, and an active layer of a TFT is formed in a space for forming wiring between these picture element electrodes 42. A first polycrystalline silicon layer 43 is formed, and the pixel electrode 42 is connected to the drain region D of the active layer 43, and the Al layer constituting the signal line L is connected to the source region S of the active layer 43. -Si electrode 44 is connected. Further, the gate electrode 45 of the TFT is formed of one of the second polycrystalline silicon layers, and constitutes the selection line W. In FIG. 22, 46 is an interlayer insulating film, 47 is a gate insulating film, and 48 is a passivation film such as a SiN film.

[0006] Also, in the region (1) of FIG. 21 and the right half of FIG. 22, the first polycrystalline silicon layer (active layer 43),
An additional capacitance C is constituted by the gate insulating film 47 and the capacitor electrode 49 made of the other second polycrystalline silicon layer.
In this case, a ground potential is applied to the capacitor electrode 49, forming a so-called signal storage capacitor (additional capacitance) C for liquid crystal (see the shaded area in FIG. 21).

[0007]

[Problems to be Solved by the Invention] Incidentally, with the recent increase in the resolution of picture elements, it has become necessary to reduce the area occupied by one picture element. Under these circumstances, the current 0.
In a 7-inch liquid crystal display device with 77,000 pixels, the area occupied by each additional capacitor is 230 μm2, which is
This area is absolutely necessary for good liquid crystal display.

However, in the conventional liquid crystal display device, an oxide film (gate insulating film 47) is formed on the first polycrystalline silicon layer (active layer 43), and two layers are formed on the gate insulating film 47. A second polycrystalline silicon layer (capacitor electrode 49) is formed, and these active layers 43 and gate insulating films 4
7 and the capacitor electrode 49, it is difficult to cope with an increase in the value of the additional capacitance or a reduction in the area occupied by the additional capacitance. The only way to do so was to reduce the area occupied by the picture element electrodes. However, reducing the area occupied by the picture element electrode 42 leads to deterioration of the sensitivity of the liquid crystal display, and there is a problem that there is a limit to the above-mentioned increase in resolution.

The present invention has been made in view of the above-mentioned problems, and its purpose is to increase the additional capacitance, and to realize higher resolution and improved sensitivity of a liquid crystal display. The object of the present invention is to provide a liquid crystal display device that can perform the following functions.

0010

[Means for Solving the Problems] The present invention provides a liquid crystal display device having a picture element electrode 2 separated for each picture element and a wiring area between each picture element electrode 2, in which a A first additional capacitance C1 formed by the second semiconductor layer 3 and the second wiring layer 11, and a transparent electrode film 13 used for forming the picture element electrode 2.
A second additional capacitance C2 is formed by the second wiring layer 11, and the first and second additional capacitances C1 and C2 are formed.
are configured by connecting them in parallel.

[0011]

[Operation] According to the structure of the present invention described above, the first additional capacitance C1 is created by the first semiconductor layer 3 and the second wiring layer 11.
Then, a second additional capacitor C2 is formed by the transparent electrode film 13 used for forming the picture element electrode 2 and the second wiring layer 11, and the first and second additional capacitors C1 and C2 are connected in parallel. This makes it possible to more than double the additional capacitance (functioning as a signal storage capacitor) per unit occupied area.

[0012] Therefore, even if the area occupied by one picture element is reduced with the increase in resolution, there is no need to reduce the size of the picture element electrode 2, and it is possible to improve the resolution and sensitivity of the liquid crystal display. It can be realized. Furthermore, since the additional capacitance is increased, the image holding ability of the liquid crystal is improved, and a high-quality liquid crystal display image can be obtained.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 20. FIG. 1 shows the main parts (picture elements) of an active matrix display type liquid crystal display device according to this embodiment.
2 is a plan view thereof, and FIG. 2 is a sectional view thereof. Here, the left half of FIG. 2 is a cross-sectional view taken along the line A--A in the region (2) of FIG. 1, and the right half is a cross-sectional view taken along the line B--B in the region (2).

In this liquid crystal display device, picture element electrodes 2 made of transparent electrode films (for example, ITO films) are formed on a quartz substrate 1 corresponding to each picture element, and spaces for forming wiring between these picture element electrodes 2 are formed. A first polycrystalline silicon layer, which is the active layer 3 of the TFT, is formed, and the picture element electrode 2 is connected to the drain region D of this active layer 3 via a contact hole 4, and the source of the active layer 3 is connected to the drain region D of the active layer 3. A that configures the signal line L in the area S
An l.Si electrode 5 is connected via a contact hole 6. Further, the gate electrode 7 of the TFT is formed from one of the second polycrystalline silicon layers, and constitutes a selection line W. In FIG. 2, 8 indicates an interlayer insulating film, and 9 indicates a gate insulating film. Further, 10 indicates a passivation film made of a SiN film or the like.

In addition, in the region (1) in FIG. 1 and the right half of FIG. In this case, a ground potential is applied to the capacitor electrode, forming a so-called liquid crystal signal storage capacitor (first additional capacitor) C1.

In this example, an insulating film 12 for additional capacitance is formed on the capacitor electrode 11, and a capacitor electrode 13 made of a transparent electrode film separated from the picture element electrode 2 is further formed on the insulating film 12. Formed and composed. At this time, the capacitor electrode 11, the additional capacitor insulating film 12, and the capacitor electrode 13 constitute a second additional capacitor C2. Then, by connecting the capacitor electrode 13 to the active layer 3 through the contact hole 14, the first
The additional capacitor C1 and the second additional capacitor C2 are connected in parallel (see the equivalent circuit diagram in FIG. 10). Therefore, the total additional capacitance according to this example is more than twice as large as the first additional capacitance C1.

As described above, according to this example, the first additional capacitance C1 formed by the active layer 3 and the capacitor electrode 11 and the transparent electrode film (capacitor electrode) used for forming the picture element electrode 2 are
13 and the second additional capacitance C2 by the capacitor electrode 11
furthermore, first and second additional capacitances C1 and C
2 are connected in parallel through the opening 14, it is possible to increase the additional capacitance (functioning as a signal storage capacitor) per unit occupied area. Currently 1
The capacitance for the picture element is 120 fF, and when converted to the occupied area, it becomes 230 μm 2 as shown in FIG. 3 (see point A). However, in the case of this example, in order to obtain the same capacity, the occupied area is less than half of that, that is, 110 μm 2 (see point B).

Therefore, even if the area occupied by one picture element is reduced due to higher resolution, there is no need to reduce the size of the picture element electrode 2, and it is possible to improve the resolution and sensitivity of the liquid crystal display. It can be realized. This leads to achieving a high resolution of, for example, 107,000 pixels while preventing a decrease in additional capacity and a decrease in aperture ratio. Also,
Since the additional capacitance is increased, the image holding ability of the liquid crystal is improved, and a high-quality liquid crystal display image can be obtained.

Next, a method for manufacturing the liquid crystal display device according to the present example will be explained with reference to FIGS. 4 to 9. Furthermore, Figures 1 and 2
Items that correspond to the above are given the same reference numerals.

First, as shown in FIG. 4A, a polycrystalline silicon layer 21 with a thickness of about 800 Å is deposited on a quartz substrate 1 by low pressure CVD.
Formed by method D. After that, silicon (Si) is implanted at an energy of about 30 KeV and a dose of about 1 x 1015 cm-2.
and implantation energy approximately 50KeV, implantation amount approximately 1×1015
After implanting into the polycrystalline silicon layer 21 at cm-2, the first polycrystalline silicon layer 21 with good crystallinity is obtained by solid phase growth at a temperature of about 620°C.

Next, as shown in FIG. 4B, after patterning the first polycrystalline silicon layer 21 to form an active layer 3, thermal oxidation is applied to the surface of the active layer 3 to a thickness of about 80 mm.
A thermal oxide film of 0 Å, that is, a gate insulating film 9 is formed.

Next, as shown in FIG. 4C, the active layer 3
After forming a resist mask 22 having openings at locations corresponding to portions that will become capacitors, N-type impurities such as arsenic (As) are implanted into the active layer 3 through the openings of the resist mask 22 at an energy of approximately 30 keV. Injection amount approx. 5
Ion implantation is performed at ×1014 cm-2.

Next, as shown in FIG. 5A, after peeling off the resist mask 22, a 2-layer film with a thickness of about 3500 Å is applied to the entire surface.
The second polycrystalline silicon layer 23 is formed by low pressure CVD. After that, after forming PSG (phosphorus silicate glass) 24 on the second polycrystalline silicon layer (indicated by a two-dot chain line), due to the diffusion of phosphorus (P) from the PSG 24,
The lower polycrystalline silicon layer 23 is lowered in resistance (made conductive).

Next, as shown in FIG. 5B, the second polycrystalline silicon layer 23 is patterned by plasma etching using a mixed gas of CF4 gas and O2 gas (mixture ratio CF4:O2 = 95:5). By doing so,
A gate electrode 7 (selection line W) and a capacitor electrode 11 are formed using a second polycrystalline silicon layer 23.

Next, as shown in FIG. 5C, using the gate electrode 7 as a mask, an LDD (lightweight diode) is formed in the active layer 3.
The LDD region 25 is formed in the active layer 3 by ion-implanting an impurity for forming a doped drain, such as arsenic (As), at an implantation energy of approximately 160 keV and an implantation amount of approximately 1×10 13 cm −2 . Note that in the active layer 3, the region below the gate electrode 7 is a channel region C.
Configure.

Next, as shown in FIG. 6A, the gate electrode 7
After forming a resist mask 26 that covers the active layer with a predetermined thickness, an impurity for forming an N channel, such as arsenic (As), is implanted into the active layer 3 using the resist mask 26 as a mask at an energy of about 140 keV and an implantation amount of 2×10 15 cm. −
By performing ion implantation in step 2, an N-channel drain region D and source region S are formed in the active layer 3.

Next, as shown in FIG. 6B, after forming a resist mask 27 in the portion related to the N channel, impurities for forming the P channel, such as boron (B), are applied to the portion of the peripheral circuit other than the N channel. ) at an implantation energy of approximately 30 keV and an implantation amount of 2.times.10.sup.15 cm.sup.-2 to form a P channel impurity diffusion region in a portion other than the N channel.

Next, as shown in FIG. 6C, after peeling off the resist mask 27, an interlayer insulating film 8 made of PSG is removed.
is formed by a low pressure CVD method.

Next, as shown in FIG. 7A, a contact hole 28 is formed in a portion of the interlayer insulating film 8 corresponding to the capacitor electrode 11.

Next, as shown in FIG. 7B, thermal oxidation is performed to form a thermal oxide film, ie, an additional capacitance insulating film 12, about 800 Å thick on the surface of the capacitor electrode 11 exposed from the contact hole 28.

Next, as shown in FIG. 7C, contact holes 4 and 14 are formed in the drain region D of the active layer 3 and the portion that will become the storage node of the capacitor, respectively. In this case, it is formed by wet etching using a mixed solution of HF solution and NH4F solution.

Next, as shown in FIG. 8A, a transparent electrode film (ITO film) 29 with a thickness of about 1400 Å is coated on the entire surface at a temperature of about 40 Å.
The film is formed at 0°C.

Next, as shown in FIG. 8B, the transparent electrode film 29 is heated with HCl gas, H2O (water vapor) and HNO3.
Mixed gas with gas (mixture ratio HCl:H2 O:HNO3
= 300:300:50) by patterning with plasma etching treatment, the transparent electrode film 2
9, the picture element electrode 2 and the capacitor electrode 13 are formed. At this time, the picture element electrode 2 is connected to the drain region D of the active layer 3 through the contact hole 4, and the capacitor electrode 13 is connected to the storage node of the active layer 3 through the contact hole 14.

Next, as shown in FIG. 8C, a contact hole 6 is formed in the source region S of the active layer 3. In this case, it is formed by wet etching using a mixed solution of HF solution and NH4F solution.

Next, as shown in FIG. 9A, an Al/Si film 30 having a thickness of approximately 6000 Å is formed over the entire surface by sputtering.

Next, as shown in FIG. 9B, the above Al.S.
The i-film 30 is heated using a mixed gas of H3 PO4 gas and H2 O (water vapor) (mixing ratio H3 PO4 :H2 O=2:1).
By patterning using the plasma etching process according to 0), an Al/Si electrode 5 (signal line L) of the Al/Si film 30 is formed. At this time, the Al.Si electrode 5 is connected to the source region S of the active layer 3 through the contact hole 6.

Next, as shown in FIG. 9C, a passivation film (SiN film) 10 having a thickness of about 4000 Å is formed on the entire surface by plasma CVD to obtain a liquid crystal display device according to this example. After this, the process of patterning the passivation film 10 and forming pads continues, but the description thereof will be omitted here.

According to this manufacturing method, the first additional capacitance C1 formed by the first polycrystalline silicon layer (active layer 3) and the second polycrystalline silicon layer (capacitor electrode 11), and the pixel electrode 2 Transparent electrode film (capacitor electrode 1) used for formation of
3) and the second polycrystalline silicon layer (capacitor electrode 11
) can easily form the second additional capacitor C2. Furthermore, the thinning of the additional capacitor insulating film 12 on the capacitor electrode 11, which is a necessary condition for forming the second additional capacitor C2, is equivalent to the thickness of the gate insulating film 9 on the active layer 3 (700~ 800 Å) can be easily realized.

In the above embodiment, when forming the additional capacitance insulating film 12, a contact hole 28 is formed in the interlayer insulating film 8, as shown in FIG. After forming, capacitor electrode 1 is formed by thermal oxidation.
In addition, as shown in FIG. 12, after the interlayer insulating film 8 is thinned by etch-back treatment or the like, the additional capacitor insulating film 12 is formed on the surface of the additional capacitor insulating film 12. may be formed by a CVD method or the like. In this case, since the height difference of the contact hole 28 can be lowered, leakage, step breakage, etc. at the height difference portion can be prevented.

In addition, as shown in FIG. 13, after forming an additional capacitance insulating film 12 on the capacitor electrode 11 by CVD method or the like, an interlayer insulating film 8 is formed on the entire surface, and then a layer corresponding to the capacitor electrode 11 is formed. The capacitor electrode 13 made of a transparent electrode film may be formed after the contact hole 28 penetrating the interlayer insulating film 8 is formed in the portion where the capacitor electrode 13 is made of a transparent electrode film. However, in this case, when forming the contact hole 28,
The lower layer additional capacitance insulating film 12 is also etched away, and the lower layer capacitor electrode 11 and gate electrode (this figure 1) are removed by etching.
3) may also be removed by etching, so if possible, as shown in another embodiment of FIG. It is preferable to intervene.

Next, a method for manufacturing a liquid crystal display device according to another embodiment shown in FIG. 14 will be described with reference to FIGS. 15 to 20. Components corresponding to those in FIGS. 4 to 9 are designated by the same reference numerals. Furthermore, since this manufacturing method involves the same steps from FIG. 4A to FIG. 4C, the explanation will be given sequentially starting from the step following the step shown in FIG. 4C.

First, as shown in FIG. 15A, a Si film with a thickness of about 300 Å is deposited on the thermal oxide film 32 formed on the active layer 3.
After forming the N film 31 by low pressure CVD, thermal oxidation is performed to form a thermal oxide film (SiO2 film) 33 on the SiN film 31. In this case, the thermal oxide film 32 and the SiN film 31
The gate insulating film 9 is composed of the thermal oxide film 33 and the thermal oxide film 33 .

Next, as shown in FIG. 15B, a second polycrystalline silicon layer 23 with a thickness of about 3500 Å is deposited on the entire surface by vacuum C.
Formed by VD method. After that, after forming a PSG 24 on the second polycrystalline silicon layer 23 (indicated by a two-dot chain line)
, Diffusion of phosphorus (P) from the PSG 24 lowers the resistance of the underlying polycrystalline silicon layer 23 (makes it conductive).

Next, as shown in FIG. 15C, the second polycrystalline silicon layer 23 is patterned by plasma etching using a mixed gas of CF4 gas and O2 gas (mixture ratio CF4:O2 = 95:5). By doing so, the gate electrode 7 (
A selection line W) and a capacitor electrode 11 are formed. At this time, the lower layer thermal oxide film 33 and SiN film 31 are patterned in the same way as the upper layer polycrystalline silicon layer 23, but in this case, they are patterned to be somewhat wider than the upper layer gate electrode 7 and capacitor electrode 11. .

Thereafter, using the gate electrode 7 as a mask, an impurity for forming an LDD, such as arsenic (As), is implanted into the active layer 3 at an energy of about 160 keV and a dose of about 1×10 13 c.
L is implanted into the active layer 3 by ion implantation at m-2.
A DD region 25 is formed. Incidentally, the region under the gate electrode 7 in the active layer 3 constitutes a channel region C.

Next, as shown in FIG. 16A, thermal oxidation is performed to form a thermal oxide film 34 with a thickness of about 500 Å on each surface of the gate electrode 7 and capacitor electrode 11.

Next, as shown in FIG. 16B, a SiN film 31 with a thickness of about 300 Å is formed on the entire surface by low pressure CVD, and then thermal oxidation is performed to form a thermal oxide film 35 on the SiN film 31. .

Next, as shown in FIG. 16C, the SiN
By patterning the film 31 using CF4 gas plasma etching, SiN is formed on each thermal oxide film 34.
The film 31 and the thermal oxide film 35 are left.

Next, as shown in FIG. 17A, after forming a resist mask 36 to cover the gate electrode 7, an impurity for forming an N channel, for example, is injected into the active layer 3 through the resist mask 36. By ion-implanting arsenic (As) at an implantation energy of approximately 140 keV and an implantation amount of 2×10 15 cm −2 , an N-channel drain region D and source region S are formed in the active layer 3 .

Next, as shown in FIG. 17B, after forming a resist mask 37 in a portion related to an N channel, impurities for forming a P channel, such as boron (B ) at an implantation energy of approximately 30 keV and an implantation amount of 2.times.10.sup.15 cm.sup.-2 to form a P channel impurity diffusion region in a portion other than the N channel.

Next, as shown in FIG. 17C, after the resist mask 37 is peeled off, an interlayer insulating film 8 made of PSG is formed by low pressure CVD.

Next, as shown in FIG. 18A, contact holes 28 and 28 are formed in the portions of the interlayer insulating film 8 that correspond to the capacitor electrodes 11 and the portions that will become the drain region D and the capacitor storage node of the active layer 3, respectively. 4 and 14
form. In this case, it is formed by wet etching using a mixed solution of HF solution and NH4F solution. At this time, the thermal oxide film 35 on the SiN film 31 in the contact hole 28 is also removed by etching. However, since the surface of the SiN film 31 is oxidized in the step of FIG. 15A, the SiN film 31 becomes dense and the surface becomes oxygen (O2).
2) Since the termination is performed, the quality of the SiN film 31 is improved. The additional capacitance insulating film 12 is constituted by this SiN film and the thermal oxide film 34 below it.

Next, as shown in FIG. 18B, a transparent electrode film (ITO film) 29 with a thickness of about 1400 Å is coated on the entire surface at a temperature of about 4 Å.
The film is formed at 00°C.

Next, as shown in FIG. 18C, the transparent electrode film 29 is heated with HCl gas, H2O (water vapor) and HNO3.
Mixed gas with gas (mixture ratio HCl:H2O:HNO
3 = 300:300:50), the picture element electrode 2 and the capacitor electrode 13 are formed by the transparent electrode film 29. At this time, the picture element electrode 2 is connected to the drain region D of the active layer 3 through the contact hole 4, and the capacitor electrode 13 is connected to the storage node of the active layer 3 through the contact hole 14.

Next, as shown in FIG. 19A, a contact hole 6 is formed in the source region S of the active layer 3. In this case, it is formed by wet etching using a mixed solution of HF solution and NH4F solution.

Next, as shown in FIG. 19B, an Al.Si film 30 having a thickness of about 6000 Å is formed over the entire surface by sputtering.

Next, as shown in FIG. 19C, the above Al.
The Si film 30 is exposed to H3 PO4 gas and H2 O (water vapor).
(mixture ratio H3 PO4 :H2 O=2:
10), the Al/Si electrode 5 (signal line L) is formed from the Al/Si film 30 by patterning using the plasma etching process. At this time, the Al.Si electrode 5 is connected to the source region S of the active layer 3 through the contact hole 6.

Next, as shown in FIG. 20, a passivation film (SiN film) 10 having a thickness of about 4000 Å is formed on the entire surface by plasma CVD to obtain a liquid crystal display device according to this example. After this, the process of patterning the passivation film 10 and forming pads continues, but the description thereof will be omitted here.

According to this manufacturing method, similarly to the manufacturing method according to the first embodiment, the first polycrystalline silicon layer (active layer 3) and the second polycrystalline silicon layer (capacitor electrode 11) A first additional capacitance C1 formed by C1 and a second capacitance C1 formed by a transparent electrode film (capacitor electrode 13) used for forming the picture element electrode 2 and a second layer of polycrystalline silicon layer (capacitor electrode 11)
The additional capacitance C2 can be easily formed. In particular, in this case, the gate insulating film 9 and the additional capacitance insulating film 12
Since the SiN film 31 having a high dielectric constant is interposed between the capacitor and the capacitor, the capacitance value of the additional capacitor is improved, and even if the area occupied by the additional capacitor is reduced, a desired capacitance value can be obtained. This means that the resolution of the liquid crystal display device can be increased without reducing the aperture ratio. Moreover, since a desired capacitance value can be obtained even if the gate insulating film 9 and the additional capacitance insulating film 12 are made thicker, the withstand voltage can be improved.

[0060]

According to the liquid crystal display device according to the present invention, it is possible to increase the additional capacity, and it is possible to realize higher resolution and improved sensitivity of the liquid crystal display.

[Brief explanation of drawings]

FIG. 1 is a plan view showing main parts (picture elements) of a liquid crystal display device according to an embodiment.

FIG. 2 is a cross-sectional view showing main parts (picture elements) of the liquid crystal display device according to the present example. The left half is a sectional view taken along line A-A in FIG. The right half is a sectional view taken along line B-B in FIG.

FIG. 3 is a characteristic diagram showing reduction in the area occupied by additional capacitance in this embodiment.

FIG. 4 is a process diagram (part 1) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 5 is a process diagram (part 2) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 6 is a process diagram (part 3) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 7 is a process diagram (part 4) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 8 is a process diagram (part 5) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 9 is a process diagram (part 6) showing the method for manufacturing the liquid crystal display device according to the present example.

FIG. 10 is an equivalent circuit diagram showing the configuration of a picture element of this example.

FIG. 11 is a sectional view taken along line CC in FIG. 2;

FIG. 12 is a sectional view showing a first modification of this embodiment.

FIG. 13 is a sectional view showing a second modification of this embodiment.

FIG. 14 is a cross-sectional view showing a liquid crystal display device according to another example.

FIG. 15 is a process diagram (Part 1) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 16 is a process diagram (part 2) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 17 is a process diagram (part 3) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 18 is a process diagram (part 4) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 19 is a process diagram (part 5) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 20 is a process diagram (part 6) showing a method for manufacturing a liquid crystal display device according to another example.

FIG. 21 is a plan view showing main parts (picture elements) of a conventional liquid crystal display device.

FIG. 22 is a cross-sectional view showing main parts (picture elements) of a conventional liquid crystal display device. The left half is a sectional view taken along line A-A in FIG. 21. The right half is a sectional view taken along line BB in FIG. 21.

[Explanation of symbols]

1 Quartz substrate 2 Pixel electrode 3 Active layer (first polycrystalline silicon layer) 4, 6, 1
4 Contact hole 5 Al/Si electrode (signal line L) 7 Gate electrode (second polycrystalline silicon layer) 8
Interlayer insulating film 9 Gate insulating film 10 Passivation film 11 Capacitor electrode (second polycrystalline silicon layer)
12 Insulating film for additional capacitance 13 Capacitor electrode (transparent electrode film) C1 1st
Additional capacitance C2 Second additional capacitance

Claims (1)

[Claims] Claim 1: A liquid crystal display device having a picture element electrode separated for each picture element and a wiring region between each picture element electrode,
On the wiring area, a first additional capacitance is formed by the first semiconductor layer and the second wiring layer, and a second additional capacitance is formed by the transparent electrode film used for forming the picture element electrode and the second wiring layer. an additional capacitor, and the first and second additional capacitors are connected in parallel.