JPH04330782A - Fine semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make possible an element isolation as designed in a fine isolation width as well as to provide a fine semiconductor device, which has a large punch through resistance and a large hot carrier resistance, and a manufacturing method of the device. CONSTITUTION:A channel layer 2 is formed in a silicon substrate 1 and an insulator layer 14, which begins in the above channel layer and ends in the above silicon substrate, is provided between source and drain regions 6 and 7, which are formed in this channel layer, and at the same time, the insulator layer is provided between the drain region of a first element and the source region of a second element.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a semiconductor device and its manufacturing method, and particularly to the short channel effect, narrow channel effect, and hot carrier characteristics of MOSLSI which require channel length, channel width, and separation width of 0.5 μm or less. The present invention relates to a fine semiconductor device that suppresses deterioration, improves isolation breakdown voltage, and prevents substrate inversion under an isolation insulating film, and a method for manufacturing the same.

0002

2. Description of the Related Art Conventionally, in order to suppress the short channel effect that accompanies miniaturization of devices, techniques have been used to increase the concentration of the channel layer, reduce the junction depth, and thin the gate insulating film. However, with this method, a reduction in junction breakdown voltage due to avalanche breakdown, an increase in the substrate effect, a deterioration in characteristics due to hot carriers due to electric field concentration, and a decrease in mobility due to an increase in the electric field in the direction perpendicular to the gate insulating film. Due to the increase in leakage current due to tunneling between bands, the power supply voltage is limited and the characteristics themselves deteriorate, making it difficult to obtain a high-performance semiconductor device. Furthermore,
There were also limits to miniaturization.

FIG. 14 is a sectional view showing the structure of such a conventional fine semiconductor device, such as a MOSFET. In the figure, 1 is a substrate such as a P-type <001> silicon substrate, 2
For example, boron ions are irradiated from the surface of the silicon substrate 1 at 2×1012 to 2×1013/2 at 30 to 70 keV.
This is a P-type channel layer formed by implanting cm2, and its peak concentration position is indicated by reference numeral 2a. 3
4 is a gate insulating film formed on a part of this channel layer 2, for example, a silicon insulating film with a thickness of 50 to 100 Å, and 4 is a gate electrode formed on a part of this gate insulating film 3, for example, a film thickness of 2000 to 100 Å. It is made of N-type polycrystalline silicon with a thickness of 4000 Å or N-type polycrystalline silicon whose surface has been transformed into a silicon compound of a high-melting point metal such as titanium, molybdenum, or tungsten, that is, a high-melting point metal silicide film. 5 is formed on the sides of this gate electrode 4 and the remainder of the gate insulating film 3, and is made of an insulating material such as a silicon oxide film and has a width of 0.05 mm.
~0.15 μm sidewall, 6, phosphorus or arsenic is applied to the channel layer 2 from its surface at an energy of 10 to 50 keV at 2×10 13 /cm 2 to 2×10 14 /
cm2 implant, and consists of a relatively low concentration of N-type impurities, and 7 is for example 1×10 at an energy of 30-50 keV.
These are high-concentration source/drain regions formed by implanting arsenic of 15/cm2 or more and made of high-concentration N-type impurities. Note that the surface of this highly doped source/drain region 7 may be made of refractory metal silicide, similarly to the gate electrode 4.

A conventional MOSF configured as described above
In ET, the channel layer 2 and gate insulating film 3 are
It operates to appropriately set a threshold voltage for the gate electrode 4 having a certain work function and to suppress through current due to punch-through. The sidewall 5 serves to appropriately set the length of the lightly doped source/drain region 6 and to prevent the high melting point silicide films of the gate electrode 4 and the highly doped source/drain 7 from being shot together. The low concentration source/drain region 6 functions to suppress electron impact, improve breakdown voltage between the source and drain, and suppress deterioration of device characteristics due to hot carriers. The silicon substrate 1, gate electrode 4, and heavily doped source/drain region 7 each act as an electrode (not shown) or an extension thereof.

FIGS. 15 and 16 are cross-sectional views showing a structure for separating the conventional MOSFET shown in FIG. 14. In FIG. 15, 1A is a silicon substrate after a channel layer 2 is formed on the silicon substrate 1 shown in FIG. 14, and 7 is a first or second MOS formed on this silicon substrate 1A.
High concentration source/drain region of FET, 8 is the first MO
In order to isolate the SFET and the second MOSFET, a P-type impurity region 9 is implanted into the silicon substrate 1A directly under an isolation insulating film, which will be described later.
An isolation insulating film is formed directly above the isolation insulating film 9, and 10 is a wiring layer formed on the isolation insulating film 9. Note that the isolation insulating film 9 functions to isolate the elements and to suppress charge reversal caused by the potential of the wiring layer 10 formed on the isolation insulating film 9. The isolation impurity region 8 acts to suppress the extension of the depletion layer from the active layer of the first MOSFET and the second MOSFET.

FIG. 17 is a cross-sectional view illustrating a method for forming such an isolation structure in the order of steps. As shown in FIG. Boron 5x with energy
1012~5x1013/cm2 and annealed at a high temperature of 1000℃ or higher for several hours to form 1x1016~
A silicon substrate 1A having a uniform impurity concentration profile of 1×10 17 /cm 2 is prepared. Next, B in Figure 17
As shown in the figure, after forming a silicon oxide film 11, an oxidation-resistant film and a silicon nitride film 12 as an etching stopper, and a photoresist 13 for the silicon substrate pad, patterning is performed using photolithography to form a photoresist 13 and silicon. Nitride film 12, silicon oxide film 11
remove part of Next, as shown in FIG. 17C, isolation boron is implanted into the silicon substrate 1A to form isolation impurity regions 8. Furthermore, as shown in FIG. 17D, the photoresist 13 is removed and then oxidized to form the isolation oxide film 9. Thereafter, silicon nitride film 12 and silicon oxide film 11 are removed. In this way, the elements are separated by the isolation insulating film 9.

[0007] This isolation structure may be formed by the method described with reference to FIG. A in FIG. 18 also shows A in FIG. 17.
A silicon substrate 1A similar to the above is prepared. Next, B in Figure 18
As shown in FIG.
, after forming photoresist 13, photoresist 1
3 is patterned and a part of it is removed. next,
As shown in FIG. 18C, the silicon nitride film 12, silicon oxide film 11, and silicon substrate 1A are selectively etched using the patterned photoresist 13 as a mask, and boron is implanted at an isolation of 1 x 1013/cm2. Then, an isolation impurity region 8 is formed. Furthermore, Figure 1
As shown in 8D, after removing the photoresist 13, a thin layer of oxidation is performed and an isolation insulating film 9 is deposited by low pressure CVD.
Etch back and embed in the hole. In this way a separated structure is obtained.

Next, a conventional MOS is installed in the separated active layer.
A method of manufacturing the FET will be described with reference to FIGS. 19 and 20. FIG. 19A is a cross-sectional view showing the active layer of the silicon substrate 1A separated by the method described with respect to FIG. 17 or 18, for example. In Fig. 19B, boron is applied to this active layer at 5 x 1012/cm2 at 40 keV to 50 keV.
~1×1013/cm2 was implanted to form a channel layer 2. After forming a gate insulating film 3 of 60 to 100 Å on this channel layer 2, a polycrystalline silicon layer of 200 to 3500 Å was patterned by photolithography. FIG. 4 is a cross-sectional view showing the gate electrode 4 obtained. C in Figure 19 shows that this sample is 1×1013/1 with an acceleration energy of about 30 keV
It is a cross-sectional view of a low concentration source/drain region 6 formed by implanting phosphorus at a concentration of cm 2 to 1×10 14 /cm 2 . Figure 2
0A is a cross-sectional view showing the state after a silicon oxide film of 1000 to 2500 Å is deposited thereon by low pressure CVD, and anisotropic etching is performed using a reactive ion etching apparatus to form sidewalls. Next, as shown in Figure 20B, 1 × 10
Arsenic of 15/cm2 or more is implanted to form source/drain regions. After that, perform wiring (not shown),
Complete MOSFET.

[0009]

However, the conventional fine semiconductor device constructed as described above has the following problems. In the isolation structures shown in FIGS. 15 and 16, when forming the element isolation insulating film 9, oxygen is also supplied to the edge portion of the oxidation-resistant film and oxidized. Silicon nitride film 12 shown in C
In other words, the dimensions of the inter-element isolation insulating film 9 are about 0.2 μm shorter than the dimensions specified in , and therefore the width is 0.
．． It is difficult to obtain an active layer of 5 μm or less.

Furthermore, in the separation structure shown in FIG. 16, the separation width is determined by the processing accuracy, so the separation width is 0.3μ
The separation width of m is the limit, and the LPCVD at the time of embedding
Since it becomes difficult for the reaction gas to enter the hole, a cavity is formed inside.

Furthermore, since the conventional MOSFET is constructed as shown in FIG. 14, in order to prevent punch-through as described above, the substrate concentration must be increased, the film thickness of the gate insulating film must be reduced, and the junction had to be made shallower. Therefore, as the withstand voltage between the source and drain decreases, the hot carrier resistance decreases, and interband tunneling leakage becomes noticeable.

The present invention has been made to solve these problems, and provides a semiconductor device that enables separation as designed with a fine separation width, and has high punch-through resistance and hot carrier resistance, and its manufacture. The purpose is to obtain a method.

[0013]

[Means for Solving the Problems] To achieve this object, a microscopic semiconductor device according to the present invention has a structure that starts in a channel layer between a source region and a drain region, ends in a substrate, and has an embedded drain region. An insulating layer having a depth of at least 0.2 μm or more equal to the drain junction depth is provided in contact with one of the source/drain regions of the first element and the other of the source/drain regions of the second element. An insulating layer having a depth of 0.2 μm or more and a width of 0.1 μm or less is also provided between them.

The method for manufacturing a microscopic semiconductor device according to the present invention also includes the steps of: forming a step on a semiconductor substrate having an insulating layer formed on its surface; and forming an insulating film on at least a sidewall of the stepped portion. burying a semiconductor layer below the step portion.

In the present invention, punch-through paths are eliminated, the junction depth can be increased, and the gate insulating film can also be made thicker.

Further, according to the present invention, a fine semiconductor device can be manufactured while separating as designed with a fine separation width and a deep separation depth.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing a MOSFET portion in an embodiment of a microscopic semiconductor device according to the present invention. In the figure, 1, 2, 2a, 3 to 7 are the same as those described for the conventional device. Note that 7A is a highly doped drain region buried deep in the silicon substrate 1, and 14 is an insulating layer formed from the channel layer 2 to the silicon substrate 1 between the source region and the drain region. is 0.2 μm or more and is in contact with the buried heavily doped drain region and is at least equal to its drain junction depth.

FIG. 2 is a sectional view showing a separation structure in one embodiment of the present invention. In the figure, 1, 2, 2a, 7, 9
, 10 are the same as those in the conventional device. Reference numeral 15 denotes an insulating layer formed between elements to prevent leakage between the elements, and is an insulating layer formed between the active layer of the first MOSFET, here one of the high concentration source/drain regions, and the high concentration source of the second MOSFET. /depth 0.2μ between the other drain regions
It exists with a width of 0.1 μm or more and a width of 0.1 μm or more.

Next, an embodiment of the method for manufacturing a fine semiconductor device according to the present invention will be described with reference to cross-sectional views shown in FIGS. 3 to 7. First, to explain the separation manufacturing, as shown in FIG. 3A, a P-type <001> silicon substrate 1 is prepared. Next, on this silicon substrate 1, for example, 1000 Å-6000 Å
An isolation insulating film 9 made of a silicon oxide film with a thickness of Å is formed. The isolation insulating film 9 is applied to a region where the isolation width is relatively large, such as the periphery of the array. Next, a silicon nitride film 12 as an oxidation-resistant film and a photoresist 13 are successively formed on the isolation insulating film 9, and the silicon nitride film 12 and the isolation insulating film 9 are patterned using the photoresist 13 as a mask. It will be as shown. Next, after removing the photoresist 13 on the silicon nitride film 12 and forming a new photoresist 13 on a part of the silicon substrate 1, this photoresist 13 and the silicon nitride film 12 are removed.
By etching the silicon substrate 1 to a depth of, for example, 2000 Å or more using the isolation insulating film 9 as a mask, the structure shown in FIG. 3C is obtained. Next, as shown in FIG. 4A, after the photoresist 13 is removed, it is oxidized to a thickness of 50 Å or more to form an insulating layer 15 on at least the sidewalls. Furthermore, as shown in FIG. 4B, the insulating layer 15 on the bottom of the recess is removed by reactive ion etching or the like. After forming an epitaxial silicon layer 16 using a selective epitaxial technique in which silicon is deposited by reacting hydrogen chloride gas and a gas such as silane at an appropriate mixing ratio in a reaction tube (not shown), boron is implanted. Channel layer 2 is then formed.

Next, the MOSFET portion will be explained. Epitaxial silicon layer 16 as shown in FIG.
Or a sacrificial oxide film 17 of approximately 200 Å on the silicon substrate 1.
After forming, this sacrificial oxide film 17 and epitaxial silicon layer 16 or silicon substrate 1 are etched by photolithography. The depth of this etching is arbitrary, but
It is desirable that the depth be shallower than that shown in FIG. 3C. After that, after going through the same steps as A and B in FIG. 4, an insulating layer is formed between the source region and the drain region as shown in B in FIG.
4 is formed and an epitaxial silicon layer 16 is formed.
A is selectively grown. Next, as shown in FIG.
A gate insulating film 3 made of a silicon oxide film with a thickness of 20 Å is formed, and a gate electrode 4 made of polycrystalline silicon with a thickness of about 3000 Å is patterned. Here, after removing the sacrificial oxide film 17 and before forming the gate electrode 4, the channel layer 2 is formed. Next, as shown in FIG. 6A, phosphorus is implanted at a dose of 1013 to 1014/cm2 at an acceleration energy of 30 keV while using the gate electrode 4 as a mask.
Low concentration source/drain regions 6 are formed. Furthermore, LP
CVD silicon oxide film (not shown) with a thickness of 500 to 150
After depositing 0 Å, anisotropic etching is performed using reactive ion etching to form the side hole 5 shown in FIG. 6B.
form. Next, as shown in FIG. 6C, 50 keV
Arsenic is implanted at an amount of 1×10 15 /cm 2 or more with an acceleration energy of 1×10 15 /cm 2 or more to form highly doped source/drain regions 7. After that, by forming an interlayer insulating film and wiring, the MOSFE
T is obtained.

In the semiconductor device according to the above embodiment, the high concentration source/drain region 7 was formed by only one arsenic implantation, but as shown in FIG. The deeply buried heavily doped drain region 7A may be formed by doping with an impurity such as.

FIG. 8 is a cross-sectional view showing a fine semiconductor device in which a channel layer exists in a direction not parallel to a silicon substrate, and a method for manufacturing the fine semiconductor device of FIG. 8 will be explained with reference to FIG. First, an insulating layer 14 is deposited on the surface of the silicon substrate 1 to obtain the structure shown in FIG. 9A. Next, as shown in FIG. 9B, the insulating layer 14 and the silicon substrate 1 are etched by photolithography. Next, as shown in FIG. 9C, an amorphous silicon layer 18 is deposited. This amorphous silicon layer 18 becomes an epitaxial layer by performing solid phase epitaxial growth later. next,
As shown in FIG. 9D, a gate insulating film 3 is deposited, a gate electrode 4 made of a polycrystalline silicon layer is deposited, and then anisotropic etching is performed using reactive ion etching to form sidewalls. Furthermore, as shown in FIG. 9E, by forming lightly doped source/drain regions 6 and heavily doped source/drain regions 7, the structure shown in FIG. 8 is obtained.

[0023] Furthermore, as shown in FIGS. 10A and 10B,
After forming the gate electrode 4 and then the sidewalls 5,
The highly concentrated source/drain regions 7 or the insulating layer 14 may be provided by etching and further etching both the source side and the drain side by self-alignment. Furthermore, the structure shown in FIG. 11A was obtained by using a structure similar to that in FIG. 10B on a silicon substrate 1 on which two or more barriers were formed; It is possible to manufacture a MOSFET having a characteristic that holes escape into the silicon substrate 1 only at a characteristic potential as the potential increases. Therefore, a memory cell can also be formed using this hole as an information carrier. Note that 19 is a layer made of a material with a large band gap, such as silicon carbide.

Furthermore, as shown in FIG. 11B, an impurity injection layer 20 may be provided in contact with the insulating layer 14 between the source and drain to suppress the depletion layer.

Furthermore, as shown in FIG. 12, the insulating layer 14
The doping concentration may be increased only in the channel layer 2 where there is no.

Furthermore, in the semiconductor device isolation method of the above embodiment, selective epitaxial growth may be performed after forming the isolation insulating film to reduce surface steps. Furthermore, as shown in FIG. 13, it is also possible to improve the latch-up resistance by forming a buried high concentration impurity layer 21 under the thin insulating layer 15 formed between the elements.

Furthermore, in the above embodiment, N channels M
Although we have explained OSFET, P-channel MOSFE
It goes without saying that the same applies to T, and also applies to a CMOS configuration. However, regarding isolation, it is possible to provide a device isolation insulating film between the NMOS and PMOS, or to form one by ion implantation and the other by using a doped selective epitaxial layer.

[0028]

Effects of the Invention The present invention provides a method for forming a buried drain region between a source region and a drain region, starting in the channel layer, ending in the substrate, and contacting the buried drain region to a depth of 0.2 μm or more, which is at least equal to the drain junction depth of the buried drain region. An insulating layer having a depth of 0.2 μm or more and a width of 0.1 μm or less is provided between one of the source/drain regions of the first element and the other of the source/drain regions of the second element. Since another insulating layer is provided, the following effects can be obtained. No punch-through path, therefore finer MOSFE
In addition to being able to manufacture T, the junction depth can be increased and the thickness of the gate insulating film can be increased, so element deterioration due to hot carriers can be suppressed. Since the thickness of the gate insulating film can be increased, the channel concentration can be lowered, and the junction capacitance and
Parasitic capacitance such as gate capacitance can be reduced, and the vertical electric field in the channel is also reduced, mobility is increased, and leakage current due to band-to-band tunneling can be suppressed. Further, the saturation voltage can be improved and the saturation current can be increased. Furthermore, subthreshold characteristics can be improved. Furthermore, compared to the SOI structure, since only a silicon substrate with high thermal conductivity exists in the depth direction of the substrate, it is possible to realize a highly integrated device with excellent heat dissipation characteristics. In addition, due to its good heat dissipation properties, when operated at low temperatures such as liquid nitrogen temperature, there is little temperature rise, and there are advantages such as improved mobility and improved saturation current due to lower temperature. Furthermore, instability of the device due to residual heat is reduced when the device is turned on and off at high speed. Furthermore, since the separation of semiconductor devices is performed as described above, it is possible to perform separation with a fine width, and the deep separation depth ensures separation, and also improves resistance to latch-up etc. be done.

[Brief explanation of drawings]

[Fig. 1] MOSFE in a microscopic semiconductor device according to the present invention
It is a sectional view showing a T structure.

FIG. 2 is a cross-sectional view showing an isolation structure in a microscopic semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the separation structure.

FIG. 4 is a cross-sectional view showing the remaining part of the manufacturing process of the separation structure.

FIG. 5 is a cross-sectional view showing a part of the manufacturing process of a MOSFET structure.

FIG. 6 is a cross-sectional view showing the remaining part of the manufacturing process of the MOSFET structure.

FIG. 7 is a cross-sectional view showing another MOSFET structure.

FIG. 8 is a cross-sectional view showing still another MOSFET structure.

9 is a cross-sectional view showing a manufacturing process of the MOSFET structure shown in FIG. 8. FIG.

FIG. 10 is a cross-sectional view showing another MOSFET structure.

FIG. 11 is a cross-sectional view showing still another MOSFET structure.

FIG. 12 is a cross-sectional view showing another MOSFET structure.

FIG. 13 is a sectional view showing another separation structure.

FIG. 14 is a cross-sectional view showing a conventional MOSFET structure.

FIG. 15 is a sectional view showing a conventional separation structure.

FIG. 16 is a sectional view showing a conventional separation structure.

17 is a cross-sectional view showing the manufacturing process of the conventional separation structure shown in FIG. 15. FIG.

18 is a cross-sectional view showing a manufacturing process of the separation structure of FIG. 16. FIG.

FIG. 19 is a cross-sectional view showing a part of the manufacturing process of a conventional MOSFET structure.

FIG. 20 is a cross-sectional view showing the remaining part of the manufacturing process of a conventional MOSFET structure.

[Explanation of symbols]

1 Silicon substrate 2 Channel layer 3 Gate insulating film 4 Gate electrode 5 Sidewall 6 Low concentration source/drain region 7 High concentration source/drain region 7A High concentration drain region 14 Insulator layer 15 Insulator layer

Claims (5)

[Claims] 1. A substrate having one conductivity type, a channel layer formed on a part of this substrate and having the one conductivity type, and a channel layer formed in a part of this channel layer having the other conductivity type. A microscopic semiconductor device comprising source/drain regions and an insulating layer starting in the channel layer and ending in the substrate between the source and drain regions. 2. The channel region in the channel layer comprises:
The length of the insulating layer is 0.5 μm or less and the depth is shallower than the junction depth, and the insulating layer has a depth of 0.5 μm or less.
2. The fine semiconductor device according to claim 1, wherein the semiconductor device has a depth of 2 μm or more and is at least equal to the drain junction depth of a drain region buried in the substrate below the source/drain region. 3. The device according to claim 1 or 2, further comprising an insulating layer between one of the source/drain regions of the first element and the other of the source/drain regions of the second element. Microscopic semiconductor device. 4. The insulating layer has a depth of 0.2 μm.
4. The fine semiconductor device according to claim 3, wherein the width is at least m and is at most 0.1 μm. 5. Forming an insulating layer on a surface of a substrate; etching a portion of the substrate and the insulating layer to form a step on the substrate; and forming a semiconductor layer on the stepped substrate. forming an insulating film layer on a step portion of the semiconductor layer; forming a source/drain region in a part of the semiconductor layer; and burying the remainder of the semiconductor layer below the step portion. A method for manufacturing a microscopic semiconductor device, including a process.