JPH0432345A - Fault detection centralizing management system in multi-processor type exchange network - Google Patents

Fault detection centralizing management system in multi-processor type exchange network

Info

Publication number
JPH0432345A
JPH0432345A JP2138784A JP13878490A JPH0432345A JP H0432345 A JPH0432345 A JP H0432345A JP 2138784 A JP2138784 A JP 2138784A JP 13878490 A JP13878490 A JP 13878490A JP H0432345 A JPH0432345 A JP H0432345A
Authority
JP
Japan
Prior art keywords
processor
management center
master processor
line
fault detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2138784A
Other languages
Japanese (ja)
Inventor
Shigeo Ono
繁雄 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2138784A priority Critical patent/JPH0432345A/en
Publication of JPH0432345A publication Critical patent/JPH0432345A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for a private line by discriminating the presence of a fault depending on the presence of a reply to an acknowledge signal when the acknowledge signal is sent at a prescribed period to a master processor from a line accommodation processor and reporting it to a management sensor so as to confirm the presence of a fault of the master processor with the management center. CONSTITUTION:A line accommodation processor 112 discriminates the presence of a fault of a master processor 110 depending on the presence of a reply signal from the master processor 110, reports a discrimination result to a management center 3 and the management centre 3 manages centralizingly the state of all multi-processors 110-1n0. Thus, the normality confirmation function of the master processor being a criterion of a fault of each of multi-processor exchanges 11-1n being components of the multi-processor type exchange network is provided to the line accommodation processors 112-1n2 accommodating communication lines with the management center 3. Thus a private line to confirm the normality of the master processors 110-1n0 not directly accommodating any line is not required.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマルチプロセッサ型交換網における障害検出集
中管理方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection centralized management system in a multiprocessor type switching network.

〔従来の技術〕[Conventional technology]

従来、複数のマルチプロセッサ型交換機とそれらを集中
管理する1つの管理センタとの間を通信回線で接続する
構成のマルチプロセッサ型交換網において、各マルチプ
ロセッサ型交換機の障害の判断規準となるマスタプロセ
ッサは管理センタとの間の通信回線を直接収容し、管理
センタに対して正常であることを一定周期で報告し、管
理センタではその報告の有無を一定周期で確認し、各マ
ルチプロセッサ型交換機から一定周期内に所定回数の正
常報告がなければその交換機は障害であると見なしてい
る。
Conventionally, in a multiprocessor switching network that connects multiple multiprocessor switches and a single management center that centrally manages them through communication lines, a master processor serves as a criterion for determining failures in each multiprocessor switch. directly accommodates the communication line with the management center, and reports to the management center that it is normal at regular intervals.The management center checks whether the report has been received at regular intervals, and from each multiprocessor type switch. If there is no normality report a predetermined number of times within a predetermined period, the exchange is considered to be at fault.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のマルチプロセッサ型交換網における障害
検出集中管理方式では、各交換機のマスタプロセッサに
通信回線を直接収容する必要があるため、その通信回線
は専用回線になるという欠点がある。
The above-described conventional fault detection centralized management system in a multiprocessor type switching network has the disadvantage that the communication line becomes a dedicated line because it is necessary to directly accommodate the communication line in the master processor of each exchange.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のマルチプロセッサ型交換網における障害検出集
中管理方式は、複数のマルチプロセッサ型交換機とそれ
らを集中管理する1つの管理センタとの間を通信回線で
接続してなるマルチプロセッサ型交換網における障害検
出集中管理方式において、前記各マルチプロセッサ型交
換機はその障害の判断規準となる前記通信回線を直接収
容しないマスタプロセッサおよび前記管理センタとの間
の前記通信回線を収容する回線収容プロセッサを備え、
前記回線収容プロセッサは前記マスタプロセッサに一定
周期で確認信号を送ったときこの確認信号への応答の有
、無により障害の無、有を判定して前記管理センタに報
告し、前記管理センタは前記報告により前記マスタプロ
セッサの障害の有無を確認することを特徴とする。また
、前記回線収容プロセッサは前記マスタプロセッサに前
記確認信号を送ってから前記応答を受信するまでをタイ
ミング監視し、タイムアウト前に前記応答を受信しなか
ったときは前記マスタプロセッサが障害である旨を前記
管理センタに報告するものとしてもよい。
The fault detection centralized management method for a multiprocessor type switching network according to the present invention is directed to a fault detection centralized management method for a multiprocessor type switching network in which a plurality of multiprocessor type exchanges and a single management center that centrally manages them are connected via communication lines. In the detection centralized management method, each of the multiprocessor type exchanges includes a master processor that does not directly accommodate the communication line and a line accommodation processor that accommodates the communication line between it and the management center, which serves as a criterion for determining a failure;
When the line accommodation processor sends a confirmation signal to the master processor at regular intervals, it determines whether there is a failure or not based on the presence or absence of a response to the confirmation signal and reports it to the management center, and the management center The present invention is characterized in that the presence or absence of a failure in the master processor is confirmed based on the report. Further, the line accommodation processor monitors the timing from sending the confirmation signal to the master processor until receiving the response, and if the response is not received before a timeout, it indicates that the master processor is at fault. The information may be reported to the management center.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す共通線信号方式を使用
したマルチプロセッサ型交換網のブロック図、第2図は
第1図における障害検出動作のシーケンス図である。
FIG. 1 is a block diagram of a multiprocessor type switching network using a common line signaling system showing one embodiment of the present invention, and FIG. 2 is a sequence diagram of a failure detection operation in FIG. 1.

第1図において、交換網は複数のマルチプロセッサ型交
換機11〜1nと、それらを集中管理する1つの管理セ
ンタ3との間を共通線41〜4n。
In FIG. 1, the switching network uses common lines 41 to 4n between a plurality of multiprocessor type exchanges 11 to 1n and one management center 3 that centrally manages them.

信号中継局2を介して共通線5で接続して構成されてい
る。各マルチプロセッサ型交換機、例えばマルチプロセ
ッサ型交換機11はマスタプロセッサ110が通信バス
111を介して回線収容プロセッサ112と接続され、
回線収容プロセッサ112は共通線41を介して信号中
継局2と接続されている。
They are connected via a signal relay station 2 and a common line 5. In each multiprocessor type exchange, for example, the multiprocessor type exchange 11, a master processor 110 is connected to a line accommodation processor 112 via a communication bus 111,
The line accommodation processor 112 is connected to the signal relay station 2 via a common line 41.

続いて本実施例の障害検出動作について第2図を併用し
て説明する。
Next, the fault detection operation of this embodiment will be explained with reference to FIG.

まず、回線収容プロセッサ112は通信バス111を介
してマスタプロセッサ110に確認信号aを一定周期で
送信すると共に監視タイミングを開始する。マスタプロ
セッサ110は確認信号aを受信すると、それに対する
応答信号すを回線収容プロセッサ112に返送する。
First, the line accommodation processor 112 transmits a confirmation signal a to the master processor 110 at regular intervals via the communication bus 111 and starts monitoring timing. When the master processor 110 receives the confirmation signal a, it returns a response signal to the line accommodation processor 112.

回線収容プロセッサ112は所定のタイミングT以内に
応答信号すを受信すれば共通線41.信号中継局2.共
通線5を介して管理センタ3に正常報告Cを行う、この
とき管理センタ3では、マルチプロセッサ型交換機11
が正常であると判断する。
If the line accommodation processor 112 receives the response signal within a predetermined timing T, the common line 41. Signal relay station 2. A normality report C is sent to the management center 3 via the common line 5. At this time, the management center 3
is judged to be normal.

ここでマスタプロセッサ110に異常が発生する(X印
で図示)と、回線収容プロセッサ112は応答信号すを
受信できない、タイミングT以内に応答信号すを受信で
きないと、回線収容プロセッサ112は管理センタ3に
障害報告dを行う。
If an abnormality occurs in the master processor 110 (indicated by an X mark), the line accommodation processor 112 cannot receive the response signal. File a problem report d.

管理センタ3では所定の時間内に障害報告dを所定回数
(例えば3回)受信したとき、マルチプロセッサ型交換
機11内のマスタプロセッサ110に障害ありと判断す
る。即ち回線収容プロセッサ112はマスタプロセッサ
110からの応答信号の有、無により、マスタプロセッ
サ110の障害の無、有を判定して管理センタ3に判定
結果を報告し、管理センタ3は全マルチプロセッサ11
0〜1nOの状態を集中管理する。
When the management center 3 receives the failure report d a predetermined number of times (for example, three times) within a predetermined time, it determines that there is a failure in the master processor 110 in the multiprocessor exchange 11. That is, the line accommodation processor 112 determines whether there is a failure in the master processor 110 based on the presence or absence of a response signal from the master processor 110, and reports the determination result to the management center 3, and the management center 3
Centrally manage the state of 0 to 1 nO.

〔発明の効果〕 以上説明したように本発明は、マルチプロセッサ型交換
網を構成する各マルチプロセッサ型交換機の障害の判断
規準となるマスタプロセッサの正常性確認機能を、管理
センタとの間の通信回線を収容する回線収容プロセッサ
に持たせることにより、回線を直接収容しないマスタプ
ロセッサの正常性を確認するための専用回線を設けなく
てよい効果がある。
[Effects of the Invention] As explained above, the present invention provides a function for confirming the normality of a master processor, which is a criterion for determining a failure in each multiprocessor type switching equipment constituting a multiprocessor type switching network, by improving communication between the master processor and the management center. By providing the line accommodating processor that accommodates the line, there is an effect that there is no need to provide a dedicated line for checking the normality of the master processor that does not directly accommodate the line.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す共通線信号方式を使用
したマルチプロセッサ型交換網のブロック図、第2図は
第1図における障害検出動作のシーケンス図である。 11、〜1n・・・マルチプロセッサ型交換機、2・・
・信号中継局、3・・・管理センタ、41.〜4n・・
・共通線、110.〜1nO・・・マスタプロセッサ、
111、〜lnl・・・通信バス、112.〜1n2・
・・回線収容プロセッサ、a・・・確認信号、b・・・
応答信号、C・・・正常報告、d・・・障害報告。
FIG. 1 is a block diagram of a multiprocessor type switching network using a common line signaling system showing one embodiment of the present invention, and FIG. 2 is a sequence diagram of a failure detection operation in FIG. 1. 11, ~1n...Multiprocessor type exchange, 2...
- Signal relay station, 3... Management center, 41. ~4n...
・Common line, 110. ~1nO...master processor,
111, ~lnl...communication bus, 112. ~1n2・
... line accommodation processor, a... confirmation signal, b...
Response signal, C: Normal report, d: Failure report.

Claims (1)

【特許請求の範囲】 1、複数のマルチプロセッサ型交換機とそれらを集中管
理する1つの管理センタとの間を通信回線で接続してな
るマルチプロセッサ型交換網における障害検出集中管理
方式において、前記各マルチプロセッサ型交換機はその
障害の判断規準となる前記通信回線を直接収容しないマ
スタプロセッサおよび前記管理センタとの間の前記通信
回線を収容する回線収容プロセッサを備え、前記回線収
容プロセッサは前記マスタプロセッサに一定周期で確認
信号を送ったときこの確認信号への応答の有、無により
障害の無、有を判定して前記管理センタに報告し、前記
管理センタは前記報告により前記マスタプロセッサの障
害の有無を確認することを特徴とするマルチプロセッサ
型交換網における障害検出集中管理方式。 2、前記回線収容プロセッサは前記マスタプロセッサに
前記確認信号を送ってから前記応答を受信するまでをタ
イミング監視し、タイムアウト前に前記応答を受信しな
かったときは前記マスタプロセッサが障害である旨を、
前記管理センタに報告することを特徴とする請求項1記
載のマルチプロセッサ型交換網における障害検出集中管
理方式。
[Scope of Claims] 1. A fault detection centralized management method in a multiprocessor type switching network in which a plurality of multiprocessor type exchanges and a single management center that centrally manages them are connected via communication lines, wherein each of the above-mentioned The multiprocessor type switch is equipped with a master processor that does not directly accommodate the communication line and a line accommodation processor that accommodates the communication line between it and the management center, which serves as a criterion for determining a failure, and the line accommodation processor is connected to the master processor. When a confirmation signal is sent at regular intervals, the presence or absence of a failure is determined based on the presence or absence of a response to the confirmation signal, and the result is reported to the management center, and the management center uses the report to determine whether or not there is a failure in the master processor. A fault detection centralized management method in a multiprocessor type switching network, which is characterized by checking. 2. The line accommodation processor monitors the timing from sending the confirmation signal to the master processor until receiving the response, and if the response is not received before a timeout, it indicates that the master processor is at fault. ,
2. The fault detection centralized management system in a multiprocessor type switching network according to claim 1, wherein the fault detection is reported to the management center.
JP2138784A 1990-05-29 1990-05-29 Fault detection centralizing management system in multi-processor type exchange network Pending JPH0432345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2138784A JPH0432345A (en) 1990-05-29 1990-05-29 Fault detection centralizing management system in multi-processor type exchange network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2138784A JPH0432345A (en) 1990-05-29 1990-05-29 Fault detection centralizing management system in multi-processor type exchange network

Publications (1)

Publication Number Publication Date
JPH0432345A true JPH0432345A (en) 1992-02-04

Family

ID=15230128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2138784A Pending JPH0432345A (en) 1990-05-29 1990-05-29 Fault detection centralizing management system in multi-processor type exchange network

Country Status (1)

Country Link
JP (1) JPH0432345A (en)

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