JPH04321158A - Distribution/collection processor for array data - Google Patents

Abstract

PURPOSE:To obtain a means which can optionally divide and assign the array data in a simple and highly efficient way for a distribution/collection processor which divides and assigns the array data to plural processors through a parallel computer and then distributes automatically the array data in an optional transfer pattern. CONSTITUTION:A transfer table production means 11 produces a transfer table 16 which contains the information on each dimensional range in accordance with the blocks divided in one or more optional dimensional directions and to be assigned to each storage space or each processor 10. A data transfer means 12 transfers the data to each storage space or each processor 10 for each divided block by reference to the table 16. Thus the array data can be automatically distributed in an optional transfer pattern.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a device for dividing and allocating array data to a plurality of processors in a parallel computer, and in particular, an array data distribution/collection processing device that automatically distributes or automatically collects data according to an arbitrary transfer pattern. Regarding.

[0002] When processing huge array data,
Systems are used in which data is divided and allocated to multiple processors and processed in parallel. In order to be able to dynamically switch how data is divided and process it, a technology is needed to efficiently rearrange data.

0003

[Prior Art] In parallel computers, in order to efficiently handle array data, it is necessary to block it into hypercuboid areas along the dimensions, separate memory allocation for each block, and manage each block with each processor in charge. many.

FIG. 13 shows an example of such division of array data. In the example shown in Figure 13, the three-dimensional array A (10
0,100,100). (a) shows an example of one-dimensional partitioning, (b) shows an example of multidimensional partitioning, and (c) shows an example of multidimensional uneven partitioning. When dividing, it can also be interpreted as one division in the i direction and the j direction.

Generally, an n-dimensional array A (M1, M2,...
, Mn) for each dimension, p1, p2,
…, pn parts (each an integer greater than or equal to 1),
It can be divided into (p1×...×pn) hypercuboid blocks. A distributed memory type parallel computer can reduce the amount of data transferred during calculations and improve efficiency by dividing and arranging data to suit the processing procedures of each processor. In the case of a shared memory type parallel computer, similar partitioning can reduce memory contention and allow processing to proceed more efficiently.

[0006] Furthermore, by dividing the physical addresses for each block, the data handled by each processor can be collected in physically consecutive addresses, which reduces page switching and cache memory misses, and reduces the number of page switches and cache memory misses. It has the advantage of being able to address even huge array data that cannot fit into the address space of .

[0007] As described above, partitioning and allocation of arrays is important, but in actual application programs, the method of partitioning data is rarely fixed, and repartitioning that involves data transfer processing during execution processing is important. Allocation is frequently required. This is the case, for example, as follows.

(a) Change in data correlation direction, especially AD
E (alternating direction editing) is well known. This is an edit that changes from a plate-like division in one dimension to a plate-like division in another dimension. Matrix calculations such as LU decomposition and multidimensional FE
Since it is necessary for T, etc., it is frequently used in numerical calculations of continuous systems. As the number of processors increases, multidimensional partitioning becomes necessary, which inevitably leads to more complex transfer patterns. For example, array A(100,100,100)
In order to allocate this to 200 processors, the only way is to divide it into two or more dimensions, and in that case, ADE transfer becomes quite complicated.

(b) Re-division allocation such as subdivision In general, as the degree of parallelism increases, overheads such as data transfer and synchronization increase, so there is an optimal value for the number of processors used depending on the procedure. Accordingly, it may be necessary to change the data partitioning allocation at the boundary between procedures with different parallelism effects.

(c) Reasons for computer operation Due to a failure of some processors, a change in the number of simultaneous users, etc., it may be necessary to move data between processors with a change in partitioning.

Conventionally, when a user writes a description using a computer description language such as FORTRAN or the C language, it takes a lot of time and effort to calculate the subscripts of an array. was difficult. Furthermore, there is a problem in that the timing of data transfer is often difficult for the user to predict, making it difficult to improve efficiency.

[0012] This may be achieved relatively easily by restricting the shape of the division, the number of divisions, etc., and computers equipped with hardware designed to improve the efficiency of specific transfer patterns are being considered, but There will be major restrictions in terms of width and operational format. In particular, in order to provide a highly versatile computer, it must be able to accommodate whatever division shape or transfer pattern the user requires. However, until now, there has been no means that can flexibly accommodate arbitrary division shapes and transfer patterns.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide means for easily and efficiently realizing arbitrary division and allocation of array data. In other words, the purpose is to enable the user to allocate and change the partitioning of an array by simply specifying the partition shape and array range without having to be explicitly aware of the details of data transfer. shall be.

[0014] Furthermore, the present invention is not limited by the order or size of the array, the number of division dimensions, whether the division width is equal, etc.
The purpose is to provide a means of distributing and collecting data that is widely applicable.

[0015]

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 10a, 10b,..., 10c
are processors each having an independent data processing function, 1
1 is a transfer table creation means, 12 is a data transfer means for distributing or collecting data, 13 is a division section number designating means for specifying the division section number of a block to be divided or collected, and 14 is a section for specifying the upper and lower limits of the division section of each block. 15 is a shared memory accessible from each processor; 16 is a transfer table used for data distribution or collection; 17 is a distribution data storage area in which data to be distributed is stored; 18 19 represents a transfer destination data storage area in which data to be processed by each processor is stored; 19 represents a collection data storage area in which collected data is stored; and 20 represents a transfer source data storage area in which data to be collected is stored.

[0016] The invention recited in claim 1 has a configuration as shown in (a), for example. An arbitrary partial array that is allocated within one block using a certain partitioning method is partitioned and allocated according to another partitioning method. Therefore, the processor 10a obtains the division section number of the block to be divided from the division section number designation means 13, and determines the range of the upper and lower limits of the division block corresponding to each division section number from the division section upper and lower limit designation means 13. Get from. The division section number designating means 13 and the division section upper and lower limit designation means 14 may be any means such as an input/output device, an external storage device, or a program.

The transfer table creation means 11 selects one to be allocated to each transfer destination data storage area 18 in the shared memory 15 based on information obtained from the division section number designation means 13 and the division section upper and lower limit designation means 14. A transfer table 16 having information regarding the range of each dimension is created corresponding to the divided blocks divided in the above arbitrary dimension directions.

The data transfer means 12 transfers data to each storage space for each divided block based on the created transfer table 16. That is, based on the transfer table 16, the data in the distribution data storage area 17 is distributed to the transfer destination data storage area 18 designated corresponding to each processor.

In the example shown in FIG. 1(a), the shared memory 15
Data is distributed above, but in a distributed memory computer, data is transferred to the local memory of each processor. The invention recited in claim 2 has a configuration as shown in (b), for example.

Data is collected from arrays that are distributed and allocated using one division method, and arbitrary partial arrays belonging to one block based on another division method are collected. Therefore, the processor 10a obtains the division section number of the block to be collected from the division section number designation means 13, and determines the range of the upper and lower limits of the division block corresponding to each division section number from the division section upper and lower limit designation means 13. Get from.

The transfer table creation means 11 is arranged in a distributed manner in the transfer source data storage area 20 in the shared memory 15 based on the information obtained from the division section number designation means 13 and the division section upper and lower limit designation means 14. A transfer table 16 having information regarding the range of data to be collected for each dimension is created corresponding to the divided blocks divided in one or more arbitrary dimension directions.

The data transfer means 12 transfers the collected data for each divided block from each transfer source data storage area 20 to the collected data storage area 1 based on the created transfer table 16.
Transfer to 9. In the example shown in (b) of Figure 1, the shared memory 1
In a distributed memory computer, data is transferred from the local memory of each processor to the local memory of the processor that collects the data.

[0023]

[Operation] In the invention as claimed in claim 1, for example, the n-dimensional array A
(M1, M2, ..., Mn) (n≧1, Md is the dimension d) subarray A (i1:j1, i2:j2, ..., in:jn
) (id, jd are the lower limit and upper limit of the index of dimension d, respectively. 0≦id≦jd≦Md−1) is within one divided block, this is divided and allocated according to another division method.

In the second aspect of the invention, on the other hand, partial arrays that have been divided and allocated are collected into one divided block according to another division method. A subarray may be the entire array. To simplify the explanation, it is assumed that the array index and division section number of each dimension are counted from 0. In other cases (for example, when counting from 1), the present invention may be applied with a shift. Furthermore, for each divided block, the memory allocation of array element A (k1,...,kn) is assumed to be placed at the address shown by the following equation.

(Base address) + (word length) ×
(k1+m1×(k2+m2×(
...m(n-1)×kn...))) (Formula 1
) In distributed memory computers, the correspondence between distributed blocks and processors is managed using tables, etc.

[0026] This coefficient md (d=1, 2,..., n-1)
is called the division coefficient of dimension d of the divided block. The division coefficient is a constant greater than or equal to the division width (index number) in the dimension direction. If equal to the partition width, the array elements within the block are allocated to consecutive addresses.

[1] In the case of a shared memory type computer, the distribution procedure when an arbitrary partial array allocated in one block by a certain partitioning method A is divided and allocated according to another partitioning method B is as follows. become. ■ The processor 10a uses the division section number designation means 13
Thus, for all dimensions d=1, . . . , n, the division method B obtains the division section number pd corresponding to id and the division section number qd corresponding to jd. As a result, the range of divided blocks of division method B is (p1:q1,...,
pn:qn).

■ The area of the transfer table 16 is divided into (q1-p1 +1)×corresponding to the divided blocks of division method B.
…× (qn − pn +1) are secured. ■ The processor 10a divides the divided blocks (r1,...r
n) Corresponding to (rd = pd, ... qd; d = 1, ..., n), complete all transfer tables 16 as follows.

[0029] The lower limit value of dimension d is id when rd = pd. When rd≧pd, the lower limit of the division interval rd. The upper limit of dimension d is jd when rd = qd. When rd ≧ qd, the upper limit of the divided section rd.

(2) The processor 10a reads out the specified array element from the distribution data storage area 17 according to all the transfer tables 16, and writes it to the transfer destination data storage area 18. In both division method A and division method B, the address calculation is based on the above (Equation 1). The number of transfer tables 16 corresponding to the entire array may be secured in advance. In that case, step ■ is not necessary.

[2] When implementing the same processing using a distributed memory computer, the processor 10b corresponding to the divided block
, . . . data is sent to 10c. The first steps ① to ② are similar to the shared memory type. In ③, the following processing is performed. (2) The data transfer means 12 executes data transfer for each transfer table 16. If the mechanism is capable of transferring only one word length at a time, it will transfer one array element at a time while repeating the process for all dimensions. If there is a mechanism that can transfer consecutive addresses at once, it is possible to transfer consecutive array elements of the first dimension at one time while repeating execution for the second and subsequent dimensions. If the mechanism allows addressing with intervals, the first
, it is possible to transfer array elements of a two-dimensional rectangular area at once. If multidimensional intervals are possible, then
More array elements can be transferred at once.

[3] In a shared memory computer, collect arbitrary partial arrays belonging to one block using partitioning method B from the arrays allocated using partitioning method A, and use partitioning method B.
The collection procedure for allocation is as follows. ■ The processor 10a uses the division section number designation means 13
As a result, for all dimensions d=1, . . . , n, the division method A obtains the division section number pd corresponding to id and the division section number qd corresponding to jd. As a result, the range of divided blocks of division method A is (p1:q1,...,
pn:qn).

■ The area of the transfer table 16 is divided into (q1-p1 +1)×corresponding to the divided blocks of division method A.
…× (qn − pn +1) are secured. ■ As in the case of distribution [1], complete all transfer tables 16 corresponding to the divided blocks.

(2) The processor 10a reads out the specified array element from the transfer source data storage area 20 according to all the transfer tables 16, and writes it to the collected data storage area 19. In both division method A and division method B, the address calculation is based on the above (Equation 1). [4] When collecting on a distributed memory computer, each processor 10b,...10 in charge of a divided block
Data will be received from c.

[0035]

Embodiment FIG. 2 shows a configuration example of the present invention applied to a distributed memory parallel computer. In the example shown in FIG. 1, data to be processed by each of the processors 10a to 10c is divided and stored in the shared memory 15, whereas in the example shown in FIG. The data is distributed and stored in the data storage area 31 of the distributed memory 30. In this case, the data transfer means 12
is composed of a bus or a transfer device that transmits and receives data between the distributed memories 30 of each processor. The other configurations are almost the same as those shown in FIG.

FIG. 3 shows an example of the configuration of a transfer table used in the embodiment of the present invention. In the maximum case, the transfer table 16 is necessary for up to the number of divided blocks, and as shown in FIG. , indicates the range of split allocation.

As an example regarding ADE transfer, two-dimensional arrays A(30,50) and B(30,50) are used in a distributed memory parallel computer with 10 processors, and are divided as shown in FIG. A specific example of the arrangement will be explained. Assign all elements from array A to array B.

Each processor distributes the entire partial array of A for which it is responsible to B. For example, processor P0 is A(0:
29, 0:4) to the corresponding element of B using the following procedure. (2) For arrays A and B, information regarding pairs of indexes and division section numbers is held using, for example, the division information table shown in FIG. Or keep it in the form of a calculation formula. By referencing or calculating this in a processor, the range of the divided interval is recognized. The division section number designation means 13 and the division section upper and lower limit designation means 14 shown in FIG. 1 are means for obtaining such a division information table and the like.

■ From interval 0:29 of dimension 1 and interval 0:4 of dimension 2, the part of array B that is the transfer destination spans 10 blocks from divided blocks (0,0) to (9,0). It can be seen that ■ The transfer table 16 is set to 1 corresponding to the divided block.
Prepare 0 pieces.

(2) Complete the transfer table 16 as transfer tables 16-0, . . . , 16-9 shown in FIG. ■ Give the necessary parameters to the transfer device and start it. For example, if you are using hardware that sends and receives data from the address interval with intervals of its own processor to the address interval with intervals of another processor, block
For (1,0), set the following parameters and start.

(a) Number of transferred data N (5-3+1
)×(4-0+1)=15(b) Transfer destination processor P
Processor P1(c) Transfer source start address b1 Number of address continuous data of A(3,0) w1 5-3+1=3 Interval i1 30(d) Transfer destination start address b2 Number of address continuous data of B(3,0) w2 5-3+1=3 intervals i2
3. The number of transferred data N can be calculated from the transfer table 16-1 shown in FIG. The transfer source head address b1 is determined from the lower limit value of the transfer table 16-1. The continuous data number w1 and the interval i1 are determined from the continuous length of the transfer table 16-1 in the first dimension direction and the division width of the table shown in FIG. 5 in the first dimension direction. The same applies to the transfer destination.

The transfer device that has received the parameters reads N pieces of data from the memory while obtaining the transfer source address, for example according to the procedure described later in accordance with FIG. Send to. Similarly, the receiving device such as the processor P1 sequentially writes N pieces of data while obtaining the transfer destination address using the procedure shown in FIG.

As a result, the data that was divided and allocated to each of the processors P0 to P9 as shown in array A in FIG. 7 is rearranged as shown in array B. In the above example, data in array A is rearranged as array B by distribution, but it is also possible to rearrange data in the same way by collecting distributed data. in this case,
Each processor P0 to P9 collects the entire partial array of array B for which it is responsible, from array A. For example, processor P0 receives partial array B (0:2, 0:49) from the corresponding element of array A. The procedure is as follows.

(2) This is the same as (2) in the above distribution. ■ The part of array A that is the transfer source is a divided block (0
,0) to (0,9). ■ Transfer table 16 is set to 10 in correspondence with the divided blocks.
Prepare one.

■ Fill the transfer table according to the procedure shown in FIGS. 8 and 9. ■ Same as in the case of distribution above, but requests each processor to transfer data to itself and waits for a response. The process of creating the transfer table 16 in the above procedure is performed as shown in FIGS. 8 and 9. Note that this example is an example of dividing data in a three-dimensional array. (a) to (z) in the following explanation are shown in FIGS. 8 and 9 (
a) Corresponds to ~(z).

(a) Set the lower and upper limits of the index of dimension 1 of the partial array to variables i1 and j1. Similarly,
The lower and upper limits of the index of dimension 2 are set as variables i2 and j2, and the lower and upper limits of the index of dimension 3 are set as variables i3 and j3.
Set to . Also, p1, q1, p2, q2, p3,
q3, i1, j1, i2, j2, i3, j3 respectively
Set the division section number corresponding to .

(b) Set p1 to variable r1. (c) All r2=p2,...,q2; r3=p3,
..., q3, transfer table table(r1,
The value of i1 is set as the lower limit value of dimension 1 of (r2, r3).

(d) If r1=q1, process (i)
Proceed to. (e) The upper limit of the division interval r1 of dimension 1 is set as the variable top
Set to . (f) All r2=p2,...,q2; r3=p3,
..., q3, transfer table table(r1,
The value of top is set as the upper limit value of dimension 1 of (r2, r3).

(g) Add 1 to r1 (h) For all r2 = p2,..., q2; r3 = p3,..., q3, transfer table table (r1, r2, r3)
The value of top+1 is set as the upper limit value of dimension 1 of . Thereafter, the process returns to process (d).

(i) All r2=p2,...,q2;
For r3=p3,...,q3, transfer table tab
As the upper limit of dimension 1 of le (r1, r2, r3), j
Set the value to 1. (j) Set p2 to variable r2.

(k) All r1=p1,...,q1;
For r3=p3,...,q3, transfer table tab
As the lower limit of dimension 2 of le (r1, r2, r3), i
Set the value of 2. (l) If r2=q2, proceed to process (q).

(m) Set the upper limit value of the division interval r2 of dimension 2 to the variable top. (n) All r1=p1,...,q1; r3=p3,
..., q3, transfer table table(r1,
The value of top is set as the upper limit value of dimension 2 of r2, r3).

(o) Add 1 to r2 (p) For all r1 = p1, ..., q1; r3 = p3, ..., q3, transfer table table (r1, r2, r3)
The value of top+1 is set as the upper limit value of dimension 2 of . Then, return to process (l).

(q) All r1=p1,...,q1;
For r3=p3,...,q3, transfer table tab
As the upper limit of dimension 2 of le (r1, r2, r3), j
Set the value of 2. (r) Set p3 to variable r3.

(s) all r1=p1,...,q1;
For r2=p2,...,q2, transfer table tab
As the lower limit of dimension 3 of le(r1, r2, r3), i
Set the value of 3. (t) If r3=q3, proceed to process (y).

(u) Set the upper limit value of the divided section r3 of dimension 3 to the variable top. (v) All r1=p1,...,q1; r2=p2,
..., q2, transfer table table(r1,
The value of top is set as the upper limit value of dimension 3 of r2, r3).

(w) Add 1 to r3 (x) For all r1 = p1, ..., q1; r2 = p2, ..., q2, transfer table table (r1, r2, r3)
The value of top+1 is set as the upper limit value of dimension 2 of . Thereafter, the process returns to process (t).

(y) all r1=p1,...,q1;
For r2=p2,...,q2, transfer table tab
As the upper limit of dimension 3 of le (r1, r2, r3), j
Set the value of 3 and complete the creation of the transfer table. The transfer device that transfers data has the processing logic shown in Figure 10.
The forwarding source or forwarding destination address is determined by

■ The number of data is N, the start address is b,
Let w be the number of continuous data and i be the interval. ■ 0 in variable k0, (i-w) in variable d, address a
Set b to ddr. ■ Set variable k1 to 0.

■ When the variable k0 becomes N, the process ends. ■ Access address addr. For the transfer source, read (Read), for the transfer destination, write (W)
rite). ■ Advance address addr by one step. Variables k0, k1
Add 1 to each.

■ Return to ■ and repeat the process until the variable k1 becomes w. ■ If variable k1 becomes w, address addr
After adding d to , return to step 3 and repeat the process. A transfer device that transfers data can be easily constructed using hardware that determines addresses using the above processing logic. Alternatively, it can also be configured by software in each processor.

When the present invention is applied to the initialization of a divided array, it is performed as follows. Initialization of a divided array with values written in a file or object code is achieved by regarding these initialization data strings as an array divided into 1×...×1, and distributing or collecting them by each processor. can do. However, when inputting from a sequential file, serialization processing is required between processors. Exclusive processing may be necessary.

When applying the present invention to the output of a divided array,
Do as follows. Outputting a divided array to a file or printer can be achieved by regarding these output destinations as an array divided into 1×...×1, and applying the distribution according to the present invention to each processor. However, when outputting to a sequential file or outputting to a printer where the output order is meaningful, serialization processing is required between processors. Exclusive processing may be necessary.

FIGS. 11 and 12 show an example of divisional allocation to which the present invention is applied and an example of data arrangement in actual memory. For example, a rectangular partial array X (1:6) of the two-dimensional array X (8, 12) shown in FIG.
, 1:7) in the first dimension direction with interval widths 2, 3, 3,
When divided in the second dimension direction by interval widths 4, 4, 4, the divided image becomes as shown in (b) of FIG.

If the data in each block divided into 3×3 blocks is allocated to consecutive addresses on the memory, the memory allocation will be as shown in FIG.
The situation will be as shown in (f). The partial array spans six blocks and is distributed at seemingly irregular addresses. However, in cases such as distributed memory type,
Each processor is aware of memory allocation according to the partitioning method,
It is possible to process data efficiently.

[0066]

[Effect of the invention] As explained above, according to the present invention,
Transfers between arrays with different partition shapes and input/output processing to partition arrays can be performed easily and efficiently in a unified manner. In particular, it is possible to improve the efficiency of data transfer processing in distributed memory parallel computers, which has a great effect on reducing the burden on user programs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram showing another configuration example of the present invention.

FIG. 3 is a diagram showing a configuration example of a transfer table according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of redistribution according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a division information table used in an embodiment of the present invention.

FIG. 6 is a diagram showing an example of a transfer table according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of memory allocation according to an embodiment of the present invention.

FIG. 8 is an explanatory diagram of transfer table creation processing according to an embodiment of the present invention.

FIG. 9 is an explanatory diagram of transfer table creation processing according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram of data transfer control according to an embodiment of the present invention.

FIG. 11 is a diagram showing an example of divisional allocation related to the present invention.

FIG. 12 is a diagram showing an example of memory allocation related to the present invention.

FIG. 13 is a diagram showing an example of dividing array data in a parallel computer.

[Explanation of symbols]

10a to 10c Processor 11 Transfer table creation means 12
Data transfer means 13 Division number designation means 14
Divided section upper and lower limit designation means 15 Shared memory 16 Transfer table 17 Distribution data storage area 18 Transfer destination data storage area 19 Collection data storage area 20 Transfer source data storage area

Claims (2)

[Claims] Claim 1: A computer in which a plurality of processors (10) each process data allocated to its own device, the computer processing all or part of data input from an input device or array data stored in a storage device. In a distribution/collection processing device for array data that is divided and allocated to each storage space or each processor (10), partitioning is performed in one or more arbitrary dimension directions to be allocated to each storage space or each processor (10). Corresponding to the block, a transfer table (16
); and data transfer means (12) that transfers data for each divided block to each storage space or each processor (10) based on the created transfer table (16). 1. An array data distribution/collection processing device, characterized in that the data is automatically distributed according to an arbitrary transfer pattern. 2. A computer in which a plurality of processors (10) each process data allocated to its own device, wherein all or part of the data distributed in each storage space or each processor (10) is processed. In an array data distribution/collection processing device that collects parts into a certain storage space or one processor (10), one or more arbitrary dimensional directions are distributed and arranged in each storage space or each processor (10). a transfer table creation means (11) for creating a transfer table (16) having information regarding the range of each dimension of data to be collected corresponding to the divided blocks divided by; and based on the created transfer table (16). The present invention is characterized in that it is equipped with a data transfer means (12) for transferring collected data for each divided block to a certain storage space or one processor (10), and is configured to automatically collect data according to an arbitrary transfer pattern. Array data distribution/collection processing device.