JPH04311245A - Computer device - Google Patents

Abstract

PURPOSE:To make plural I/O ports having the same port address and different functions normally accessible while the ports are simultaneously mounted by setting desired port accessing light in advance. CONSTITUTION:When a CPU 1 wants to read the data of an I/O port 13 or 14, the CPU 1 sends an I/O port address z which is common to the I/O ports to a system bus. Then the CPU 1 sets a system bus reading request signal 15 to an 'L' level and, when both of the switch signal 17 of a switch 2 and port output 18 of an I/O port 3 are 'H' in level, only the readout request signal 19 of the I/O port 13 to an 'L' level. Then the I/O port 13 sends the data to a data bus, because the address sent from the CPU 1 matches with its own address z and the signal 19 is 'L' in level. When either the switch signal 17 or port output 18 is 'L' in level, the I/O port 13 sets a readout signal 21 only to an 'L' level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device equipped with an I/O channel and an I/O slot for mounting an I/O board on which peripheral integrated circuits are mounted.

0002

[Prior Art] In general computer equipment, C.
The connection between the PU and the I/O channel is configured as shown in FIG.

FIG. 5 is a block diagram illustrating the connection relationship between a CPU and an I/O channel in this type of computer device. Reference numeral 51 denotes a CPU, which connects devices (not shown) via a system bus 52. A plurality of I/O slots 54 are provided which are configured to be totally controllable and which are attached to the I/O channels 53.

[0004] I/O slot 54 configured in this way
When an I/O board on which a peripheral integrated circuit is mounted is installed on the CPU 51, access to the I/O board from the CPU 51 is via the I/O port on the I/O board using signals on the system bus 52. is running through. That is, C
The PU 51 accesses the I/O board by reading and writing data to the I/O port using signals from the system bus 52. Furthermore, I/O boards have different port addresses for different purposes. Since a plurality of I/O ports can be provided, the CPU 51 can identify and access each I/O port by the port address number of the I/O port.

FIG. 6 shows the I
3 is a flowchart illustrating an example of a read access processing procedure for the /O port. Note that (1) to (5) indicate each step.

[0006] When the CPU 51 attempts to read data from an I/O port at a certain address, the system bus 52
The CPU 51 sends the port address of the I/O port to the I/O port (1). Next, the CPU 51 connects to the system bus 5.
The read request signal -IOR (active in LOW state) of No. 2 is set to LOW state (2). At this time, I/O
The port sends data to the system bus 52 because the address sent from the CPU 51 to the system bus 52 matches its own port address and the read request signal -IOR of the system bus 52 is in the LOW state (3
). Next, the CPU 51 reads the data on the system bus 52 (4), and the CPU 51 returns the read request signal -IOR on the system bus 52 to the HIGH state (5).
Finish the read operation.

According to the above procedure, the CPU 51 reads desired data from the I/O port of the I/O board.

The write access processing operation of the I/O port by the CPU 51 will be described below with reference to the flowchart shown in FIG.

FIG. 7 shows the I
3 is a flowchart illustrating an example of a write access processing procedure for the /O port. Note that (1) to (5) indicate each step.

When the CPU 51 attempts to write data to an I/O port at a certain address, the CPU 51 sends the port address of the I/O port to the system bus 52 (1). Next, the CPU 51 connects to the system bus 52.
The write request signal -IOW (active in LOW state) is set to LOW state (2). At this time, the I/O port does not send data to the system bus 52 because the address sent from the CPU 51 to the system bus 52 matches its own port address and the write request signal -IOW of the system bus 52 is in the LOW state. Send (3)
. Next, the I/O board reads the data on the system bus 52 (4), the CPU 51 returns the write request signal -IOW on the system bus 52 to the HIGH state (5),
Finish the write operation.

According to the above procedure, the CPU 51 writes desired data to the I/O port of the I/O board.

[0012] In this way, the CPU 51 is able to access the I/O board.

[0013]

However, in conventional computer equipment, multiple I/O boards having the same I/O port address are connected to the I/O channels.
/O slot, when the CPU 51 accesses the I/O ports, multiple I/O ports will be accessed at the same time.
It becomes impossible to control access only to ports and I/O boards, and there are problems such as the computer device being unable to perform normal data processing (normally inoperable state) and unable to normally execute programs. Therefore, there is a problem in that I/O boards having the same I/O port address and different functions cannot be simultaneously installed in the I/O slots of the computer device.

The present invention has been made to solve the above problems, and by setting access to desired I/O boards having the same I/O port address and different functions, multiple To obtain a computer device which can be normally accessed even when I/O boards having the same port address and different functions are installed at the same time.

[0015]

SUMMARY OF THE INVENTION A computer apparatus according to the present invention is provided with a setting means for setting in advance a desired board access destination for port addresses that conflict with each other in a plurality of I/O boards.

Further, the setting means is constituted by a soft switch that sets a desired board access destination for a port address that conflicts with each other in a plurality of I/O boards based on an input board access destination designation state.

Furthermore, the setting means is constituted by a hard switch for manually setting desired board access destinations for mutually conflicting port addresses in a plurality of I/O boards.

Further, the setting means is constituted by an address converter that converts an arbitrarily output port address into a conflicting port address.

[0019]

[Operation] In the present invention, a plurality of I/Os are set by the setting means.
If the desired board access destination for port addresses that conflict with each other on the O board is set in advance, when port addresses that conflict with each other are specified on multiple I/O boards, only the desired I/O board will be accessed. Enable normal access.

[0020] Furthermore, when desired board access destinations for port addresses that conflict with each other on multiple I/O boards are set based on the board access destination instruction state inputted by the soft switch, the multiple I/O boards When conflicting port addresses are specified, the desired I
/ Allow normal access only to the O board.

[0021] Furthermore, a hard switch allows multiple I/O
If you manually set the desired board access destination for port addresses that conflict with each other on the O board, when conflicting port addresses are specified on multiple I/O boards, only the desired I/O board will be accessed. Enable normal access.

Furthermore, when an arbitrary port address is output, the address converter converts it into a port address that conflicts with each other on multiple I/O boards, allowing normal access to only the desired I/O board. .

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a system block diagram showing the configuration of main parts of a computer device according to an embodiment of the present invention, mainly showing the configuration of an I/O board control section.

In the figure, 1 is a CPU, 2 is a hardware switch (switch), and by switching the hardware switch 2, one input of the AND operation unit 12 at the subsequent stage can be set to HIGH or LOW. 3 is an I/O port, which can be accessed by software, and data “80
If you write data "00H", the output of I/O port 3 will be set to HIGH, and if you write data "00H", the output of I/O port 3 will be set to LOW. It is possible. 4-7 are NAND operation units, 8-
11 is a NOT arithmetic unit, and 12 is an AND arithmetic unit. 13
is an I/O board (I/O board A), which has an I/O board (not shown).
It is installed in the I/O slot of the O channel and has an I/O port with I/O port address Z. 14 is an I/O board (I/O board B), which is an I/O board (not shown).
It is attached to the I/O slot of the channel and has an I/O port with I/O port address Z. 15 is a system bus read request signal (read request signal - IOR
), 16 is a system bus write request signal (write request signal - IOW), 17 is a switch signal that is the output of the switch 2, 18 is a port output that is the output of the I/O port 3, and 19 is the I/O port output. A read request signal input to the O board 13; 20 a write request signal input to the I/O board 13; 21 a read request signal input to the I/O board 14; 22 a write request signal input to the I/O board 14; A write request signal is input to 14, and 23 is an address converter.
By specifying a pre-conversion address and a post-conversion address using software, the address sent from the CPU 1 is converted and delivered to the I/O slot. 24 is a system bus address signal, 25 is an address signal, and I/
O channel I/O slot 26 and address converter 2
3 and are mutually transferred.

The I/O board 13 and I/O board 14 will be explained below with reference to the flowchart shown in FIG.
The process of reading and accessing data from the O port will be explained.

In the computer device configured as described above, setting means (soft switch, hard switch,
A plurality of I/O boards (in this embodiment, the I/O board 13,
If the desired board access destination for mutually conflicting port addresses is set in advance in 14 I/O slots 26), when mutually conflicting port addresses are specified on multiple I/O boards, the desired I/O board Allow normal access only to .

For example, desired board access destinations are set for conflicting port addresses on a plurality of I/O boards based on the board access destination instruction state input by data set to I/O port 3, which serves as a soft switch. Then, when conflicting port addresses are specified on multiple I/O boards, only the desired I/O board can be accessed normally.

Furthermore, when the desired board access destination for port addresses that conflict with each other on multiple I/O boards is manually set using the hard switch (switch 2), the port addresses that conflict with each other on multiple I/O boards are manually set. When specified, normal access is allowed only to the desired I/O board.

Furthermore, when an arbitrary port address is output from the CPU 1 via the address bus 24, the address converter 23 converts it into a port address that conflicts with each other on a plurality of I/O boards, and converts it into a port address that conflicts with each other on a plurality of I/O boards. Allow normal access only to . [I/O board access destination setting process using soft switch] FIG. 2 shows the I/O board 13 and I/O board shown in FIG.
3 is a flowchart illustrating an example of a data read access processing procedure from the I/O port of the O board 14. FIG. In addition,
(1) to (9) indicate each step. Also, switch 2
It is assumed that the settings of the I/O port 13 and the settings of the I/O port 13 have been made in advance.

[0030] The CPU 1 is connected to the I/O board 13 or the I/O board 13 or
When attempting to read data from the I/O port of the O board 14, the CPU 1 first reads the data from the I/O ports of the I/O boards 13 and 14.
Sends the I/O port address Z common to the /O ports to the system bus (1). Next, the CPU 1 sets the read request signal 15 of the system bus to the LOW state (2). At this time, the state of the switch signal 17 which is the output of the switch 2 and the port output 18 of the I/O port 13 are both HI.
Check whether it is GH (3), and if YES, the read request signal 19 connected to the I/O board 13
LOW, and the read request signal 20 connected to the I/O board 14 remains HIGH (4)
. At this time, the I/O port of the I/O board 13 is
Since the address sent from 1 to the system bus matches its own address Z and the read request signal 19 is LOW, the I/O port of the I/O board 13 transfers the data to the system bus. (5) onto a bus (not shown). At this time, the I/O board 14
The /O port does nothing because the read request signal 21 remains in the HIGH state. Next, the CPU 1 reads the data on the system bus (8), returns the read request signal 15 on the system bus to the HIGH state (9), and ends the read operation. That is, at this time, CPU1 is I/O
Read the data of the I/O port of the board 13.

On the other hand, in the check in step (3), the switch signal 17 or the port output 18 of the I/O port 13
If any of the I/O board 1 is in the LOW state,
Only the read request signal 21 connected to I/O board 13 is set to the LOW state, and the read request signal 19 connected to the I/O board 13 remains at the HIGH state (6). At this time,
Since the address sent from the CPU 1 to the system bus matches its own address Z, and the read request signal 21 is in the LOW state, the I/O port of the I/O board 14 is not connected to the I/O port of the I/O board 14. The I/O port sends the data to the system bus (7), and the process proceeds to step (8), where the CPU 1 reads the data from the I/O port of the I/O board 14.

On the other hand, at this time, the I/O port of the I/O board 13 does nothing because the read request signal 19 remains in the HIGH state.

In this way, by changing the states of switch 2 and I/O port 3, two identical I/O
Data reading from I/O boards 13 and 14 having I/O ports with port addresses can be separated and data can be selectively read out. [I/O board access destination setting process using a hard switch] The I/O board access destination setting process will be described below with reference to the flowchart shown in Figure 3.
The process of writing data to the I/O ports of the /O board 13 and I/O board 14 will be described.

FIG. 3 is a flowchart showing an example of a procedure for data write access to the I/O ports of the I/O board 13 and I/O board 14 shown in FIG. Note that (1) to (9) indicate each step. Further, it is assumed that the settings of the switch 2 and the I/O port 13 have been made in advance.

[0035] The CPU 1 is connected to the I/O board 13 or the I/O board 13 or
When attempting to write data to the I/O port of the O board 14, the CPU 1 first writes data to the I/O port of the I/O boards 13 and 14.
Sends the I/O port address Z common to the /O ports to the system bus (1). Next, the CPU 1 sets the write request signal 16 of the system bus to the LOW state (2). At this time, the state of the switch signal 17 which is the output of the switch 2 and the port output 18 of the I/O port 13 are both HI.
Check whether it is GH (3), and if YES, the write request signal 20 connected to the I/O board 13
LOW, and the write request signal 22 connected to the I/O board 14 remains HIGH (4)
. Next, the CPU 1 sends data to be written to the I/O port to the system bus (5). At this time, I/O bow 1
Since the address sent from CPU 1 to the system bus matches its own address Z and the write request signal 20 is LOW, I/O port 3 is not connected to I/O port 3.
The I/O port of the /O board 13 reads data on the system bus (6). On the other hand, the I/O board 14 does nothing because the write request signal 22 remains in the HIGH state.

Next, the CPU 1 returns the write request signal 20 of the system bus to the HIGH state (10) and ends the write process. That is, data sent from the CPU 1 is written to the I/O board 13.

On the other hand, in the check in step (3), the switch signal 17 or the port output 18 of the I/O port 13
If any of the I/O board 1 is in the LOW state,
Only the write request signal 22 connected to I/O board 13 is set to the LOW state, and the write request signal 20 connected to the I/O board 13 remains at the HIGH state (7). Then,
Next, the CPU 1 sends data to be written to the I/O port to the system bus (8). At this time, I/O board 1
Since the address sent from the CPU 1 to the system bus matches its address Z, and the write request signal 22 is in the LOW state, the I/O port of the I/O board 14 is connected to the I/O port of the I/O board 14. reads the data on the system bus (9), the CPU 1 returns the write request signal 20 of the system bus to the HIGH state (10), and ends the write process. That is, data sent from the CPU 1 is written to the I/O board 14.

On the other hand, at this time, the I/O port of the I/O board 13 does nothing because the write request signal 20 remains in the HIGH state.

In this way, by changing the states of switch 2 and I/O port 3, two identical I/O
Data writing from the I/O boards 13 and 14 having I/O ports with port addresses can be separated and data can be selectively written. [I/O board access destination setting process by address converter 23] Hereinafter, with reference to the flowchart shown in FIG. 4, the I/O port access process of the I/O board connected to the I/O slot 26 by address conversion process will be explained. I will explain about it.

FIG. 4 shows the I/O slot 26 shown in FIG.
3 is a flowchart illustrating an example of an I/O port access processing procedure. Note that (1) to (5) indicate each step. The CPU 1 sets a specific address to be converted, which is indicated by the address signal 24, in the address converter 23 (1). Next, a translation address for the specific address is set (2). Next, the CPU 1 sends out the address before conversion (a specific address set so as not to be the same address as any other I/O port) (3). Next, the address converter 23 converts the address sent from the CPU 1 into a preset converted address (another I/O address).
(4) and sends the converted address to the I/O slot 26 (5)
. Thereafter, read access and write access are executed according to the flowcharts shown in FIGS. 2 and 3.

[0041] As a result, other I/O boards 13, 14
I/O with the same address as the I/O port address of
Even if the boards are installed in the I/O slots 26 at the same time, they can be accessed together with the other I/O boards 13 and 14.

In the above embodiment, switch 2 and I
As a means to change the state of /O port 3, NAND
Although a case has been described in which the arithmetic units 4 to 7, NOT arithmetic units 8 to 11, AND arithmetic unit 12, etc. are used, it is easy to construct the same means by appropriately combining other logical arithmetic devices.

[0043]

Effects of the Invention As explained above, the present invention provides a plurality of I
Since we have provided a setting means for setting in advance the desired board access destination for port addresses that conflict with each other on the /O board, even if multiple I/O boards are installed in each slot and port addresses that conflict with each other are specified, , normal access can be executed only to a desired I/O board set in advance.

Furthermore, since the setting means is constituted by a soft switch that sets a desired board access destination for port addresses that conflict with each other on a plurality of I/O boards based on the input board access destination designation state, the soft switch It is possible to easily switch and instruct access to a desired I/O board according to the data written to the board.

Furthermore, since the setting means is configured with a hard switch that manually sets the desired board access destination for port addresses that conflict with each other on multiple I/O boards, access to the desired I/O board can be made by the hard switch. can be reliably instructed.

Furthermore, since the setting means is constituted by an address converter that converts an arbitrary output port address into a conflicting port address, access to a desired I/O board can be executed by a pseudo port address instruction. be able to.

Therefore, the process of checking the I/O board installed in the I/O slot by the user before processing data can be greatly reduced. Furthermore, it is possible to easily instruct switching of I/O boards having conflicting port addresses in response to changes in the system environment. Furthermore, it is possible to prevent system runaway caused by a user's mistake in removing an I/O board from a slot.

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing the main configuration of a computer device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an example of a data read access processing procedure from an I/O port of the I/O board illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating an example of a procedure for data write access to an I/O port of the I/O board illustrated in FIG. 1;

FIG. 4 is a flowchart showing an example of an I/O port access processing procedure for the I/O slot shown in FIG. 1;

[Figure 5] CPU and I in this type of computer device
FIG. 3 is a block diagram illustrating the connection relationship with the /O channel.

FIG. 6 is a flowchart showing an example of an I/O port read access processing procedure by the CPU shown in FIG. 5;

7 is a flowchart illustrating an example of an I/O port write access processing procedure by the CPU illustrated in FIG. 5; FIG.

[Explanation of symbols]

1 CPU 2 Switch 3 I/O port 4 NAND operation unit 5 NAND operation unit 6 NAND operation unit 7 NAND operation unit 8 NOT operation unit 9 NOT operator 10 NOT operator 11 NOT operator 12 AND operator 13 I/O board 14 I/O board 23 Address converter 26 I/O slot

Claims (4)

[Claims] [Claim 1] An I/O board that can be installed with multiple I/O boards at the same time.
1. A computer device in which a /O channel can be connected to a system bus, characterized in that the computer device is equipped with a setting means for presetting desired board access destinations for port addresses that conflict with each other on a plurality of I/O boards. 2. The setting means comprises a soft switch that sets desired board access destinations for port addresses that conflict with each other in a plurality of I/O boards based on input board access destination instruction states. 2. The computer device according to claim 1. 3. The computer apparatus according to claim 1, wherein the setting means comprises a hard switch for manually setting desired board access destinations for mutually conflicting port addresses on a plurality of I/O boards. 4. The computer apparatus according to claim 1, wherein the setting means comprises an address converter that converts an arbitrarily output port address into a conflicting port address.