JPH04311066A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a device provided with a TFT and a capacitor to be efficiently formed by a method wherein a source, a drain, a channel, and the lower electrode of a capacitor are formed of the same material at a time, a gate insulating film and a capacitor insulating film are formed at the same time, ions are implanted into the lower electrode, and a gate electrode and the upper electrode of the capacitor are formed of the same material at a time. CONSTITUTION:A first polycrystalline silicon 102 is formed on a glass substrate 101 to serve as the source, the drain, and the channel region of a TFT and a lower electrode region of a capacitor. Then, polycrystalline silicon is thermally oxidized for the formation of an SiO 103, which is made to serve as the gate insulating film of the TFT and the insulating film of the capacitor. Next, a resist 104 is formed excluding the lower electrode region of the capacitor. Phosphorus ions are implanted to turn a polycrystalline silicon region which is not covered with resist into a conductive layer, which is made to serve as a lower electrode region 102' of the capacitor, and the resist is removed. Then, a second polycrystalline silicon is formed to serve as a gate electrode 105 and the upper electrode 105' of the capacitor.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a MOS type TFT (Th
in Film Transistor).

0002

2. Description of the Related Art In active matrix liquid crystal display devices using TFTs, an additional capacitor is usually connected to the TFTs that switch pixels, as shown in FIG. This is to improve the display performance of the liquid crystal display device by increasing the amount of charge held in the pixel electrode. FIG. 3 shows one pixel, 301 is a scanning line, 302 is a data line, 303 is a TF
It is T. 304 is a liquid crystal capacitor corresponding to the area of the pixel electrode, and 305 is the additional capacitor mentioned above. The structure of the capacitor consists of upper and lower electrodes and an insulating film between them. A TFT is usually a MOS type, and this structure usually consists of a semiconductor layer that constitutes a source, a drain, and a channel, a gate insulating film, and a gate electrode. Conventional techniques for manufacturing TFTs and the additional capacitance on the same substrate as efficiently as possible include:
There is a method in which the date insulating film of the TFT and the insulating film constituting the capacitor are simultaneously formed of the same material, and the gate electrode of the TFT and the upper electrode of the capacitor are simultaneously formed of the same material. but,
The lower electrode of the capacitor needs to be conductive, and in the prior art, the lower electrode of the capacitor was formed of a material different from the semiconductor material that constitutes the TFT. FIG. 2 shows a conventional technique for fabricating TFTs and capacitors on the same substrate as efficiently as possible, as described above. In FIG. 2, a conductive layer 202' that will become the lower electrode of the capacitor is formed on a glass substrate 201, then a semiconductor layer 202 that will become the source, drain, and channel of the TFT is formed, and then an insulating film 203 is formed. This is used as the gate insulating film of the TFT and the insulating film of the capacitor. Next, the gate electrode 205 of the TFT and the upper electrode 205' of the capacitor are formed simultaneously. Next, an interlayer insulating film 206 is formed, contact holes are opened, and necessary electrode wiring (207, 207') is formed.

0003

[Problem to be Solved by the Invention] However, in devices that require both a TFT and a capacitor, the above-mentioned prior art
Since the semiconductor layer serving as the source, drain, and channel of the FT and the conductive layer serving as the lower electrode of the capacitor are formed of different materials, there is a problem in that the number of steps increases. An increase in the number of steps causes problems such as increased cost and decreased yield.

0004

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides (1) a MOS type TF formed on an insulating substrate or an insulating film;
In a semiconductor device having a structure having a capacitor electrically connected to the MOS type TFT, the semiconductor layer forming the source, drain, and channel of the TFT and the semiconductor layer serving as the lower electrode of the capacitor are made of the same material. A gate insulating film of the TFT and an insulating film constituting the capacitor are simultaneously formed of the same material, and after the insulating film is formed, impurities are implanted into the semiconductor layer that will become the lower electrode region of the capacitor. The gate electrode of the TFT and the upper electrode of the capacitor are simultaneously formed of the same material.

(2) A step of forming a first polycrystalline silicon layer on an insulating substrate or an insulating film, which will become the source, drain, channel, and lower electrode of the capacitor, and then forming a gate insulating film and an insulating film that will form the capacitor. a step of simultaneously forming the first polycrystalline silicon by thermal oxidation or CVD, a step of forming a mask for ion implantation using a resist or the like, and a step of forming a lower electrode of the capacitor using the resist as a mask. a step of introducing impurities into the first polycrystalline silicon by ion implantation, a step of removing the resist, and then forming a gate electrode and an upper electrode of the capacitor from a second polycrystalline silicon, Next, an impurity of the same conductivity type as the impurity introduced into the lower electrode of the capacitor is introduced into the source and drain regions by ion implantation using the gate electrode and the upper electrode of the capacitor as a mask, and then interlayer insulation is performed. It is characterized by the steps of forming a film, then a heat treatment step to activate the ion-implanted impurities, then a step of opening a contact hole for taking out the electrode, and then forming an electrode wiring using Al or the like. shall be.

[0006]

[Example] FIG. 1 shows an example of the present invention.
A process for simultaneously forming a TFT and a capacitor is explained using cross-sectional views. In FIG. 1(a), the glass substrate 101
A first polycrystalline silicon 102 having a thickness of 100 nm is formed thereon to serve as the source, drain, and channel regions of the TFT and the lower electrode region of the capacitor. Next, by thermal oxidation of the polycrystalline silicon, SiO2 103 was formed to a thickness of 100 nm, and T
This is used as the gate insulating film of FT and the insulating film of capacitor. Said first
After the thermal oxidation, the film thickness of the polycrystalline silicon was reduced to about 45 nm.
The thickness will be m. Next, in FIG. 1B, a resist 104 is formed except for the portion that will become the lower electrode region of the capacitor. Next, phosphorus ions were implanted at an energy of 90 KeV and an implantation amount of 1×
1015/cm2 is implanted, and the polycrystalline silicon in the area not covered with the resist is made into a conductive layer and becomes the lower electrode region 102' of the capacitor. After ion implantation, the resist is removed. Next, as shown in FIG. 1C, a second polycrystalline silicon film having a thickness of 350 nm is formed to form the gate electrode 105 and the capacitor upper electrode 105'. Here, the distance between the ion-implanted region 102' and the gate electrode 105 must be set so that the implanted impurities do not diffuse and reach the channel region under the influence of all the heat treatment steps after the ion implantation. be. The value required for this setting may be 1 to 2 μm, and the TFT and capacitor can be made close to each other. Next, using the second polycrystalline silicon that constitutes the gate electrode and the upper electrode of the capacitor as a mask, second phosphorus ions are implanted at an energy of 90 KeV and an implantation amount of 2×1015/cm2.
Then, source and drain regions are formed. Further, the necessary electrical connection between the lower electrode of the capacitor and the TFT is also performed by the second ion implantation. Next, as shown in FIG. 1(d), a 500 nm thick SiO2 film 106 is formed by CVD to serve as an interlayer insulating film. Next, the implanted ions, which have been performed twice, are activated by a method such as lamp annealing. Next, contact holes are opened, and then electrode wirings 107 and 107' are connected to A.
Do it with l.

The above embodiment is a TF formed on a glass substrate.
V is based on T, but uses a silicon wafer as a substrate.
It can also be easily applied to LSI devices and three-dimensional circuit elements.

[0008]

[Effects of the Invention] As explained above, according to the present invention, T
A device including an FT and a capacitor can be efficiently and highly integrated with a small number of steps.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing a method of simultaneously forming a TFT and a capacitor according to the present invention.

FIG. 2 is a cross-sectional view showing the structure of a TFT and a capacitor according to the prior art.

FIG. 3 is a diagram showing one pixel of an active matrix LCD.

[Explanation of symbols]

101, 201 Glass substrate 102, 202 Polycrystalline silicon 102', 202' Capacitor lower electrode 103, 203 Insulating film 104 Photoresist 105, 105', 205, 205' Polycrystalline silicon 106, 206 Insulating film

Claims (2)

[Claims] Claim 1: M formed on an insulating substrate or an insulating film
In a semiconductor device having a structure having a capacitance electrically connected to an OS type TFT and the MOS type TFT, the TF
The semiconductor layer forming the source, drain, and channel of the TFT and the semiconductor layer forming the lower electrode of the capacitor are simultaneously formed using the same material, and the gate insulating film of the TFT and the insulating film forming the capacitor are simultaneously formed using the same material. and introducing impurities by ion implantation into the semiconductor layer that will become the lower electrode region of the capacitor after forming the insulating film, and simultaneously forming the gate electrode of the TFT and the upper electrode of the capacitor from the same material. A semiconductor device and its manufacturing method characterized by the following. 2. A step of forming a first polycrystalline silicon layer on an insulating substrate or an insulating film to become a source, drain, channel, and capacitor lower electrode, and then forming a gate insulating film and an insulating film constituting the capacitor. A step of simultaneously forming the first polycrystalline silicon by thermal oxidation or CVD, a step of forming a mask for ion implantation using a resist, and a step of forming the first polycrystalline silicon, which will become the lower electrode of the capacitor, using the resist as a mask. A step of introducing impurities into the first polycrystalline silicon by ion implantation, a step of removing the resist, and then a step of implanting the gate electrode and the upper electrode of the capacitor into the second polycrystalline silicon.
Next, an impurity of the same conductivity type as the impurity introduced into the lower electrode of the capacitor is introduced into the source and drain regions by ion implantation using the gate electrode and the upper electrode of the capacitor as a mask. The process of
Next, there is a step of forming an interlayer insulating film, a heat treatment step to activate the ion-implanted impurities, a step of opening a contact hole for taking out the electrode, and then forming an electrode wiring using Al, etc. A method for manufacturing a semiconductor device, characterized in that: