JPH04310040A - Data receiver - Google Patents

Abstract

PURPOSE:To implement interference compensation over a wide frequency range with respect to the revision in the frequency of an object interference wave by selecting an intermediate frequency band for the operating frequency band of a voltage controlled oscillator so as to widen the frequency variable range. CONSTITUTION:A PLL circuit comprising a voltage controlled oscillator 7, a low pass filter 8, a phase comparator 9, a phase shifter 10 and an orthogonal detector 1' is phase-locked to an output of an analog adder 11 being an extracted interference signal (f). Moreover, signals i,q being extracted interference wave signals whose jitter component is suppressed are outputted. The signals i,q are respectively converted into, e.g. 3-bit data signals d(D'1-D'3) by A/D converters 14,15 and outputted from an interference wave detection circuit 6. Since the frequency band of the oscillator 7 is selected to be an intermediate frequency band, the variable range of the frequency is widened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of Industrial Application The present invention relates to a data receiving apparatus that reproduces a data signal from orthogonally modulated waves in which signals modulated by other systems coexist as interference wave signals.

0002

[Prior Art] As is well known, in digital wireless communication,
For the purpose of high efficiency transmission, 16QAM (Quadratur)
e Amplitude Modulation)
, 64QAM, 256QAM, and other multi-value quadrature amplitude modulation methods are being developed and put into practical use, but transmission signals based on such multi-value quadrature amplitude modulation methods are susceptible to the effects of transmission signals based on other coexisting modulation methods. The problem is how to eliminate this interference.

[0003] As a conventional interference cancellation method, for example, the method described in Japanese Patent Laid-Open No. 1-095641 is known. FIG. 2 shows a specific example thereof, and its operation will be explained. The input signal is a four-value baseband signal (that is, when n=2), which includes an interference wave signal consisting of a signal wave based on another modulation method such as an FM wave. This input signal is converted by the AD converter 2 into a 6-bit (6-column) binary data signal. The output of the AD converter 2 is sent to the delay circuit 16
At the same time, a part of the error data signal f (D3 to D6) is provided to the interference wave extraction circuit 25. The interference wave extraction circuit 25 includes a DA converter 12, a bandpass filter 24, and an AD converter 14. DA converter 1
2 converts the data signal f (D3 to D6) into an analog signal and supplies it to the bandpass filter 24. Bandpass filter 2
4 suppresses various noises contained in the output of the DA converter 12, extracts interference wave signal components, and supplies it to the AD converter 14. The AD converter 14 converts the extracted interference wave signal into a binary signal and generates a 3-bit data signal d(D1'~
D3') and is applied to the multiplier 21 and the correlator 23. The delay circuit 16 consists of a shift register, for example, and receives data signals a (D1, D2) and f (D3 to D6).
) is subjected to delay processing to compensate for the time delay (bit shift) in the signal path from the interference wave extraction circuit 25 via the multiplier 21, and the delayed signal b is provided to the digital adder 18. The digital adder 18 adds this delayed signal b and the signal c output by the multiplier 21, and sends out the main data signals (D1, D2) as reproduced data, while
The error data signal e (D3 to D6) is given to the correlator 23. The correlator 23 receives the data signal d (D1' to D3'
) and the error data signal e (D3 to D6) to generate a multi-bit control signal by performing digital correlation processing and supplying it to the multiplier 21. The multiplier 21 responds to the multi-bit control signal to generate a digital signal d(D1' to D3'
) is weighted and given to the digital adder 18 as the multiplier output c. That is, the multiplier output c is controlled by the control signal so that it becomes a signal having the same amplitude level and opposite polarity as the interference wave signal included in the delayed signal b. As a result, the digital adder 18 receives the main data signals (D1, D
2) and error data signal e (D3 to D6).

0004

[Problems to be Solved by the Invention] Although it is possible to realize an efficient interference compensator using digital processing in the conventional example shown in FIG. It consists of a shaped filter, and has the disadvantage of not being able to respond flexibly to changes in the frequency of the target interference wave. Further, the filtering means includes a voltage controlled oscillator.
An LL circuit can be used, but even in that case, the voltage controlled oscillator used is in the baseband band, the frequency variable range is narrow, and very little effect can be expected.

The present invention eliminates these drawbacks and provides a digital receiver equipped with interference compensation means that can flexibly respond to changes in the frequency of the target interference wave over a wide frequency range. With the goal.

[0006]

[Means for Solving the Problems] The present invention provides a detection means for synchronously detecting an orthogonal modulated wave in which a modulated signal of another system coexists as an interference wave signal using a reference carrier wave, and an in-phase of the orthogonal modulated wave synchronously detected by this detection means. A conversion means for generating a data string consisting of main signal bits and error bits by multi-value identification of the components and orthogonal components; In the data receiving apparatus, the means for obtaining the extracted interference wave signal includes a voltage controlled oscillator controlled by a control signal, and quadrature detection of the output of the voltage controlled oscillator using the carrier wave. an analog-to-digital converter that digitally converts the output of the quadrature detector and outputs the extracted interference wave signal; and at least an in-phase component and a quadrature component of the quadrature modulated wave synchronously detected by the detection means. A digital-analog converter that converts one error bit into an analog quantity, and a phase comparator that compares the phases of the output of the digital-analog converter and the output of the quadrature detector to generate the control signal. It is characterized by

[0007] Here, the digital-to-analog converter has the following features:
This means converts each error bit of the in-phase component and quadrature component of the orthogonal modulated wave synchronously detected by the above-mentioned detection means, and calculates the sum of the outputs of this digital-to-analog converter and supplies this sum to the above-mentioned phase comparator. An adder may be provided.

[0008]

[Operation] The operation of digitally subtracting the main data signal containing the interference wave to obtain the extracted interference wave signal d for reproducing the main data signal is as follows. The output of the voltage controlled oscillator 7 is subjected to quadrature detection using the output of the voltage controlled oscillator 5, and i and q are output. The control signal of the voltage controlled oscillator 7 is obtained as the output of a phase comparator that compares the phase of the output obtained by digital-to-analog conversion of at least one signal f of the outputs of I' and Q' with at least one of i and q. It will be done. i and q as A
The D converters 14 and 15 perform analog-to-digital conversion to obtain an extracted interference wave signal d.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment according to the present invention. This embodiment, as shown in FIG. 6, low-pass filter 8, phase comparator 9, phase shifter 10, analog adder 11, DA converters 12 and 13, delay circuits 16 and 17, and digital adder 1
8 and 19, multipliers 20 and 21, and correlator 22
and 23. That is, in this embodiment, FIG.
As shown in FIG. 1, a quadrature detector 1, a logic circuit 4, and a voltage controlled oscillator 5 are used as detection means for synchronously detecting a quadrature modulated wave in which a modulated signal of another method coexists as an interference wave signal using a reference carrier wave.
and AD converters 2 and 3, which are conversion means for generating a data string consisting of main signal bits and error bits by performing multi-value discrimination on the in-phase component and the orthogonal component of the orthogonal modulated wave synchronously detected by the detection means; a delay circuit 16 which is interference compensation means for digitally subtracting the weighted extracted interference wave signal from the data string output by the conversion means to reproduce the main data signal;
, 17, digital adders 18, 19, multipliers 20, 21
, correlators 22 and 23 and an interference wave extraction circuit 6,
Further, as a feature of the present invention, the interference wave extraction circuit 6, which is the means for obtaining the extracted interference wave signal, includes a voltage controlled oscillator 7 controlled by a control signal, and an output of the voltage controlled oscillator 7 that is connected to the carrier wave. a quadrature detector 1' that performs orthogonal detection, and an AD converter 14 and 1 that digitally converts the output of this quadrature detector 1' and outputs the extracted interference wave signal.
5, a DA converter 12 or 13 that converts error bits of at least one of the in-phase component and the orthogonal component of the orthogonal modulated wave synchronously detected by the detection means into an analog quantity, and the output of this DA converter 12 or 13. Quadrature detector 1 above
A phase comparator 9 is provided for generating the control signal by comparing the phase with the output of '. Further, the digital-to-analog converters are DA converters 12 and 13 which are means for converting error bits of the in-phase component and the orthogonal component of the orthogonal modulated wave synchronously detected by the detection means, respectively. It is also possible to provide an analog adder 11 that calculates the sum of the outputs of 13 and supplies this sum to the phase comparator 9.

Next, the operation of this embodiment will be explained. FM
The 16QAM wave, which includes interference waves of other modulation methods such as waves, is synchronously detected by the quadrature detector 1 using the reference carrier wave from the voltage controlled oscillator 5, and converted into I and Q four-level baseband signals. These I and Q signals are converted into 6-bit (6 columns) binary data by AD converters 2 and 3, respectively. This 6-bit binary data signal is converted into the most significant bit (MSB).
) to the second bit of data signal a (D1, D2
) and the data signal f(D
3 to D6), the data signal a(D1,
D2) corresponds to the main data signal, and the data signal f(D3
~D6) corresponds to the error data signal. This data signal f (D3 to D6) indicates how much the four-level input signal deviates from its original level, and includes the interference wave signal. Therefore, the outputs of AD converters 2 and 3 are output from delay circuits 16 and 1, respectively.
7, and the data signal f is provided to the interference wave extraction circuit 6. Furthermore, among the outputs of the AD converters 2 and 3, D1 and D2 enter the logic circuit 4, where a phase control signal for controlling the voltage controlled oscillator 5 is created. The configuration and operation of the logic circuit 4 are detailed in, for example, Japanese Patent Laid-Open No. 57-131151 (57.8.13) ``Carrier Regeneration Circuit''.

Next, the interference wave extraction circuit 6 which is a feature of the present invention
I will explain about it. Of the outputs of the AD converters 2 and 3, the f signal is converted into an analog quantity by the DA converters 12 and 13, then added by the analog adder 11, and input to the phase comparator 9. The other input signal of the phase comparator 9 is obtained by passing the output i and q signals of the quadrature detector 1' through a phase shifter 10. The output of the phase comparator 9 controls the voltage controlled oscillator 7 after high-frequency jitter components are removed by the low-pass filter 8. The frequency band of the voltage controlled oscillator 7 is the same as that of the interference wave signal included in the input 16QAM wave, and the output of the voltage controlled oscillator 7 is converted into the reference carrier of the voltage controlled oscillator 5 by the quadrature detector 1'. If orthogonal detection is performed by
It has the same frequency as the output of the analog adder 11, which is the interference wave extracted from the 6QAM signal. Therefore, the PLL circuit composed of the voltage controlled oscillator 7, the low-pass filter 8, the phase comparator 9, the phase shifter, and the quadrature detector 1' outputs the phase of the output of the analog adder 11, which is the extracted interference wave signal. It is possible to output i and q signals as extracted interference wave signals that are synchronized and have jitter components suppressed. The i and q signals are finally converted into 3-bit data signals d (D1' to D3') by AD converters 14 and 15, respectively, and output from the interference wave extraction circuit 6. Here, d
Although the signal is assumed to be 3 bits, a value around this value can be selected taking into consideration the characteristics and circuit scale. Since the frequency band of the voltage controlled oscillator 7 can be selected as the intermediate frequency band as described above, the frequency can be varied over a wide range.

Although FIG. 1 shows a configuration in which I' and Q' are used as inputs to the phase comparator 9, either one can be operated. Further, the phase shifter 10 provided at the other input of the phase comparator 9 can have a resistor addition configuration, and the phase can be changed by changing the value thereof. By changing this phase, the phase of the extracted interference signals i and q can be changed, and is used to adjust the phase at the input points of the digital adders 18 and 19, but depending on the circuit configuration, it may not be necessary. . In that case, i or q is directly connected to the phase comparator 9
All you have to do is enter it.

The i and q d signals of the interference wave extraction circuit 6 (
D1' to D3') are input to multipliers 20, 21 and correlators 22, 23, but the delay circuit 16 shown in FIG.
The operation of the circuit composed of the digital adder 18, multiplier 21, and correlator 23 and the circuit composed of the delay circuit 17, digital adder 19, multiplier 20, and correlator 22 is shown in FIG.
Delay circuit 16, digital adder 18, and multiplier 21 shown in
, the operation is similar to that of the circuit composed of the correlator 23.

[0014]

[Effects of the Invention] As explained above, the present invention selects an intermediate frequency band as the operating frequency band of the voltage controlled oscillator, and can widen the frequency variable range, so that it is possible to change the frequency of the target interference wave. This has the effect of being able to respond flexibly over a wide frequency range.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing the configuration of a conventional example.

[Explanation of symbols]

1, 1' Quadrature detector (QAMDET) 2, 3, 14, 15 AD converter (AD) 4 Logic circuit (LOGIC) 5, 7 Voltage controlled oscillator (VCO) 6, 25 Interference wave extraction circuit 8 Low-pass filter (Fs) 9 Phase comparator (PHDET) 10 Phase shifter (φ) 11 Analog adder (+) 12, 13 DA converter (DA) 16, 17 Delay circuit (SR) 18, 19 Digital adder (+) 20, 21 Multiplier (×) 22, 23 Correlator (×) 24 Bandpass filter (Fb)

Claims (2)

[Claims] 1. Detection means for synchronously detecting orthogonal modulation waves in which other modulation signals coexist as interference wave signals using a reference carrier wave, and multi-value identification of in-phase and orthogonal components of the orthogonal modulation waves synchronously detected by the detection means. a converting means for generating a data string consisting of main signal bits and error bits; and an interference compensating means for digitally subtracting a weighted extracted interference wave signal from the data string output by the converting means to reproduce the main data signal. In the data receiving device, the means for obtaining the extracted interference wave signal includes: a voltage controlled oscillator controlled by a control signal; a quadrature detector that orthogonally detects the output of the voltage controlled oscillator using the carrier wave; an analog-to-digital converter that digitally converts the output of the detector and outputs the extracted interference wave signal; and an analog-to-digital converter that digitally converts the output of the detector and outputs the extracted interference wave signal; A data receiving device comprising: a digital-to-analog converter; and a phase comparator to generate the control signal by comparing the phases of the output of the digital-to-analog converter and the output of the quadrature detector. 2. The digital-to-analog converter is means for converting error bits of the in-phase component and the orthogonal component of the orthogonal modulated wave synchronously detected by the detection means,
2. The data receiving apparatus according to claim 1, further comprising an analog adder which calculates the sum of the outputs of the digital-to-analog converter and supplies this sum to the phase comparator.