JPH04307974A - Electrically erasable nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To contrive an increase in the integration of the title device by a method wherein floating gates are respectively divided functionally into a write site and an erase site and in the sides of the erase sites, a tunnel oxide film is provided to constitute the erase sites without providing a source offset and in the sides of the write sites, a source offset is provided to constitute the write sites. CONSTITUTION:One pair of L-shaped floating gates 2 consisting of a polysilicon film are respectively provided on gate regions between a source line 3 in the surface of a silicon substrate and one pair of drain lines 4 and 4 arranged on both sides of the line 3 via an insulating film. Moreover, control gates 5 consisting of a polysilicon film to the gates 5 are respectively provided on the gates 2 via an interlayer insulating film. In one pair of write sites, writing using an injection of electrons from the side of each drain to each gate 2 is performed. On the other hand, in the erase sites, erase using an F-N tunneling is performed en bloc from the side of a source to the gates 2 and 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrically erasable nonvolatile semiconductor memory devices (EEPROMs). More specifically, the present invention relates to an EEPROM element structure suitable for high integration.

0002

2. Description of the Related Art Hitherto, electrically erasable non-volatile semiconductor memory devices (EEPROMs) of various structures have been known, all of which have so-called floating gates and which can be used for writing by hot electrons or for F-N (F-N).
(Fowler-Nordheim) uses erase/write by tunneling.

[0003] And selection gate
The so-called early stacked gate EEPRO without
In M, writing is performed by hot electrons from the drain side, and erasing is performed by FN tunneling from the source side.

However, in this way, F
A structure in which data is erased by -N tunneling has the disadvantage that over-erasing often occurs, resulting in depletion of the memory cell.

[0005] For this reason, it is often done to prevent the above-mentioned over-erasing by combining select gates.

[0006]

However, when the selection gate is provided independently, the area occupied by the memory cell increases, and the degree of integration of the EEPROM is significantly reduced.

[0007] Therefore, it is conceivable to provide an offset between the source line and the floating gate constituting the EEPROM, and to arrange the selection gate on this offset portion.

However, in this case, due to the existence of the offset width, the F between the source and the floating gate is
-N tunneling was difficult to occur, and data could not be erased smoothly. Further, in this case, it is possible to utilize FN tunneling between the drain and the floating gate, but in order to achieve this, it is necessary to apply a relatively high voltage to the drain. Therefore, it is necessary to increase the drain junction breakdown voltage to prevent leakage current, and to do so, it is necessary to smooth the concentration profile of the drain junction, but in this case, the hot electron generation efficiency There was an inconvenience that the write characteristics deteriorated.

The present invention was made under such circumstances, and it is an object of the present invention to provide a structure that enables erasing by FN tunneling from the source side even in an EEPROM in which a selection gate is configured in the source side offset section. That is.

0010

[Means for Solving the Problems] According to the present invention, there is provided a source region, a pair of drain regions disposed on both sides of the source region, a pair of gate regions disposed between these regions, and a pair disposed on the gate regions. a floating gate and a control gate disposed on the floating gate, each of the pair of floating gates (a) being located on the gate region via a source offset to form a pair of drain drive write sections; (b) an erase region located on tunnel oxide films disposed on both sides of the source and forming one source drive erase region, and the control gate is connected to the pair of floating An electrically erasable nonvolatile semiconductor memory device is provided which is arranged to commonly cover a write region of a gate and a source offset.

In order to solve the above problems, the present invention functionally divides the floating gate into a writing region and an erasing region, and on the erasing region side, a tunnel oxide film is provided without providing a source offset, thereby forming a single erasing region. consists of
On the write site side, a source offset is provided to form a pair of write sites.

0012

[Operation] In the drain drive write section, a source offset is ensured, and the control gate on this offset can be used as a selection gate, and hot electrons are injected from each drain side that does not have an offset. Each writing is performed smoothly.

On the other hand, since there is no source offset in the source drive erase section, F-N tunneling is performed from the source side through tunnel oxide films disposed on both sides of the source region, resulting in smooth erase. This will be done all at once.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments shown in the accompanying drawings.

FIG. 1 shows an EEPRO according to an embodiment of the present invention.
FIG. 2A is a planar configuration explanatory diagram showing M, FIG. 2A is a cross-sectional explanatory diagram taken along the line AA' in FIG. 1, and FIG. 2B is a cross-sectional explanatory diagram taken along the line B-B' in FIG.

As shown in these figures, the EE of the present invention
PROM has a pair of L-shaped floating gates made of polysilicon placed on a gate region between a source line 3 on the surface of a silicon substrate and a pair of drain lines 4 arranged on both sides of the source line with an insulating film interposed therebetween. 2 is arranged,
Further, a common control gate 5 made of polysilicon is disposed on the floating gate 2 via an interlayer insulating film.

As shown in FIG. 2(A), the floating gate 2 has a pair of writing regions located on the gate oxide films 1, 1 in the gate region while maintaining the source offset 9 in the AA' cross section. (narrow width part). Here, it is suitable that the source-drain width is 1.6 to 2.0 μm and the source offset is 0.8 to 1.0 μm. The control gate 5 on such a write site also functions as a selection gate on each source offset.

On the other hand, as shown in FIG. 2(b), BB'
In cross section, it has erased portions (wide portions) covering tunnel oxide films 6 disposed on both sides of source line 3. Note that in the figure, 7 is an element isolation region made of a LOCOS oxide film.

In the EEPROM having such a structure, writing is performed by injecting hot electrons from the drain side to the floating gate at each of the pair of write portions. Then, in the erased portion, erasing is performed by FN tunneling from the source side to both floating gates 2, 2 at once. Then, the above hot electron injection and F-N
Tunneling is controlled using the control gate as a selection gate.

The EEPROM shown in FIG. 1 can be manufactured, for example, as follows. First, as shown in FIG. 3, an element isolation region 7 is formed in a predetermined region of a silicon substrate by the Locos oxidation method, and then ion implantation of the source configuration line of the memory cell and arsenic ion implantation are performed to form a DDD structure. Form a source line. A gate oxide film 1 with a thickness of, for example, 200 to 300 Å is formed on the entire surface by thermal oxidation, and a window for a tunnel oxide film is formed in a part of the gate oxide film 1 by photolithographic patterning and etching. After removing , a pair of tunnel oxide films 6 are formed by thermal oxidation.

Next, by depositing polysilicon on the entire surface by CVD, diffusing N-type impurities, and photo-etching, a pair of L-shaped regions each having a narrow width region and a wide region are formed as shown in FIG. Floating gate 2 is formed.

After the floating gate 2 is formed, as shown in FIG. 6, arsenic ions are implanted into the drain forming line of the memory cell by photolithography using a photoresist 8 to form a drain line.

After that, an interlayer insulating film (SiO2) is formed by CVD on each writing part of the floating gate 2, and then an N-type impurity is diffused into the deposited polysilicon layer, and the deposited layer is patterned and etched by photolithography. By doing this, the control gate 5 is formed as shown in FIG.
A PROM is obtained.

[0024]

As described above, according to the EEPROM of the present invention, even when the offset section on the source side is used as a selection gate, the erasing operation can be performed more smoothly than on the source side, so an independent erasing gate is provided. The area occupied by the memory cell is significantly reduced compared to the conventional case, and it becomes possible to further increase the integration of the EEPROM.

Furthermore, it is possible to separately optimize the drain junction, which has a high hot electron generation efficiency, and the source junction, which has a small leakage current even at high voltages for erasing. Therefore, from the viewpoint of manufacturing an electrically erasable nonvolatile semiconductor memory device that writes data using hot electrons from the drain side and erases data from the source side using F-N tunneling, the design is easier and the manufacturing process is also easier. You can also get

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a planar configuration of an EEPROM according to an embodiment of the present invention.

2A is an explanatory cross-sectional view taken along the line AA' in FIG. 1, and FIG. 2B is an explanatory cross-sectional view taken along the line B-B' in FIG.

FIG. 3 is a layout diagram showing a manufacturing process of the EEPROM shown in FIG. 1;

FIG. 4 is a layout diagram following FIG. 3;

FIG. 5 is a layout diagram following FIG. 4;

FIG. 6 is a layout diagram following FIG. 5;

FIG. 7 is a layout diagram following FIG. 6;

[Explanation of symbols]

1 Gate oxide film 2 Floating gate 3 Source line 4 Drain line 5 Control gate 6 Tunnel oxide film 7 Element isolation region 8 Photoresist 9 Source offset

Claims (1)

[Claims] 1. A source region, a pair of drain regions disposed on both sides of the source region, a pair of gate regions disposed between these, a pair of floating gates disposed on the gate regions, and a pair of floating gates disposed on the floating gates. each of the pair of floating gates includes: (a) a write region located above the gate region via a source offset and forming a pair of drain drive write portions; erase portions that are located on tunnel oxide films disposed on both sides and constitute one source drive erase portion, and the control gate has a write portion and a source offset of the pair of floating gates in common. an electrically erasable nonvolatile semiconductor memory device arranged to cover the electrically erasable semiconductor memory device;