JPH04307867A - Picture processor and method therefor - Google Patents

Abstract

PURPOSE:To obtain high-resolution data by referring to data of the n-th line and data of the (n+1)th line in the subscanning direction of received data to generate interpolation data between them and interpolating picture element data. CONSTITUTION:A smoothing part 41 discriminates whether printing is started in a recording part 38 of a facsimile equipment or not. Two-line components of picture data are written in a two-line FIFO 100, and data of the first line is read out from the FIFO 100, and data of the first line and the second line are referred to generate interpolation data. Next, data of the second line is read out from the FIFO 100, and it is discriminated whether picture data of all lines are completely read out or not. If they are not completely read out, picture data of the next line is written in the FIFO 100 from a buffer memory 40, and a program reads out the next line. This operation is repeated till the end of read of picture data of all lines.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method thereof, and more particularly to an image processing apparatus and method capable of interpolating low-resolution image data and outputting high-resolution data. .

0002

[Prior Art] A facsimile machine has multiple resolutions,
For example, 16 x 15.4, 8 x 7.7, 8 x 3.85 (
The unit is book/mm. The same applies hereinafter), etc., and the receiving side is equipped with a recording device that can receive data at the highest resolution (16 x 15.4). One way to use such a device is to use it in a low resolution mode such as 8×3.85 in order to shorten communication time or reduce signal data. However, when receiving a signal in such a low resolution mode, the recording device operates with a recording function at the highest resolution, resulting in areas where data is missing. In order to eliminate such inconveniences, interpolation processing is generally performed. An example of this interpolation processing will be explained next.

FIG. 13 is a diagram showing an example of data interpolation processing described in Japanese Unexamined Patent Publication No. 61-242467.

Referring to FIG. 13, a predetermined low resolution pixel data area is divided into a plurality of areas in a matrix,
Data interpolation is performed for each divided area. As a result, smooth high-resolution image data can be obtained based on the image data received at low resolution.

[0005]

Conventionally, interpolation of image data from low resolution to high resolution has been performed as described above. In this case, the following problems occur.

Referring to FIG. 12, when an image (a) with ruled lines such as a report sheet or a table is transmitted by facsimile, the image may become stepped as shown in (b). At this time, if data is interpolated using a matrix as described in the prior art, smoothing is performed only in a very limited portion as shown in (c). As a result, there is a problem in that a smooth image cannot be obtained, especially when an image with diagonal lines is received.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an image processing device and method that can smoothly interpolate data over the entire line in the sub-scanning direction. shall be.

[0008]

Means for Solving the Problems According to claim 1 of the present invention, an image processing device for converting low resolution image data into high resolution image data and storing the converted image data converts received image data into at least two lines in the sub-scanning direction. The storage means stores data for each line of nth line and nth line of data for each line.
Data for the +1st line is sequentially written, a reference means for referencing the data for the nth line and the data for the n+1st line written in the storage means, and data for interpolating the data for the line between them based on both referenced data. and an interpolation means, and outputs high-resolution data based on the interpolated data.

A resolution conversion method for converting low-resolution image data into high-resolution image data according to claim 2 of the present invention provides image data at the same position in the line direction in each line for two adjacent lines of low-resolution image data. Compare them, detect the range where the two lines of image data do not match, and if the two lines of image data match,
The data that is the same as the data on both lines is determined as the data between the two lines of data, and for areas where the two lines of image data do not match, the data on the two lines is determined based on at least the data adjacent to both sides of the detected range. The data between the lines is determined, and each determined data is output as data between the two lines.

0010

[Operation] According to the present invention, the received nth
Interpolation data between the data on the line and the data on the (n+1)th line is created with reference to the data on the (n+1)th line, and pixel data is interpolated. This situation is shown in FIG.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a laser facsimile apparatus to which the present invention is applied. Referring to FIG. 1, the laser facsimile apparatus includes a document reading section 1 for sending and a recording section 38 for receiving.

In the document reading section 1, the document on the platen 2 is irradiated with a light source 3 and a scanner 4 is moved to scan the document. The reflected light from the original is reflected by a mirror and enters a linear CCD sensor (for example, 8 pixels/mm) 6 via a lens 5. The output signal of the linear CCD sensor 6 is digitized as explained later, and then binarized. Note that the configuration can be simplified if the reading is performed using a moving document type.

In the recording section 38 , the laser optical system 12 controls the light emission of the laser diode in response to the received signal, and the light is incident on the photoreceptor 13 . Then, development, transfer, and fixing are performed using a well-known electrophotographic process, and the received signal is printed on plain paper.

The reading and printing operations described above are similar to those of conventional laser printers, so a detailed explanation will be omitted.

Next, an outline of the operation of the facsimile will be explained with reference to FIG. First, the operation of the calling side will be explained. Photoelectric conversion section 31 including linear CCD sensor 6 of reading section 1
The original is converted into an electrical signal. Next, the processing section 32
A predetermined binarization process (dither process, etc.) is performed on the signal, and the signal is converted into a binary time series signal. The converted data is temporarily stored in the buffer memory 40. Next, the data read from the buffer memory 40 is processed into the MH by the compression unit 33.
, MR, etc. The encoded signal is then stored in code memory 34. The transmission control section 35 establishes a connection with the called side, and sends out the signal in the code memory 34 to the line through the line connection section 36 according to a predetermined procedure.

Next, the operation of the called side will be explained. When the transmission control unit 35 receives a connection request from the calling side through the line connection unit 36, it connects the line, receives the signal, and
Accumulate to 4. The decompression unit 37 encodes the signal in the code memory 34, and the buffer memory 40 temporarily stores this signal. Next, the smoothing unit 41 performs interpolation of the image data so that the image becomes smooth as described below.
The received signal is recorded via the recording section 38.

Note that the control section 39 controls the above signal processing in response to instructions from the operation display section 51.

FIG. 3 shows a CPU that controls a facsimile machine.
It is a control block diagram around 71. The CPU 71 includes a working RAM 72, a timer clock IC 73, and a ROM.
74, connected to PIU75. In addition, the CPU 71
The key matrices 52 to 58 of the operation display section 51 and the LC
It is connected to the D display section 59 and to each control section (see FIG. 2).

FIG. 4 shows the CPU 71 that controls the facsimile.
2 is a flowchart showing the main flow of FIG. In step S1, initial settings after resetting the CPU 71 are performed. In step S2, input/output processing of the CPU 71 is performed. In step S3, the control mode indicating the control state is checked and the process branches. If the control mode value is 0, go to step S4; if it is 1, go to step S
If it is 2 to 5, proceed to step S6. In the standby mode of step S4, the device waits for an incoming signal by key operation or reception. When the device is performing reception processing, it passes through the reception mode of step S5. For example, in the transmission mode or when processing other than the reception mode, such as registration of one-touch dialing, the other processing of step S6 is performed. After each process ends, the program returns to step S2.

FIG. 5 is a flowchart showing the contents of the standby mode processing shown in step S4 of FIG. In step S101, input of an incoming signal is checked. When an incoming call signal is input, the process advances to step S102, the control mode is set to 1, and the program returns. If no incoming call signal is input, the program proceeds to step S103, performs other processing, and returns.

Next, details of the smoothing section according to the present invention will be explained with reference to FIG.

Referring to FIG. 6, the smoothing unit 41 according to the present invention has a two-line FIFO that stores image signals from the buffer memory 40 one line at a time in the sub-scanning direction.
an adder 102 that is connected to 100 and reads out two lines of data at the same time; an adder 102 and a two-line FIFO;
a determination circuit 101 that receives data from 100 and outputs a signal for interpolating data between those two lines;
A latch circuit 105 that latches the image signal from the 2-line FIFO 100, and the latch circuit 105 and the determination circuit 101.
It includes a selector 106 that selects desired image data in response to a select signal from the selector 106, and a latch circuit 107 that receives the signal from the selector 106, latches the image data, and sends out the image data to the recording unit 38. The smoothing section 41 further includes a 2-line FIFO 100 and a determination circuit 1.
01 and a latch clock control 110 connected to a latch circuit 105.

Next, the operation of the smoothing section 41 will be explained with reference to FIG.

First, it is determined whether or not printing has started in the recording section 38 of the facsimile machine (step S11, hereinafter steps will be omitted). Next, 2 line FIF
Two lines of image data are written to O100 (S1
3). Next, the first line data is stored in a 2-line FIFO10
The data is read from 0 (S15), and interpolation data is created with reference to the first and second lines (S17). Next, the second line of data is further read out from the two-line FIFO 100 (S19), and it is determined whether reading of all lines of image data has been completed (S21). If reading of all lines has not been completed in S21, the image data of the next line is written from the buffer memory 40 to the 2-line FIFO 100 (S23), and the program proceeds to reading of the next line in S15. The above operations are continued until reading of image data for all lines is completed (S21).

Next, details of the interpolation data creation subroutine shown in step S17 in FIG. 7 will be explained with reference to FIGS. 6 and 8. In this routine, it is first determined whether the lower output of the adder 102 is 0 (S3
1). Here, the adder 102 adds the data of the lth line and the data of the next (l+1)th line. That is, S31
If the lower output of the adder is 0, it means that the lth line and l+
Indicates that the data on the first line match.

If the data of the l-th line and the data of the l+1-th line match in S31, the interpolation data may be the same as the data of the l line, so the processing from S33 onwards is performed. First, the l-th line data of the 2-line FIFO 100 is stored in a register in the determination circuit 101 (S33). This is used to determine whether or not there has been a change in the image data of the 1st line in order to create interpolated data from the image processing data of the 1st line in the processes of S49 to S53, which will be described later. Next, from the determination circuit 101 to the selector 10
3 and the select signal 1 outputted to the up/down counter 104 are set to 0, and the select signal 2 outputted from the determination circuit 101 to the selector 106 is set to 0 (S37).

Here, the select signal 1 is the selector 10
3 to select the read clock to the FIFO 100 between a clock with a normal frequency (hereinafter simply referred to as CK) and a clock with twice the frequency (hereinafter referred to as 2CK), and to switch up and down of the up-down counter 104. used for. When the select signal 1 is 1, the read clock 2CK is set and the counter 10
A count up of 4 is performed, and when it is 0, it is set to CK, and if the count value is not 0, a count down is performed.

Select signal 2 is a signal for selecting whether to invert and output the data from latch circuit 105 or to output it without inverting. When select signal 2 is 1, an inverted signal is output. . It is determined whether the up/down counter 104 is counting down (S39). If the countdown is in progress, the output of the latch clock from the latch clock control circuit 110 to the latch circuit 105 is stopped, and the current data is held (S41
). If the countdown is not in progress in S39, the stoppage of the latch clock to the latch circuit 105 is released, and new data can be written (S43).

Note that during the countdown, the read enable signal (read enable signal) RE bar (bar line drawn above RE) output from the up/down counter 104 becomes inactive, and the image data from the FIFO 100 is Output is prohibited.

If the lower output of the adder is not 0 in S31, the data on the lth line and the data on the l+1th line do not match, so first the value of the first half of the interpolated data between them is output. First, select signal 1 is set to 1 (S47),
The FIFO read clock is set to 2CK, and the up/down counter 104 is also counted up. Subsequently, it is determined whether the current output value of the l-th line of the two-line FIFO 100 is the same as the value (D) stored in the register in the determination circuit 101 (S49). In other words,
When the image data of the l line and the l+1 line differ, it is determined whether or not there has been a change in the image data of the l line.

If YES is determined in S49, the select signal 2 output from the determination circuit 101 to the selector 106 is set to 0, and the signal from the latch circuit 105 is output as is. On the other hand, when the determination is NO, the select signal 2 is set to 1, and an inverted signal of the signal from the latch circuit 105 is output. When the above steps are completed, it is determined in S45 whether one line has been completed, and if it has not been completed, the program proceeds to S31.

Note that when the select signal 1 is set to 1 to start counting up, and then the select signal 1 is set to 0 to start counting down, the read permission signal RE becomes "H" and the data is The circuit within up/down counter 104 is configured so that reading is impossible.

Next, a more specific operation of the smoothing section 41 will be explained with reference to FIGS. 9 and 10. Figure 9 is a timing chart of each signal, and Figure 10 is a 2-line FI
Data in the FO 100, adder 102, and printer output are shown for each dot. The numerical values 0 and 1 shown in FIG. 10 and the data output numbers n-2 to n to n+7 in the sub-scanning direction correspond to each other.

Here, a case will be explained in which an image sent with a resolution of 8×7.7 is outputted by a printer with a resolution of 16×15.4 (lines/mm).

Note that the read enable signal RE bar and the clocks CK and 2CK are controlled by the select signal 1 outputted from the determination circuit 101 through an up/down counter 104 and a selector 103, respectively.

2 read from the 2-line FIFO 100
Line data a-1 and a-2 are input to the adder 102, and the upper bit (b-2) and lower bit (b-1)
The signal is input to the determination circuit 101 as follows. Two lines of data a-1 and a-2 are also input at the same time. A signal indicating the resolution mode is also input. Based on these data, the determination circuit 101 controls the read clock CK of the 2-line FIFO 100, the read enable signal RE, and the selector 106. The read data for l lines is input to the latch circuit 105, synchronized with the output of the determination circuit 101, and then sent to the selector circuit 10 together with the inverted data.
6 is input. Then, the selector circuit 106 selects whether to output the inverted data or the unchanged data using the select signal 2, and the printer clock (C
16 lines/mm in the main scanning direction using a clock with a period twice that of K
Then, data is input to the recording section 38.

To the 2-line FIFO 100 a-1 in FIG.
, a-2, the output from the adder 102 becomes the values shown as b-1 and b-2. Then, this value is controlled by the determination circuit 101, and printer outputs as shown by c-1 to c-3 are obtained from the recording section 38.

Next, a detailed explanation will be given with reference to the timing chart of FIG. First, when outputting the l-th line data, the read clock of the 2-line FIFO 100 is CK.
Then, the read enable signal RE is always activated, the selector circuit 106 is selected to 0, and the data output in the main scanning direction is simply doubled. Next, interpolated line data is created from the l-th line image data. In other words, the same line will be read twice. 1st line, 1st line
When both +1 lines are “0”, it remains “0”
Output. At this time, a value of "0" is stored in a register within the determination circuit 101.

Next, when the lth line becomes "1" and the l+1th line becomes "0", the lower bit of the adder 102 becomes "1".
become. Based on this and other input signals, the determination circuit 101 makes a decision, sets the select signal 1 to "1", and sets the read clock to 2CK. In both cases, the count value of the up/down counter 104 is incremented by 2CK. and the lth
This state is maintained while the line is "1" and the (l+1)th line is "0". At this time, the value "0" in the above register and the value "1" on the 1st line are compared, and since they are different values,
Select signal 2 is "1" and selects the inverted signal. If the lth line is "0" and the l+1th line is "1", the select signal 2 becomes "0". Thereafter, with data n+4, both the 1st line and the 1+1st line become "1". At this time, the select signal 1 is returned to "0", the clock signal CK is selected again, and the up/down counter 104 starts counting down. During this down count, the read enable signal RE becomes "1" and the 2-line FIF
Reading of data from O100 is prohibited, the clock to the latch circuit 105 is stopped, and new writing to the latch circuit is prohibited. At this time, select signal 2 is “
0", the output data becomes "1". In other words, the data is read out at twice the speed. During this time, the data is inverted, and if both the 1st line and the 1+1th line become 1, it is read out at twice the speed. Interpolated line data is obtained by not reading data for a certain period. An example of interpolation performed in this way is shown in Fig. 12(d).Compared to the conventional example (c), data interpolation is smoother. It is being done.

[0041] Above, from 8 x 7.7 lines/mm to 16 x 15
．． I mentioned the case where data is interpolated to 4 lines/mm,
The same method can be used to change the size from 8×3.85 lines/mm to 16×15.4 lines/mm.

Note that in the above embodiment, data interpolation was performed by referring to two lines, the 1st line and the 1+1th line, but if data interpolation was performed by referring to 3 lines, curved images could also be interpolated. Favorable interpolated data is obtained.

[0043]

As described above, according to the present invention, pixel data of a previous line and a subsequent line can be referenced in an image processing device and an image processing method that convert received low-resolution image data into high-resolution image data and store it. Then, the pixel data of the lines between them are interpolated. One line of data to be interpolated is created by referring to the data before and after it.

As a result, it is possible to provide an image processing apparatus and an image processing method that can perform smooth interpolation over the entire line in the sub-scanning direction.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a laser facsimile device to which the present invention is applied.

FIG. 2 is a block diagram illustrating an outline of the operation of a facsimile.

FIG. 3 is a control block diagram around the CPU.

FIG. 4 is a flowchart showing the main flow of a CPU that controls a facsimile.

FIG. 5 is a flowchart showing standby mode.

FIG. 6 is a diagram showing details of a smoothing section according to the present invention.

FIG. 7 is a flowchart showing the operation of the smoothing section according to the present invention.

FIG. 8 is a flowchart showing the content of creating interpolation data according to the present invention.

FIG. 9 is a time chart showing the operation contents of the smoothing section.

FIG. 10 is a diagram showing the contents of data in the main part of the smoothing section.

FIG. 11 is a diagram illustrating the operation of the present invention.

FIG. 12 is a diagram showing a conventional example and the effects of the present invention.

FIG. 13 is a diagram for explaining a conventional technique.

[Explanation of symbols]

38 is a recording section, 40 is a buffer memory, 41 is a smoothing section, 100 is a 2-line FIFO, 101 is a determination circuit, 102 is an adder, 103 is a selector, 104 is an up/down counter, 105 and 107 are latch circuits, 106
110 is a selector, and 110 is a latch clock control circuit.

Claims (2)

[Claims] 1. An image processing apparatus for converting and recording low resolution image data into high resolution image data, the apparatus comprising: storage means for storing at least two lines of the image data in the sub-scanning direction; is one line at a time n
a reference means for referencing both stored data when the data on the line 1 and the data on the nth line and n+
An image processing device comprising: interpolation means for interpolating data between the first line data based on the first line data, and outputting the high resolution data based on the interpolation data. 2. A resolution conversion method for converting low-resolution image data into high-resolution image data, the method comprising: converting two adjacent lines of the low-resolution image data into image data at the same position in the line direction in each line; A comparison is made to detect a range where the two lines of image data do not match, and if the two lines of data match, the same data as the data of both lines is determined as data between the two lines of data. , for a range where the two lines of image data do not match, data between the two lines is determined based on at least data adjacent on both sides of the detected range, and each of the determined data is A resolution conversion method characterized by outputting data between two lines.