JPH04307521A - Wiring structure for thin film transistor device and its production - Google Patents

Abstract

PURPOSE:To detect and preclude a defect, caused by an electric conductor which drives a thin film transistor(TFT) used for an active matrix liquid crystal display device, in the early stage of a manufacture process. CONSTITUTION:The gate electric conductor 102 and source electric conductor 103 of the TFT are formed on a substrate 101 in the beginning of the manufacture process and in the stage, the defect such as the open circuit, short circuit, etc., of the electric conductors is detected and corrected to form the TFT which is free from the defect caused by the electric conductors. In the early stage of the manufacture process, the electric conductors are inspected, so the cause of the defect is easily narrowed down, a countermeasure is easily taken, and the substantial manufacture cost of each finished article is reducible. Further, the electric conductors are embedded in the substrate, so picture elements are put over the electric conductors, which can be used as light shield belts between the picture elements to eliminate the need for light shield belts on an counter substrate, so panel assembly is facilitated, the aperture rate is improved, and large contrast is obtained.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a wiring structure and manufacturing method for thin film transistors, and in particular, a technique for preventing defects caused by disconnections in wiring and short circuits between wirings in a liquid crystal display device in which a large number of thin film transistors are arranged in a matrix. Regarding.

0002

2. Description of the Related Art Conventionally, active matrix type liquid crystal displays are known in which each pixel arranged in a matrix has a driving element of a thin film transistor. To drive this thin film transistor, it is necessary to input mutually independent source signals and gate signals to the thin film transistor, so it is necessary to wire them three-dimensionally on the same substrate while insulating them from each other. In recent years, as liquid crystal display devices have become larger and more precise, the number of constituent pixels has increased significantly, resulting in an increase in the occurrence of defects and a decrease in the yield of finished products. Defects that reduce yield can be broadly classified into point defects and line defects. Causes of point defects include poor characteristics of thin film transistors and short circuits between ITO and source lines due to poor patterns. Line defects are caused by cross shorts due to defects in the interlayer insulating film such as wire breaks, short circuits, and pinholes. be. As described above, apart from defective characteristics of thin film transistors, many of the causes of decreased yield are defects caused by wiring, and it is necessary to devise a wiring structure.

Until now, in order to prevent these defects from short-circuiting at the cross section, an inverted staggered transistor was used in which the gate wiring was formed first, and the structure of the cross section between the gate line and the source line was improved. In order to reduce defects, the insulating film was multilayered as shown in Figure 3.

0004

[Problems to be Solved by the Invention] However, although the above-mentioned conventional technology can greatly reduce short-circuit defects at cross sections, it is not inspected until after the source wiring is formed in the latter half of the board manufacturing process. If there are many defects and it is difficult to correct them, the time and cost required for manufacturing up to that point will be wasted, and subsequent corrections will also be quite difficult. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a thin film transistor wiring structure in which defects caused by wiring can be detected and corrected at the early stage of the manufacturing process.

[0005]

[Means for Solving the Problems] In the wiring structure of a thin film transistor of the present invention, gate wiring and source wiring are formed at the beginning of the manufacturing process before forming the thin film transistor, and defects caused by the wiring can be detected at the early stage of the process. Features.

[0006]

Embodiment (Embodiment 1) FIGS. 1(a) and 1(b) are a plan view and a sectional view of an embodiment of the present invention.

The wiring structure of the thin film transistor in the embodiment of the present invention is shown in FIG. 1(b). 10
1 is an insulating substrate, 102 is a gate wiring, 103 is a source wiring, 104 is a pixel ITO, and 105 is a gate electrode.

The manufacturing method will be explained below.

First, a gate wiring 102 and a source wiring 103 are formed on an insulating substrate 101 made of glass or quartz, with an interlayer insulating film 106 in between, as shown in FIG. 1(b). In FIG. 1B below, the gate wiring is formed before the source wiring, but the gate wiring may be formed after the source wiring. However, since direct current components are constantly applied to the gate wiring, when applied to a liquid crystal display, there is a possibility of deteriorating the liquid crystal, so it is better to form the gate wiring before the source line and leave the distance to the liquid crystal layer. Good in terms of LCD reliability. Further, in order to prevent line defects due to disconnection, the cross-sectional shape of the first layer wiring is tapered. This is because if it is vertical, abnormal growth tends to occur near the edge or the interface with the substrate when forming an interlayer insulating film, reducing the coverage of the second layer wiring and leading to disconnection. In this example, the gate wiring is formed first, Cr and Al are used as wiring materials for the gate and source, respectively, and the interlayer insulating film is made of Si.
O2 was used. Note that the gate wiring and the source wiring may be made of the same material. In this case, the degree of light shielding does not depend on the type of wiring, which is extremely effective when wiring is used as a light shielding zone. In addition, when adopting laser annealing technology to lower the process temperature, as will be explained later,
It is preferable that the source and gate be made of the same material because the heat for recrystallizing the active layer can be diffused relatively uniformly within the plane, and in-plane variations in the characteristics of the thin film transistor can be suppressed.

Next, wiring patterning will be explained in detail with reference to FIG. FIG. 2 is a schematic diagram showing each manufacturing process of wiring formed on a substrate. First, 150 nm of Cr, which will become a gate wiring, is formed on an insulating substrate by sputtering and patterned by taper etching. Taper etching is performed using cerium ammonia nitrate ((NH4)2[C
The adhesion of the resist at the pattern edges was reduced by adding nitric acid to e(NO3)6 ]). Furthermore, the gate wiring is patterned in a staggered manner as shown in FIG. 2A so that short circuits between adjacent wirings can be easily detected. Furthermore, since the outer periphery of the active area 201 where thin film transistors are arranged in a matrix and where a picture is actually displayed after assembly does not intersect with the gate wiring, the lead-out portion for mounting on the source wiring side is also patterned at the same time. The reason for this is that liquid crystal displays must be assembled with a constant distance (gap) between them and the opposing substrate, and to adjust this distance, a glass fiber with a diameter corresponding to the gap is mixed in the adhesive, and the lead-out wiring around the substrate is adjusted. They are glued together at the top, and it is easier to assemble if the film thickness is the same at the lead-out part, so the lead-out part on the source wiring side is also patterned. Reference numeral 202 denotes a mounting terminal, and the mounting terminals are short-circuited depending on the drawing direction. By inspecting continuity between short-circuited terminals with different lead-out directions, it can be determined whether a short-circuit exists between wires. Reference numeral 203 is an auxiliary terminal for defect detection, and is used to disconnect or short-circuit individual wirings. Next, atmospheric pressure chemical vapor deposition (AP) using monosilane and oxygen as raw material gases was performed.
A 300 nm thick film of SiO2, which will become an interlayer insulating film, is formed at a reaction temperature of 300° C. using the CVD method. Thereafter, contact holes are opened for the mounting terminals and the auxiliary terminals, and then an Al film, which will become the source wiring, is formed by sputtering to a thickness of 400 nm. Subsequently, as shown in FIG. 2(b), Al is patterned to form source wiring and gate/source terminals. Patterning is performed in a staggered manner in the same way as the gate wiring at this time. At this stage, inspect for wire breaks and short circuits between wires. The inspection method is to detect the presence or absence of electrical continuity between the three short-circuited terminals in different lead-out directions and the auxiliary terminals in the remaining directions. Normally, there is continuity only in opposing directions, but if there is a disconnection, there will be no continuity in all three directions, and if there is a short circuit between the gate and source lines, continuity will be detected in one direction in addition to the opposing direction. . After such inspection, only those with no defects and those that can be corrected are sent to the next process, and those with many short circuit defects are recycled by peeling off the second layer wiring and forming a thin film again. By including this inspection step, the yield for proceeding to the next step can be improved.

Next, a method for manufacturing a thin film transistor will be explained with reference to FIG. 1(b). In this embodiment, a top-gate coplanar type thin film transistor using a polycrystalline silicon film with high mobility as an active layer will be described, but the present invention is not limited thereto, and can also be applied to an inverted staggered type thin film transistor. First, SiO2, which will become the base of the thin film transistor, is placed on the substrate that has been processed as described above.
The film 107 is again grown using atmospheric pressure chemical vapor deposition (APCVD).
After that, amorphous Si was formed to a thickness of 300 nm by plasma chemical vapor deposition (P-CVD) at 300°C.
A film with a thickness of 50 nm is formed. Subsequently, the amorphous Si film is irradiated with an excimer laser to crystallize it. When manufacturing thin film transistors, it is important to note that since the metal wiring has already been done, the manufacturing temperature must be kept at 30°C.
It is necessary to keep the temperature below 0°C. Therefore, polycrystalline silicon was obtained by employing a technique of laser annealing amorphous Si at a low temperature. Furthermore, an excimer laser was used because it is extremely effective in annealing thin films such as those described above. Thereafter, the crystallized Si film is patterned, and then a 150 nm thick SiO2 film, which will become a gate insulating film, is formed by ECR plasma chemical vapor deposition, and then a contact hole is formed on the gate wiring. Subsequently, 150 nm of Cr, which will become a gate electrode, is formed and patterned in the contact hole. After that, boron ions are implanted and the source
After forming the drain region 108, the excimer laser is irradiated again to activate the source/drain region. Subsequently, a 200 nm thick SiO2 film 109 is formed by APCVD. Connection 11 with the source wiring even without this insulating film
0 is possible, but a film is formed to prevent short circuits with the gate electrode due to pattern defects. After that, contact holes are opened for the source/drain regions, and the pixel IT
Form O104. Furthermore, after opening a contact hole in the source wiring, Al was formed again by sputtering method.
As shown in 10, the source region and source wiring are connected with Al. The reason why the process of forming the contact hole was divided into two steps is because the film thickness of the part to be opened is different.Since the film thickness of the source/drain region is extremely thin, over-etching is required when etching the contact to the source/drain. Because you can't. Through the above steps, a thin film transistor is formed on the substrate that has been wired in advance.

[0012] The embodiment described here is just one embodiment. (Example 2) The wiring structure described in Example 1 included a step of patterning the interlayer insulating film before forming the second layer wiring. When an insulating film is patterned, holes may be formed in the insulating film, resulting in defects due to penetration of etching solution due to pinholes in the resist, pattern defects due to dust, fluff, etc. Therefore, we also invented a manufacturing method in which the second layer wiring is formed without patterning the interlayer insulating film by etching.

First, the gate wiring Cr serving as the first layer wiring is
After patterning as in Example 1 as shown in FIG. 2(a), an interlayer insulating film of SiO2 is formed by sputtering, covering areas other than the active area 201 in FIG. 2(a). The design rules for the terminal portion are looser than those for the inside of the active area, and patterning by mask sputtering is sufficient since it is sufficient to prevent the insulating film from being formed only at the terminal. After that, a second layer of wiring is formed and patterned. According to this method, the number of defects is reduced, the number of photoetch steps is reduced by one, and the insulating film and the second layer wiring can be formed continuously, so that the through-top is greatly improved.

[0014]

Effects of the Invention The wiring structure and manufacturing method of a thin film transistor according to the present invention has the following excellent effects.

First, since the gate wiring and source wiring are formed at an early stage of the manufacturing process before forming the thin film transistor, it is easy to narrow down the cause of the defect and take countermeasures. Further, even if a defect occurs, the substrate is not sent to the next process, thereby substantially reducing the manufacturing cost per finished product.

Second, since the wiring is embedded inside the substrate, it is now possible to form the ITO constituting the pixel on top of the wiring, and the light shielding body, which was previously provided on the opposing substrate, can be replaced with the gate and source. Since wiring can be used instead, the spacing between pixel ITOs is narrower, allowing for a larger aperture ratio, and at the same time, the control of assembly misalignment between the thin film transistor and the opposing substrate is relatively relaxed, making it easier to assemble the panel. alignment becomes easy.

[0017] Therefore, a defect-free, high-contrast liquid crystal display can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view (a) and a cross-sectional view (b) of an embodiment of the present invention.

FIG. 2 is a schematic diagram of each manufacturing process of a wiring structure.

FIG. 3 is a cross-sectional view of a cross section between a conventional thin film transistor and wiring.

[Explanation of symbols]

101 Insulating substrate 102 Gate wiring 103 Source wiring 104 Pixel ITO 105 Gate electrode 106 Interlayer insulating film 107 Base SiO2 108 Source/drain region 109 SiO2 film 110 Connection with source wiring (Al) 201 Active area 202 Mounting terminal 203 Auxiliary terminal 301 Source Wiring 302 Gate wiring 303 n+ amorphous Si 304 Etching stopper 305 Gate (Ta) 306 Ta2 O5 307 SiNx 308 Amorphous Si

Claims (4)

[Claims] 1. A wiring structure for a thin film transistor device in which a plurality of thin film transistor devices are arranged in a matrix, wherein two layers of wiring, a gate wiring and a source wiring, are formed before forming a thin film transistor. 2. The wiring structure according to claim 1, wherein the gate wiring is formed as the first layer wiring and the source wiring is formed as the second layer wiring, so that the gate wiring is formed before the source wiring. Wiring structure of thin film transistor device. 3. A wiring structure for a thin film transistor device according to claim 1, wherein the gate wiring and the source wiring are made of the same wiring material. 4. A method for manufacturing a wiring structure for a thin film transistor device, comprising forming a second layer of wiring continuously after forming an interlayer insulating film for insulating between wirings in the wiring structure according to claim 1.