JPH0430217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable controller, and more particularly to an input/output data transmission system between a controller main body, an input unit, and an output unit when the input unit and output unit are configured separately from the controller main body.

Recently, relatively large-scale centralized control systems using programmable controllers are often seen in control systems for general mechanical plants and the like. In such a centralized control system,
In many cases, various input devices, such as limit switches, temperature switches, proximity switches, photoelectric switches, etc., and various output devices, such as motors, plungers, solenoid valves, etc., are each connected to a central control device by separate signal lines. In this case, in systems where there are a large number of these input/output devices and each input/output device is distributed over a relatively wide space, the wiring space and wiring cost that connect each input/output device and the central control unit become a major problem. Therefore, there is a strong desire to simplify signal transmission during this time by applying appropriate multiplex transmission.

Various multiplex transmission systems have been known in the past, and some have been used to transmit input/output data in programmable controllers.
However, in the conventional multiplex transmission system, a unique address is assigned to each terminal, and each terminal has a circuit for determining the address, and the transmission control procedure including this address determination circuit is extremely complicated and sophisticated. Therefore, it is an expensive device. Of course, such an advanced circuit system is meaningful, but there are many functions that are unnecessary for the input/output data transmission system in the programmable controller, and as a result, it has not been possible to adequately meet the above-mentioned demands.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to configure the input unit and output unit separately from the controller main body, and to connect the required number of input units and output units in series to the controller main body. By simply connecting all data input terminals and output terminals in series to form a closed loop via one series data line, there is no need for an address discrimination circuit on the input unit or output unit side. To provide an input/output data transmission method for a programmable controller that enables simultaneous transmission of output data from a controller body to an output unit and transmission of input data from an input unit to the controller body without going through a transmission control procedure. It is in.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

Figure 1 shows a programmable system to which this invention is applied.
1 is a block diagram showing the overall schematic configuration of a controller system. FIG. This system is divided into a controller main body 1 and 32 input/output units U1 to U32. The input/output unit is a general term for input units and output units.
In this figure, U1 and U32 are shown as input units, and U2 and U3 are shown as output units. You can connect up to 32 units in total including input and output units. The plurality of input units have exactly the same configuration, and U1 will be explained below as a representative. The plurality of output units have exactly the same configuration, and below, U2 will be explained as a representative.

The input unit U1 has a serial input terminal SI for serial data transmission and a serial output terminal SO in addition to an input terminal to which 8-bit input data IN1 to IN8 are externally applied in columns. In addition, output unit U2 outputs 8-bit output data from OUT9 to OUT1.
6 to the outside in parallel, a serial input terminal SI and a serial output terminal SO for serial data transmission. 32 input/output units U1 to U3
2 are each other's series input terminal SI and series output terminal SO
are connected to each other by a serial data line 2, and the whole is connected in series by a serial data line 2.
Also, the series input terminal SI of the input unit U1 on one end side is the series output terminal of the controller body 1.
It is also connected to SOT by a serial data line 2, and the serial output terminal SO of the input unit U32 on the other end side is connected to the serial input terminal SIT of the controller main body 1 by a serial data line 2. Individual addresses are not set for each of the input/output units U1 to U32, and the numbers U1 to U32 are numbers assigned sequentially from the output terminal SOT side to the input terminal SIT side of the controller main body 1. Similarly, for the 8-bit input terminal of the input unit and the 8-bit output terminal of the output unit, consecutive numbers from 1 to 256 are assigned in order from the output terminal SOT of the controller body 1 to the input terminal SIT. I'm wearing it.

The controller body 1 serves as the center of overall control.
A CPU 3 (central processing unit), a system program memory 4 storing system programs to be executed by the CPU 3, a working memory 5 used as a temporary storage area for various variable data by the CPU 3, and a system program memory 4 that stores system programs executed by the CPU 3; A user program memory 6 in which a set sequence control program is stored, and an input/output memory 7 in which input data taken in from the input unit and output data to be given to the output unit are stored, as will be described later.
Then, serial data containing the output data to be given to the above output unit in a predetermined order is sent to the output terminal SOT.
and a receiving device 9 that operates simultaneously with the transmitting device 8 and receives serial data containing input data in a predetermined order from the input unit applied to the input terminal SIT. .
The transmitting device 8 includes a transmitting buffer memory 10 to which input/output data (including input data and output data) stored in the input/output memory 7 is transferred prior to transmitting the input data. Receiving device 9
has a reception buffer memory 11 for temporarily storing received input/output data. From the received data stored in the receive buffer memory 11, only the input data from the input unit is selected and written to the input/output memory 7 as will be described later.

As is well known, the execution operation of a user program in this type of programmable controller basically involves sequentially reading user instructions from the user program memory 6, and input/output stored in the input/output memory 7 according to each user instruction. It performs logical operation processing between data and updates the output data in the input/output memory 7 according to the result of the operation, and the latest output in the input/output memory 7 is updated every cycle of this user program. An output update operation for transmitting data to a predetermined output unit and an input update operation for writing the latest input data from the input unit to the input/output memory 7 are performed. This creates a sequence state defined by the user program in the relationship between the input data given to the input unit and the output data output from the output unit.

Programmable controller according to the present invention
In the system, once the user program has been executed once by the CSU 3, all input/output data in the input/output memory 7 is transferred to the transmitting buffer memory 10, and only input data is extracted from the data in the receiving buffer memory 11. and write it to the input/output memory 7. At this point, the CPU 3 starts executing the user program. At the same time, the transmitting device 8 and the receiving device 9 operate, and in parallel with the execution of the user program, the output data in the transmitting buffer memory 10 is given to the output unit, and the input data from the input unit is taken into the receiving buffer memory 11. The above operations are repeated.

Furthermore, in the system of the present invention, there are no restrictions on the arrangement order or number of input units and output units, and up to 32 input units and output units in total can be connected. Then, as an initial process when the power is turned on to this system,
Controller body 1 has output terminal SOT and input terminal
During SIT, processing is performed to recognize how many input and output units are connected and in what order. The details of the processing will be described later. Then, the connection state of that unit is recorded in the unit table set in the working memory 5, and during subsequent actual operation, the receiving device 9
Out of the data stored in the buffer memory 11, input data is distinguished by referring to the unit table.

Figure 2 shows input unit U1 and output unit U2.
shows the configuration of The input unit U1 is mainly composed of a transmission circuit 12 consisting of a 1-chip CPU, and also receives 8-bit input data IN1 to IN8 from the outside.
It has an input interface 13 for receiving data. An 8-bit serial buffer register SBR is set in the RAM area of the transmission circuit 12.
This register SBR essentially functions as an 8-bit shift register during the above-mentioned serial data transmission. The above serial data transmission is performed in a closed loop connecting the controller main body 1 and each input/output unit.
This is performed in units of 8 bits using a so-called start-stop synchronization method. The transmission circuit 12 detects the start bit applied to the input terminal SI, generates the internal clock CK, receives the 8-bit serial data sequentially supplied, and shifts the data sequentially from one end of the serial buffer register SBR. The input receiving means and the above-mentioned serial buffer register simultaneously with the operation of this receiving means.
It has transmitting means for transmitting serial data sequentially shifted and output from the other end of the SBR from the output terminal SO. Furthermore, the transmission circuit 12 stores the serial buffer register in each cycle of the serial data transmission, that is, each time the transmission of 36 units is completed.
The SBR has input data reading means for storing N-bit input data IN1 to IN8 inputted via the input interface 13 in parallel. Furthermore, to create the unit table mentioned above,
The input unit U1 has initial setting means for storing a predetermined input unit identification code in the serial buffer register SBR as an initial process when the power is turned on.

The output unit U2 mainly includes a transmission circuit 14 composed of a 1-chip CPU similar to the input unit U1, and outputs 8-bit output data OUT9 to OUT16.
It has an output interface 15 for outputting the data to the outside in parallel. Transmission circuit 14 includes a serial buffer register SBR that essentially functions as an 8-bit shift register for output data transmission. The transmission circuit 14 detects a start bit applied to the input terminal SI, generates an internal clock CK, receives serial data sequentially applied, and sequentially shifts input data from one end of the serial buffer register SBR. and the serial buffer register mentioned above at the same time as the operation of this receiving means.
It has transmitting means for transmitting serial data sequentially shifted and output from the other end of the SBR from the output terminal SO. In addition, the transmission circuit 14 connects the serial buffer register SBR for each cycle of the serial data transmission.
The 8-bit data stored by the shift input is read out and supplied in parallel to the output interface 15, and these data are output as output data OUT9.
It has output data reading means for outputting to the outside as OUT16. Furthermore, in order to create the unit table, the transmission circuit 14 has an initial setting means for storing a predetermined output unit identification code in the serial buffer register SBR as an initial process when the power is turned on.

As is clear from the above explanation, when 256-bit serial data for 32 units is transmitted from the transmitter 8 of the controller main body 1, the data is sent to the serial buffer register SBR in each input/output unit U1 to U32 in the order in which it is sent. Each number of input/output data is stored in reverse correspondence. At the same time, each input/output unit U1 is
A total of 256 bits of data stored in the serial buffer register SBR in ~U32 is input to the receiving device 9 of the controller body 1 in the numerical order of input/output data from "256" to "1". Therefore, when transmitting data from the transmitting device 8, if the output data to be given to the output units is transmitted in a predetermined order, the data will be stored in the serial buffer register SBR in the required output unit, and then the output data will be stored in the serial buffer register SBR in the required output unit. The purpose is achieved by outputting the data to the outside via the output interface 15. Further, if input data is read into the serial buffer register SBR via the input interface 13 prior to transmission, the input data is taken into the receiving device 9. Furthermore, as the initial processing at power-on described above, the input unit identification code and output unit identification code are stored in the serial buffer register SBR of the input unit and output unit, respectively, so these identification codes are stored at the time of the first serial data transmission. The code is supplied to the receiving device 9, and the CPU 3 of the controller main body 1 uses the identification code to determine in what order the input units and output units are connected in series between the output terminal SOT and the input terminal SI. Based on this, a unit table is created that indicates whether each unit is an input unit or an output unit.

FIG. 3 is a flowchart showing an outline of the operation of the CPU 3 of the controller body 1, FIG. 4 is a flowchart showing an outline of the operation of the transmitter 8 and the receiver 9, and FIG. This is a flowchart showing an outline of the operation of the unit. The overall operation of the above system will be explained below by linking these flowcharts.

When the power is turned on to this system, the above-mentioned unit table is created as part of the initial processing, but the operation will be described later. First, let me explain it as if it were. In the initial state, output data to be supplied to each output unit is stored in the transmission buffer memory 10 in a predetermined order. In this state, the CPU 3 executes step 302,
A data transmission start command is issued to the transmitting device 8 and the receiving device 9, and then the CPU 3 executes step 30.
Proceed to step 3 to enter the user program execution routine. On the other hand, the transmitting device 8 is also
Upon receiving the transmission start command from CPU3, step 4
Proceed to step 03 to execute the data transmission routine and send the data in the transmission buffer memory 10 to the output terminal in order.
Send to SOT. At the same time, in the receiving device 9, the CPU
3 is detected in step 410, the program proceeds to a data reception routine in step 411, and stores the received data sequentially applied to the input terminal SIT in the reception buffer memory 11. Transmitting device 8
The data transmission routine of step 403 is 32
This is done for the unit's worth of data. Further, if a data transmission error is detected in the received data during the data reception routine of the receiving device 9, an error flag is set and this is notified to the transmitting device 8 and the CPU 3.

On the other hand, the input unit and the output unit operate simultaneously as the transmitting device 8 starts the transmitting operation. The input/output unit executes step 502 and waits for a start bit to be applied to input terminal SI. When the start bit is detected,
Proceeding to step 503, an input/output operation is performed in which the supplied 8-bit serial data is sequentially shifted using the serial buffer register SBR. In the next step 504, it is determined whether data transmission for 32 units has been completed, and until 32 units have been transmitted, the process returns to step 502 and waits for a start bit prior to the next 8-bit transmission. When the data transmission for 32 units is completed, the input unit receives the 8 data input via the input interface 13 in step 505.
The bit input data is preset in parallel to the serial data SBR, and the process returns to the first step 502. Similarly, the output unit returns to step 502. Similarly, in step 505, the output unit stores the serial buffer register at the end of data transmission.
The 8-bit output data remaining in the SBR is output to the outside via the output interface 15,
Then, the process returns to the first step 502.

In the transmitting device 8, when the data transmission for 32 units is completed in step 403, the process proceeds to step 404.
In step 405, it is determined whether the data transmission was successful or not. If it is normal, it is determined in step 405 whether there was a transmission error.
It has the ability to handshake with CPU3. When receiving device 9 finishes receiving data for 32 units in step 411, it proceeds to step 412, notifies CPU 3 of the end of data transmission, and then waits for handshake with CPU 3 in step 413.

After executing the user program once in step 303, the CPU 3 waits until it is notified of the end of data transmission from the receiving device 9 in step 304. When receiving a data transmission end notification from the receiving device 9, the process proceeds to step 305, where it is determined whether there is a notification of loop breakage from the transmitting device 8, and if not, in step 306, whether there is a notification of a transmission error from the receiving device 9. If not, proceed to step 307. In step 307, handshake is performed with the transmitter 8 to enable input/output data transfer. As a result, the transmitting device 8 performs step 4.
06 is determined as YES, and the process advances to step 407. On the other hand, the CPU 3 proceeds to step 308, and sequentially transfers the input/output data (only the output data, or the entire data) of the input/output memory 7 to the transmitting device 8 side. In the transmitting device 8, in step 407
It receives input/output data from the CPU 3 and stores it in the transmission buffer memory 10. The transmitter 8 then returns to step 402 and waits for the CPU 3 to issue a transmission start command. Next, the CPU 3 proceeds to step 309 and performs handshake with the receiving device 9 to enable data transmission. As a result, in the receiving device 9, in step 413,
If the answer is YES, the process advances to step 414. In step 414, the received data stored in the receive buffer memory 11 is transferred to the CPU 3 in order.
The CPU executes step 310, receives data from the receiving device 9, selects only input data from the data, and stores it in a predetermined area of the input/output memory 7. After executing step 414, the receiving device 9 returns to the first step 410 and waits for a transmission start command from the CPU 3.

The CPU 3 selects input data from the data transmitted from the receiving device 9 in step 310, and at this time the above-mentioned unit table is referred to. Details of this step 310 are shown in FIG. 3C. In other words, step 317
At step 318, the unit address register UAR for specifying the unit address corresponding to each input/output unit individually is cleared, and at the next step 318, the first 8 bits of data are fetched from the receiving device 9.
In the next step 319, the unit address register is
The identification code is read for the unit in the unit table indicated by UAR, and it is determined in step 320 whether or not the identification code is the input unit identification code. If it is not an input unit, the unit address register UAR is incremented by 1 in step 323, and the process returns to the data acquisition routine in step 318. Steps 319 and 320 are then executed, and if the input unit identification code is detected, the process proceeds to step 321, where the captured 8-bit input data is stored in a predetermined area of the input/output memory 7. Then step 3
At step 22, it is determined whether or not 32 units have been completed, and the above processing is repeated via step 323 until the end. When 32 units have been completed, this input acquisition ends.

When the CPU 3 finishes the processing in step 310 described above, it returns to step 302 and issues a data transmission start command to the transmitting device 8 and receiving device 9. This causes the above-described operation to be repeated.

Next, the process of creating a unit table as part of the initial process will be explained. As an initial process in the first step 501, the input unit and the output unit respectively preset the input unit identification code or the output unit identification code in the serial buffer register SBR. Further, as part of the initial processing 401 in the transmitting device 8, the transmitting buffer memory 10 is cleared. The CPU 3 creates a unit table as part of the initial processing 310. The unit table creation routine is shown in FIG. 3B. First, in step 311, the transmitter 88 and the receiver 9
A data transmission start command is issued to the next step 31.
At step 2, the device waits for a notification of completion of data transmission from the receiving device 9. Upon receiving this, the transmitting device 8 and the receiving device 9
As a result, the above-described serial data transmission is carried out, and as a result, all the unit identification codes preset in the serial buffer register SBR of the input/output unit are taken into the receiving buffer memory 11 of the receiving device 9. When the data transmission is completed, the CPU 3 first performs handshake with the receiving device 9 in step 313, receives the unit identification code received from the receiving device 9 in step 314, and sequentially stores it in the unit table in the working memory 5. Next, in step 315, handshake is performed with the transmitter 9, and in step 316, data of all "0" is passed to the transmitter 8. This completes the unit table creation routine.

As explained in detail above, according to the input/output data transmission method of a programmable controller according to the present invention, the required number of input units and output units within the limit number can be transmitted to the controller body using one series of serial data lines. By simply connecting them all in series to form a closed loop, there is no need to set an address on the input/output unit side, and there is no need for a control circuit to determine the address on the input/output unit side. Output data transmission from the controller main body to each output unit and input unit transmission from each input unit to the controller main body can be performed simultaneously by wire. That is,
The configuration of the transmission control portion of each input/output unit is extremely simple and can be manufactured at low cost. In addition, when adding input/output units, simply add them in series within the transmission loop, and the controller itself automatically recognizes the order in which input and output units are placed within the transmission loop. Since this is done, there is no need for the user to take any troublesome measures to add or reduce the number of input/output units. Of course, the above-mentioned transmission loop only requires one system of transmission line, and it goes without saying that the installation of the transmission line is very simple and inexpensive.

[Brief explanation of drawings]

Figure 1 shows a programmable system to which this invention is applied.
Figure 2 is a block diagram showing the schematic configuration of the controller system. Figure 2 is a block diagram showing the structure of the input unit and output unit. Figure 3 is a diagram of the controller main body.
FIG. 4 is a flowchart showing the operation of the CPU, FIG. 4 is a flowchart showing the operation of the transmitting device and receiving device of the controller body, and FIG. 5 is a flowchart showing the operation of the input unit and output unit. 1... Controller body, U1 to U32... Input unit or output unit, 2... Series data line, SOT... Output terminal, SIT... Input terminal,
SI...Input terminal, SO...Output terminal, SBR...Serial buffer register, IN1 to IN8...Input data, OUT9 to OUT16...Output data.

Claims (1)

[Claims] 1. An input unit to which N bits of input data are given in parallel from the outside and an output unit to derive N bits of output data to the outside in parallel are each configured separately from the controller main body, and a plurality of units are provided. The input unit and output unit of the controller are all connected in series to form a closed loop via a serial data line between the serial data output terminal and the serial data input terminal of the controller body; each of the input unit and output unit is N
A bit serial buffer register, a receiving means for receiving serial data applied to an input terminal via the serial data line, and sequentially shifting and inputting the serial data from one end of the serial buffer register, and operation of the receiving means. At the same time, the input unit includes transmitting means for outputting serial data sequentially shifted and outputted from the other end of the serial buffer register from an output terminal to the serial data line;
The above N is stored in the above serial buffer register every cycle.
The output unit has input data reading means for storing bit input data in parallel, and initial setting means for storing a predetermined input unit identification code in the serial buffer register as an initial process; 1
output data reading means for reading N-bit data stored in the serial buffer register by the shift input in each cycle and outputting it in parallel as the output data; The controller main body has an initial setting means for storing an output unit identification code; the controller main body has a transmitting means for transmitting serial data including output data to be given to the output unit in a predetermined order from the output terminal;
Receiving means for receiving and temporarily storing serial data containing input data from the input unit in a predetermined order applied to the input terminal simultaneously with the operation of the transmitting means, and transmitting the serial data for the first time as an initial process. initial setting means for creating a unit table based on identification codes of the input unit and output unit received by the receiving means; and received data temporarily stored in the receiving means for each cycle of the serial data transmission. An input/output data transmission system for a programmable controller, characterized in that it has an input data selection means for selecting and extracting input data from the unit table by referring to the unit table.