JPH04296187A - Scramble system - Google Patents

Abstract

PURPOSE:To send schedule information to a receiver side so that the operation of a peripheral equipment at a receiver side is implemented under accurate time management in the scramble system provided with a system computer and scramblers. CONSTITUTION:The scramble system is provided with a system computer 1 receiving subscriber information and schedule information or the like from an authorization center computer and scramblers 2, 3 applying scramble processing to a video input signal VDIN and an audio input signal AUDIN in response to the schedule information from the system computer 1 and sending the resulting signal. A system computer 21 sends the schedule information controlling the operating time of the peripheral equipment of a receiver side to the scramblers 2, 3 so that the information is inserted in a control data area in a BS format and the result is sent from the scramblers 2, 3 together with an audio signal. The scramblers 2, 3 insert the schedule information for the peripheral equipment control into a control data area in the BS frame the same as that for the audio signal or the like based on the command of the system computer 21 and output the result.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scrambling system that uses a communication satellite or the like to perform predetermined scrambling processing on video and audio signals depending on the destination (subscriber or customer).

0002

[Prior Art] As a system that performs scrambling processing on video and audio signals for each subscriber so that only authorized subscribers can receive them effectively, for example, a satellite communication (C/S) scramble system is used. and descrambler systems are known.

FIG. 6 shows a partial configuration of a conventional C/S scrambler system on the transmitting side, and FIG. 7 shows a partial configuration of a C/S descrambler system on a receiving side. This C/S scramble system consists of an authorization center computer 11 that manages subscriber registration, changes, etc.
Subscriber information and scrambled information from MO
System computer 1 receiving via DEM etc.
21, a scrambler 13, and a sending device 14 for sending video signals, audio signals, and digital signals to the scrambler 13. A video signal scrambled by a scrambler 13 is radiated to a communication satellite via an uplink 15 and an antenna 16. Figure 7
The C/S descrambler system shown in FIG.
Descrambler 23 that descrambles the signal from 2
have. The video signal VIDEO and audio signal AUDIO decoded by the descrambler 23 are sent to the TV receiver 24 and speaker 25 of the authorized subscriber. Further, the signal is sent from the descrambler 23 to a peripheral device control circuit 26 such as a VTR device, and is outputted to the VTR device or the like.

0004

[Problems to be Solved by the Invention] In FIG. 6, control information for operating peripheral devices such as a TV receiver 24 and a VTR device on the receiving side, which is sent from the system computer 12 to the scrambler 13, is sent from the authorization center in advance. - Registered in the computer 11 and stored in the memory of the system computer 12, for example, a hard disk drive (HD). When the system computer 12 receives this information from the authorization center computer 11, it temporarily stores it in the HD and
When outputting information to the corresponding subscriber, it is read from the HD and output to the scrambler 13. The scrambler 13 receives such information from the system computer 12, temporarily stores it in memory, and after scrambling the video signal, audio signal, etc., also sends the information to the uplink 15. However, a time delay occurs between reading the peripheral device control signal from the HD in the system computer 12 and transmitting it from the scrambler 13 to the uplink 15. The time delay elements include the time D1 for downloading from the HD in the system computer 12, the time D2 for receiving it on the scrambler 13 side, storing it in memory, and putting it on air, and the time V1 for shuffling and formatting the video signal. be. Also, Figure 7
In the C/S descrambler system shown in
In the descrambler 23, the sending time D3 for deinterleaving, error correction processing, format decoding, etc.
, a time delay such as a delay time V2 for deshuffling and deformatting the video signal occurs. As a result, peripheral devices cannot be operated under accurate time management. In particular, video signals, audio signals, etc. are sent from the sending device 14 to the scrambler 13, and the scrambler 13 performs predetermined scrambling processing, but due to the above-mentioned time delay,
The temporal correspondence between the video signal and the audio signal is out of sync, causing problems such as peripheral devices not operating even though the video signal and audio signal are being received on the receiving side.

[0005]

[Means for Solving the Problem] In order to solve the above problem, we have provided a system computer that receives information from a center computer that performs subscriber registration, etc., and a system computer that receives information from the system computer that inputs video and audio signals. In the scrambling system of the present invention, which has a scrambler that performs scrambling processing based on information and performs scrambling processing on video signals and audio signals depending on the destination, the system computer controls a format that is compatible with the BS format. Using the data area, schedule information that controls the operation of peripheral devices on the receiving side is sent to the scrambler, and the scrambler inserts the received schedule information into the control data area of the BS format, such as audio information, etc. output at the same time.

[0006]

[Operation] Schedule information is sent to the BS along with audio signals, etc.
Since it is inserted into the format and transmitted, it is possible to control the operation of peripheral devices on the receiving side under accurate time management on both the sending and receiving sides.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of a C/S scrambling system as an embodiment of the scrambling system of the present invention. This C/S scrambling system corresponds to FIG. The C/S scramble system includes a system computer 1 connected to an authorization center computer (not shown) that manages subscriber registration, changes, etc., via MODEM, for example. first scrambler 2
and a second scrambler 3, these scramblers 2,
3, video input signal VDIN, audio input signal AUDIN
, a sending device 4 that outputs digital input data DGDTIN, and further monitors the operating states of the first scrambler 2 and the second scrambler 3 to determine whether the scrambler 2 is normal.
Alternatively, the switching circuit 5 sends the scrambled video signal and audio signal from 3 to the uplink. The first scrambler 2 and the second scrambler 3 have the same device configuration, and have a duplex system configuration to improve system reliability. The circuit configuration of the first scrambler 2 is shown in FIG. 1st
The scrambler 23 includes a video circuit 2A and a control device 2B.
, an audio/PSK circuit 2C, and a PCM circuit 2D.

[0008] The video circuit 2A is an A/D converter 2A.
1, frame memory 2A2, video control circuit 2A3, D
/A converter 2A4. The A/D converter 2A1 converts the video input signal VDIN into a digital signal, and the frame memory 2A2 converts the video input signal VDIN into a digital signal.
Remember DIN. The video control circuit 2A3 is composed of a microcomputer, and is a control circuit 2B in the control device 2B.
1 to control the video signal. The D/A converter 2A4 converts the signal-processed digital signal format video signal into an analog signal format, and converts the video signal VD2 into an analog signal format.
Output as . The control device 2B includes a control circuit 2B1, RAM 2B2 and H
It has D2B3. The control circuit 2B1 and the system computer 1, for example, RS230C or SCS
The system computer 1 inputs subscriber information, its scramble information, schedule information, etc., and stores it in the HD2B3. The control circuit 2B1 sends a scramble signal to the video control circuit 2A3.
Outputs schedule information and other processing signals. Furthermore, the control circuit 2B1 monitors the operation of the video control circuit 2A3.

The audio/PSK circuit 2C includes A/D converters 2C1 and 2C2, which convert two types of audio input signals AUDIN1 and AUDIN2 into digital signals, respectively.
And, it has a 4-phase PSK modulator 2C3. PCM
Circuit 2D includes selector 2D1, multiplexer 2D2, B
CH・SEL2D3, BCH・SEL2D3, and
It has a differential converter 2D4. Selector 2D1 receives audio input signal A from A/D converters 2C1 and 2C2.
Select UDIN1 and AUDIN2. The selected audio input signal AUDIN is the digital input data DGD.
The signals from TIN and control circuit 2B1 are multiplexed in multiplexer 2D2. The output of the multiplexer 2D2 is a bit stream BS2 based on the audio A/B mode control signal A/BCNT at the BCH/SEL 2D3. The bit stream BS2 is further subjected to differential conversion in a differential converter 2D4, and is converted into a 4-phase PSK signal in a 4-phase PSK modulator 2C3.
It is modulated and output as a subcarrier SUBCR.

FIG. 3 shows the A-mode BS format. The basic format of control data is an address signal for decoding control, an SDA signal for video shuffling data, and a synchronization flag signal PFLG for data scrambling (decoding). The address signal defines the word and frame defined by the word sync (synchronization) and frame sync signals called address word and address frame, and defines the address format. The address regulations are 5.
Five formats are available for transmitting different information.
There are ORMAT1 to FORMAT5. FORMAT1
is a word containing a frame sync pattern, defines keys, parameters, etc., and transmits decoder common information. FORMAT2 transmits video and audio authorization information. FORMAT3 transmits authorization information for independent audio and independent decoders. FORMAT4 transmits message information. FORMAT5 transmits service bit information and defines a decoder common information transmission format.

FIG. 4 shows an example of schedule information transmitted using the control data area in the BS format shown in FIG. 3. FIG. 4A shows the name of the source peripheral device, the year, month, day, and time (hour, minute, second) when its operation started, and the year, month, day, and time when its operation ended. Figure 4(b)
, (c) also indicates the operation schedule and mode of the source peripheral device. Such schedule information is created by the authorization center computer 11 shown in FIG.
will be sent to. System computer 1 is its own HD
Remember it. The system computer 1 then inserts the schedule information into the control data area of the BS format shown in FIG.
It instructs the first scrambler 2 and second scrambler 3 to output.

Control circuit 2B1 in first scrambler 2
receives the schedule information from the system computer 1, stores it in the HD2B3, outputs it to the video control circuit 2A3, processes it in the video circuit 2A,
When setting the signal to the BS format shown in Figure 3,
Schedule information is inserted into the control data area of BS format. Similar processing is performed in the second scrambler 3 as well. First scrambler 2 and second scrambler
The scrambler 3 outputs the same scrambled audio signal, video signal, and the above schedule information, but the switching circuit 5 selects these signals from the normally operating scrambler and uploads them. Send to link. As a result, the schedule information is sent from the sending device 4 to the receiving side together with the audio signals input to the first scrambler 2 and the second scrambler 3, and peripheral devices on the receiving side are specified by the schedule information. It operates under the specified schedule conditions. The above schedule information also includes time information generated on the sending side, so that the receiving side and the sending side use the same clock to accurately manage time. In this way, it is possible to centrally control the scheduled operation of peripheral devices on the receiving side on the sending side. It also controls the operation of peripheral devices under accurate time management without being affected by time delays within the system computer 1, first scrambler 2, second scrambler 3, or time delays on the receiving side. be able to.

FIG. 5 shows the BS format of B mode. Also in this BS format, the schedule information shown in FIG. 4 is inserted into the control data area and sent to the receiving side.

[0014]

[Effect of the invention] As described above, according to the present invention,
By inserting schedule information for time management of the operation of peripheral devices on the receiving side into the control data area of the BS format on the sending side and transmitting the data together with audio signals, etc., it is possible to avoid delays in operation time on the sending and receiving sides. It is possible to manage the operation of peripheral devices under accurate time management on the receiving side, without being affected by other factors. Since such schedule management is performed centrally on the transmitting side, schedule management for all peripheral devices on the receiving side can be performed accurately and efficiently.

[Brief explanation of the drawing]

FIG. 1 is a partial configuration diagram of a C/S scrambling system as an embodiment of the scrambling system of the present invention.

FIG. 2 is a circuit configuration diagram of the scrambler shown in FIG. 1.

FIG. 3 is an A-mode BS format diagram used in the embodiment of the present invention.

FIG. 4 is a diagram showing schedule information inserted into the control data area of FIG. 3;

FIG. 5 is a diagram of a B-mode BS format used in the embodiment of the present invention.

FIG. 6 is a partial configuration diagram of a conventional C/S scrambling system.

FIG. 7 is a partial configuration diagram of a conventional C/S descrambling system.

[Explanation of symbols]

1...System computer, 2,3...Scrambler, 4...Sending device, 5...Switching circuit 2A...Video circuit, 2B...Control device, 2C...Audio/PSK circuit, 2D...PCM circuit

Claims (1)

[Claims] [Claim 1] A system computer that receives information from a center computer that performs subscriber registration, etc., and a scrambler that inputs video and audio signals and performs scrambling processing based on the information from the system computer. In a scrambling system that scrambles video and audio signals according to the destination, the system computer controls the operation of peripheral devices on the receiving side using a control data area with a format compatible with the BS format. A scrambling system characterized in that schedule information to be controlled is sent to the scrambler, and the scrambler inserts the received schedule information into a control data area of a BS format and outputs it simultaneously with audio information and the like.