JPH04293241A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To shorten manufacturing time, reduce cost as compared with the conventional IG method, lengthen gettering action, and reduce wafer contamination during a gettering process as compared with the conventional EG method, regarding a semiconductor substrate manufacturing method using gettering action. CONSTITUTION:The following are provided; a process wherein an amorphous layer 2 is formed in a semiconductor substrate 1 by ion implantation, and a process wherein a residual defect layer 3 is formed by heat tratment of rapid thermal annealing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for gettering contaminants such as heavy metals and compounds in a method of manufacturing a semiconductor single crystal substrate.

0002

2. Description of the Related Art In semiconductor technology, process miniaturization is progressing more and more, and contamination caused by the process and associated malfunction of elements have become important problems. Gettering is a technique that stabilizes device characteristics and improves yield by diffusing contaminants outside the device formation region. Conventional gettering techniques can be broadly classified into two types. One is intrinsic gettering (hereinafter abbreviated as IG method. For example, JP-A-63-51
646), which utilizes the precipitation of interstitial oxygen contained in the CZ single crystal. The other method is extrinsic gettering (hereinafter abbreviated as EG method).
This is a method called ``reference method'' (described in Japanese Patent Application No. 33), in which gettering is performed by mechanically damaging the substrate.

The above-mentioned IG method requires a technique for successfully depositing interstitial oxygen present in the substrate outside the device formation region. Usually, this is carried out by combining two heat treatments: precipitation nucleation by low-temperature heat treatment and nucleation by high-temperature heat treatment, but since low-temperature heat treatment lasts for several tens of hours, there are problems in terms of manufacturing time, man-hours, and cost. Furthermore, since the oxygen concentration in the pulled single crystal ingot varies, to obtain a similar effect for all substrates,
Highly controlled pulling and heat treatment techniques are required. Conversely, it is difficult to stabilize the effect. However, since no external processing (film formation, etc.) is performed, it can be said to be a clean technology.

On the other hand, the EG method uses mechanical damage caused by sandblasting, phosphorus diffusion, ion implantation, poly-Si and Si3
This is a method in which the semiconductor substrate is mechanically damaged or dislocated due to stress by depositing N4 on the back surface, and heavy metals are gettered onto the dislocations or damage by the Cottrell effect. This EG method is easy to perform and the effect is stable at first, but as the heat treatment is performed during the element formation process, the damage is recovered and the gettering effect does not last long. There is a drawback. Therefore, creating damage that is difficult to recover from by heat treatment is an important factor in the EG method. In addition, in the case of the EG method, which is performed by forming a poly-Si or Si3N4 layer, the film is formed not only on the back side but also on the front side, so subsequent steps of peeling and cleaning are required, which increases the number of steps. Not only that, but it is also a method that is vulnerable to contamination.

[0005]

[Problems to be Solved by the Invention] As mentioned above, the conventional IG method has problems in terms of manufacturing time, man-hours, and cost, and requires highly controlled pulling technology and heat treatment technology. The problem is that it is difficult to stabilize the Furthermore, in the conventional EG method, (1) in the case of a method based on mechanical damage or ion implantation damage, the damage is quickly recovered by heat treatment during the element formation process, and gettering does not last long. ■Poly-Si and Si3N
The method of forming four layers had a problem in that element characteristics deteriorated due to residual damage and contamination caused by surface treatment.

[0006] The present invention was made to solve the problems of the prior art as described above, and the manufacturing time is significantly shorter and the cost is lower than that of the conventional IG method.
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate with a gettering effect, in which the gettering effect lasts longer than in the conventional EG method, and the wafer is less contaminated during the gettering process.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the present invention, after performing high concentration ion implantation into a semiconductor substrate to form an amorphous layer, rapid thermal annealing is performed.
By performing rapid annealing (hereinafter abbreviated as RTA), many residual defects are left at the amorphous-crystalline interface, and these residual defects become the core of the getter sink.

[0008]

[Operation] The residual defects formed at the interface between the amorphous layer and the crystalline layer by the above process are not recovered even by subsequent process heat treatment because secondary defects grow. Therefore, the gettering effect lasts for a long time. In addition, ion implantation and R
Since only TA is performed, wafer contamination during the getter process is reduced compared to other EG methods.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing the steps of an embodiment of the present invention. In FIG. 1, first, as shown in (a), a Si single crystal substrate 1 is prepared. As this single crystal substrate 1, in the case of a large diameter wafer, a substrate made by the CZ method is generally used. Next, as shown in (b), from the back side of the single crystal substrate 1, group IV elements such as Si and C, dopants of the same conductivity type as the substrate, for example, in the case of an n-type substrate, large and heavy elements such as Sb+ and As+ ( The amorphous layer 2 is formed by ion-implanting ions such as P (possibly even P). Next, (c)
As shown in the figure, RTA (Rapid Thermal A
nnealing). Temperature is 900℃~110℃
The temperature is about 0°C and the time is about several tens of seconds. As a result, a residual defect layer 3 remains at the interface between the amorphous layer 2 and the crystalline layer. Also, (d
), the subsequent process heat treatment also resulted in 2
Due to the growth of the secondary defect layer 4, the remaining defects are not easily recovered.

Next, the operation will be explained. Gettering is the reverse concentration diffusion of substances that exist in a nearly uniform state, and to do this, Cottrell
ell) effect is used. The Cottrell effect is that heavy metals such as Cu and Fe are attracted to the strain field formed by dislocations. Therefore, how to efficiently form and stabilize dislocations is important in gettering, especially in the case of the EG method. When ions are implanted into a silicon substrate, the implanted ions collide with Si atoms at lattice sites, damaging the silicon substrate. If the implantation amount is small, the defects will be point defects, but as the implantation amount increases, they will become cluster-like, reaching the critical dose (~5×101 for Si+).
4/cm2) or more, it becomes amorphous (2 in FIG. 1). RTA is performed on the wafer in this state. The temperature is 900
The temperature is about ~1100°C, and the time is about several tens of seconds at most. When such RTA is performed, residual defects (3 in FIG. 1) remain between the amorphous layer and the crystalline layer. This is because recrystallization proceeds randomly due to rapid and short-term heat treatment, leaving defects near the interface. Such defects are difficult to eliminate even by subsequent heat treatment, and remain continuously during the element formation process. Interstitial oxygen is attracted to the strain field generated near this defect and precipitates SiO2. The interstitial silicon generated by this is the OS
F(Oxidation Induce Stacki)
ng Fault: oxidation-induced stacking fault). These defects collectively act as a getter sink and cause heavy metals to getter. In particular, it acts as a powerful getter sink in the miniaturization process where the process temperature is becoming lower. As a result of the above process, we were able to reliably getter the contaminants in the element formation area.
The breakdown voltage characteristics of the formed device were improved. In particular, the breakdown voltage failure of n-channel devices was significantly reduced from 60% to 5%, and a clear effect could be confirmed.

FIGS. 2 and 3 are electron micrographs (magnification approximately 23,000 times) of the crystal structure inside an actual silicon substrate.
2, ions are implanted into the silicon substrate 1 and RTA is performed.
FIG. 3 shows an electron micrograph of a cross section of the wafer after the heat treatment. The residual defect layer 3 is clearly shown in FIG. 2, and the secondary defect layer 4 is clearly shown in FIG.

Next, FIG. 4 is a sectional view showing the manufacturing process of another embodiment of the present invention. In this embodiment, the amorphous layer 2 is formed at a deep position from the back surface by performing ion implantation for forming the amorphous layer at a high energy of about several MeV. In this way, the interface between the amorphous layer 2 and the crystal layer is 2
Two residual defect layers 3 and 3' are formed by performing RTA. Therefore, more getter sinks can be created, and a stronger gettering effect can be provided. In addition, by deeply implanting ions, there is an effect of bringing the getter sink and the element formation region closer together, which also makes it possible to obtain a stronger gettering effect.

Next, FIG. 5 is a sectional view showing the manufacturing process of a third embodiment of the present invention. In this embodiment, an amorphous layer 2 is formed deep on the surface of a silicon substrate 1 by ion implantation with high energy of about several MeV from the surface, and two residual defect layers 3 are formed by RTA. 3'. By forming the getter sink under the element formation region on the substrate surface in this manner, the distance between the getter sink and the element formation region can be further reduced.

[0014]

[Effects of the Invention] As explained above, in the present invention, an amorphous layer is formed in a semiconductor substrate by ion implantation,
After that, a heat treatment using rapid thermal annealing is performed to form a residual defect layer, which makes it difficult for the defect layer to be recovered by heat treatment during the subsequent device formation process, compared to the conventional EG method. The gettering effect lasts for a long time. ■Compared to the IG method, it can be done in a much shorter time, so costs can be reduced, and it is more stable than the IG method. ■ Wafer contamination during the getter process is less compared to other EG methods. Excellent effects such as these can be obtained. Further, in the embodiment shown in FIG. 4, since there are two defective layers, the gettering effect becomes stronger. Further, in the embodiment shown in FIG. 5, since the getter sink and the element formation region are located close to each other, the effect that the gettering effect becomes even stronger can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a first embodiment of the present invention.

FIG. 2 is a diagram showing an electron micrograph of the crystal structure inside the silicon substrate after RTA.

FIG. 3 is a diagram showing an electron micrograph of the crystal structure inside the silicon substrate after heat treatment.

FIG. 4 is a sectional view showing the manufacturing process of a second embodiment of the present invention.

FIG. 5 is a sectional view showing the manufacturing process of a third embodiment of the present invention.

[Explanation of symbols]

1...Silicon substrate 2...Amorphous layer 3, 3'...Residual defect layer 4...Secondary defect layer

Claims (1)

[Claims] 1. A step of forming an amorphous layer on a semiconductor substrate by ion implantation, and a step of forming a residual defect layer by subjecting the semiconductor substrate to heat treatment by rapid thermal annealing. A method for manufacturing a semiconductor substrate, comprising the step of gettering contaminants that worsen the quality of the semiconductor substrate using the residual defect layer.